From a783791193149f0f6261cd977939b5ffe1b4edd8 Mon Sep 17 00:00:00 2001 From: Jorge Ferreira Date: Tue, 25 Aug 2026 14:21:24 +0000 Subject: [PATCH 1/4] Tighten timing constraints on swerv_wrapper, coyote and jpeg Shorten the clock periods, and the matching input delays, so these designs land with negative slack instead of slack to spare. swerv_wrapper also moves to 55% core utilization and NLDM libraries. Signed-off-by: Jorge Ferreira --- flow/designs/asap7/swerv_wrapper/config.mk | 5 +- .../asap7/swerv_wrapper/constraint.sdc | 6 +- flow/designs/gf12/coyote/constraint.sdc | 1570 ++++++++--------- flow/designs/sky130hs/jpeg/constraint.sdc | 2 +- 4 files changed, 792 insertions(+), 791 deletions(-) diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index f5b1745e48..77bdc1800d 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -42,7 +42,8 @@ export SYNTH_KEEP_MODULES ?= \ ram_256x34 -export LIB_MODEL = CCS +#export LIB_MODEL = CCS +export LIB_MODEL = NLDM export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v \ @@ -52,7 +53,7 @@ export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/constraint.sdc export ADDITIONAL_LEFS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lef/*.lef)) export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/lib/*.lib)) -export CORE_UTILIZATION = 30 +export CORE_UTILIZATION = 55 export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/io.tcl export PLACE_DENSITY_LB_ADDON = 0.20 diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index a3eb1dd11a..b900446bfb 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -2,13 +2,13 @@ current_design swerv_wrapper set clk_name core_clock set clk_port_name clk -set clk_period 1600 +set clk_period 1300 # Match the old set_input/output_delay = 0.2 * clk_period budget, as # optimization targets only (no set_input/output_delay — see rationale in # $PLATFORM_DIR/constraints.sdc). -set in2reg_max [expr { $clk_period * 0.8 }] -set reg2out_max [expr { $clk_period * 0.8 }] +set in2reg_max [expr { $clk_period * 0.6 }] +set reg2out_max [expr { $clk_period * 0.6 }] set in2out_max [expr { $clk_period * 0.6 }] source $::env(PLATFORM_DIR)/constraints.sdc diff --git a/flow/designs/gf12/coyote/constraint.sdc b/flow/designs/gf12/coyote/constraint.sdc index 55b59bb9b2..89b6ff4ad7 100644 --- a/flow/designs/gf12/coyote/constraint.sdc +++ b/flow/designs/gf12/coyote/constraint.sdc @@ -6,1578 +6,1578 @@ current_design bsg_rocket_node_client_rocc ############################################################################### # Timing Constraints ############################################################################### -create_clock -name core_clk -period 4000 -waveform {0.0000 2000} [get_ports {clk_i}] -create_clock -name vclk -period 4000 +create_clock -name core_clk -period 2000 -waveform {0.0000 1000} [get_ports {clk_i}] +create_clock -name vclk -period 2000 set_clock_transition 59.0000 [get_clocks {core_clk}] set_clock_uncertainty -setup 200.0000 core_clk set_clock_uncertainty -hold 20.0000 core_clk set_clock_latency 335.750 [get_clocks {core_clk}] set_clock_latency 335.750 [get_clocks {vclk}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {en_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[0]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[10]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[11]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[12]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[13]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[14]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[15]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[16]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[17]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[18]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[19]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[1]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[20]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[21]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[22]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[23]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[24]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[25]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[26]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[27]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[28]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[29]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[2]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[30]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[31]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[32]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[33]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[34]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[35]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[36]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[37]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[38]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[39]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[3]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[40]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[41]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[42]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[43]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[44]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[45]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[46]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[47]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[48]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[49]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[4]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[50]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[51]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[52]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[53]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[54]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[55]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[56]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[57]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[58]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[59]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[5]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[60]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[61]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[62]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[63]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[64]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[65]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[66]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[67]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[68]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[69]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[6]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[70]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[71]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[72]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[73]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[74]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[75]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[76]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[77]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[78]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[79]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[7]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[8]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_i[9]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_v_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_yumi_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {reset_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_ready_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_ctrl_i_busy_}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_ctrl_i_interrupt_}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[0]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[100]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[101]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[102]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[103]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[104]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[105]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[106]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[107]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[108]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[109]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[10]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[110]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[111]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[112]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[113]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[114]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[115]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[116]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[117]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[118]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[119]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[11]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[120]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[121]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[122]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[12]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[13]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[14]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[15]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[16]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[17]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[18]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[19]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[1]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[20]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[21]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[22]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[23]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[24]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[25]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[26]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[27]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[28]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[29]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[2]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[30]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[31]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[32]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[33]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[34]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[35]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[36]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[37]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[38]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[39]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[3]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[40]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[41]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[42]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[43]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[44]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[45]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[46]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[47]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[48]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[49]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[4]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[50]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[51]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[52]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[53]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[54]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[55]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[56]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[57]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[58]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[59]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[5]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[60]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[61]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[62]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[63]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[64]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[65]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[66]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[67]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[68]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[69]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[6]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[70]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[71]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[72]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[73]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[74]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[75]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[76]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[77]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[78]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[79]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[7]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[80]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[81]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[82]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[83]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[84]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[85]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[86]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[87]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[88]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[89]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[8]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[90]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[91]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[92]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[93]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[94]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[95]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[96]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[97]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[98]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[99]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_data_i[9]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_v_i}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[0]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[10]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[11]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[12]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[13]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[14]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[15]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[16]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[17]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[18]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[19]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[1]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[20]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[21]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[22]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[23]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[24]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[25]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[26]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[27]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[28]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[29]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[2]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[30]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[31]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[32]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[33]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[34]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[35]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[36]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[37]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[38]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[39]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[3]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[40]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[41]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[42]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[43]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[44]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[45]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[46]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[47]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[48]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[49]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[4]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[50]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[51]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[52]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[53]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[54]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[55]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[56]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[57]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[58]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[59]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[5]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[60]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[61]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[62]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[63]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[64]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[65]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[66]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[67]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[68]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[6]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[7]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[8]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_data_i[9]}] -set_input_delay 2000 \ +set_input_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_v_i}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[0]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[10]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[11]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[12]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[13]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[14]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[15]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[16]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[17]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[18]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[19]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[1]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[20]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[21]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[22]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[23]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[24]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[25]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[26]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[27]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[28]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[29]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[2]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[30]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[31]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[32]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[33]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[34]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[35]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[36]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[37]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[38]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[39]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[3]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[40]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[41]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[42]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[43]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[44]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[45]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[46]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[47]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[48]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[49]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[4]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[50]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[51]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[52]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[53]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[54]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[55]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[56]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[57]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[58]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[59]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[5]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[60]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[61]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[62]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[63]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[64]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[65]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[66]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[67]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[68]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[69]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[6]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[70]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[71]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[72]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[73]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[74]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[75]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[76]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[77]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[78]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[79]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[7]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[8]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_data_o[9]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_ready_o}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {fsb_node_v_o}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[0]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[100]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[101]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[102]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[103]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[104]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[105]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[106]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[107]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[108]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[109]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[10]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[110]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[111]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[112]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[113]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[114]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[115]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[116]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[117]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[118]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[119]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[11]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[120]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[121]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[122]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[123]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[124]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[125]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[126]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[127]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[128]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[129]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[12]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[130]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[131]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[132]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[133]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[134]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[135]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[136]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[137]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[138]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[139]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[13]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[140]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[141]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[142]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[143]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[144]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[145]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[146]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[147]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[148]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[149]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[14]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[150]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[151]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[152]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[153]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[154]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[155]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[156]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[157]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[158]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[159]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[15]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[16]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[17]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[18]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[19]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[1]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[20]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[21]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[22]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[23]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[24]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[25]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[26]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[27]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[28]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[29]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[2]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[30]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[31]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[32]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[33]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[34]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[35]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[36]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[37]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[38]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[39]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[3]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[40]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[41]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[42]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[43]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[44]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[45]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[46]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[47]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[48]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[49]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[4]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[50]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[51]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[52]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[53]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[54]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[55]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[56]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[57]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[58]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[59]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[5]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[60]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[61]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[62]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[63]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[64]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[65]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[66]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[67]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[68]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[69]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[6]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[70]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[71]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[72]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[73]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[74]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[75]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[76]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[77]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[78]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[79]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[7]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[80]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[81]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[82]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[83]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[84]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[85]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[86]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[87]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[88]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[89]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[8]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[90]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[91]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[92]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[93]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[94]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[95]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[96]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[97]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[98]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[99]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_data_o[9]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_cmd_v_o}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_ctrl_o_exception_}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_ctrl_o_host_id_}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_ctrl_o_s_}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_req_ready_o}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[0]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[100]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[101]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[102]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[103]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[104]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[105]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[106]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[107]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[108]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[109]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[10]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[110]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[111]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[112]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[113]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[114]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[115]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[116]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[117]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[118]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[119]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[11]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[120]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[121]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[122]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[123]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[124]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[125]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[126]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[127]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[128]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[129]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[12]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[130]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[131]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[132]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[133]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[134]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[135]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[136]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[137]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[138]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[139]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[13]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[140]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[141]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[142]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[143]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[144]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[145]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[146]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[147]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[148]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[149]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[14]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[150]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[151]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[152]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[153]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[154]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[155]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[156]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[157]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[158]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[159]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[15]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[160]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[161]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[162]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[163]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[164]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[165]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[166]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[167]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[168]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[169]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[16]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[170]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[171]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[172]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[173]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[174]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[175]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[176]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[177]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[178]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[179]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[17]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[180]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[181]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[182]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[183]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[184]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[185]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[186]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[187]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[188]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[189]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[18]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[190]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[191]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[192]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[193]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[194]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[195]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[196]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[197]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[198]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[199]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[19]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[1]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[200]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[201]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[202]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[203]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[204]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[205]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[206]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[207]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[208]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[209]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[20]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[210]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[211]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[212]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[213]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[214]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[215]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[216]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[217]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[218]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[219]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[21]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[220]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[221]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[222]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[223]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[224]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[225]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[226]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[227]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[228]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[229]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[22]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[230]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[231]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[232]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[233]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[234]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[235]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[236]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[237]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[238]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[239]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[23]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[240]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[241]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[242]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[243]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[244]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[245]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[246]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[247]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[248]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[249]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[24]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[250]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[251]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[252]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[25]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[26]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[27]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[28]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[29]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[2]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[30]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[31]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[32]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[33]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[34]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[35]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[36]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[37]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[38]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[39]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[3]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[40]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[41]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[42]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[43]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[44]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[45]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[46]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[47]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[48]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[49]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[4]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[50]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[51]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[52]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[53]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[54]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[55]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[56]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[57]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[58]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[59]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[5]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[60]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[61]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[62]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[63]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[64]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[65]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[66]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[67]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[68]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[69]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[6]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[70]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[71]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[72]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[73]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[74]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[75]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[76]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[77]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[78]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[79]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[7]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[80]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[81]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[82]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[83]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[84]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[85]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[86]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[87]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[88]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[89]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[8]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[90]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[91]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[92]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[93]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[94]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[95]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[96]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[97]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[98]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[99]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_data_o[9]}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_mem_resp_v_o}] -set_output_delay 2000 \ +set_output_delay 1000 \ -clock [get_clocks {vclk}] -add_delay [get_ports {rocc_resp_ready_o}] set_disable_timing -from {CLKA} -to {CLKB} \ [get_cells {r2f.rocket.RocketTile.dcache.data.T112.mem.macro_mem0.macro_mem0}] diff --git a/flow/designs/sky130hs/jpeg/constraint.sdc b/flow/designs/sky130hs/jpeg/constraint.sdc index 2a20d289a2..757858c59e 100644 --- a/flow/designs/sky130hs/jpeg/constraint.sdc +++ b/flow/designs/sky130hs/jpeg/constraint.sdc @@ -2,7 +2,7 @@ current_design jpeg_encoder set clk_name clk set clk_port_name clk -set clk_period 4.0 +set clk_period 3.5 set clk_io_pct 0.2 set clk_port [get_ports $clk_port_name] From 4b9c9614652854302b2b540231edeafa35ce780c Mon Sep 17 00:00:00 2001 From: Jorge Ferreira Date: Wed, 26 Aug 2026 21:20:00 +0000 Subject: [PATCH 2/4] Update rules-base.json metrics for coyote, jpeg, and swerv_wrapper Signed-off-by: Jorge Ferreira --- .../asap7/swerv_wrapper/rules-base.json | 40 +++++++++---------- flow/designs/gf12/coyote/rules-base.json | 38 +++++++++++------- flow/designs/sky130hs/jpeg/rules-base.json | 34 ++++++++-------- 3 files changed, 61 insertions(+), 51 deletions(-) diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index e56608d56c..938ef3dbd1 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -18,11 +18,11 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 54927, + "value": 54564, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { - "value": 141318, + "value": 131145, "compare": "<=" }, "detailedplace__design__violations": { @@ -30,51 +30,51 @@ "compare": "==" }, "cts__design__instance__count__setup_buffer": { - "value": 12288, + "value": 11404, "compare": "<=" }, "cts__design__instance__count__hold_buffer": { - "value": 12288, + "value": 11404, "compare": "<=" }, "cts__timing__setup__ws": { - "value": -80.0, + "value": -168.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -320.0, + "value": -2010.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -80.0, + "value": -65.0, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -320.0, + "value": -260.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 101, + "value": 100, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -80.0, + "value": -204.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -320.0, + "value": -3000.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -80.0, + "value": -65.0, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -320.0, + "value": -260.0, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 1287970, + "value": 1067592, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -86,27 +86,27 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 101, + "value": 100, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -80.0, + "value": -170.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -320.0, + "value": -2470.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -80.0, + "value": -65.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -320.0, + "value": -260.0, "compare": ">=" }, "finish__design__instance__area": { - "value": 55372, + "value": 55103, "compare": "<=" } } \ No newline at end of file diff --git a/flow/designs/gf12/coyote/rules-base.json b/flow/designs/gf12/coyote/rules-base.json index 97e26689b1..51bd3de5f9 100644 --- a/flow/designs/gf12/coyote/rules-base.json +++ b/flow/designs/gf12/coyote/rules-base.json @@ -1,6 +1,16 @@ { + "synth__canonical_netlist__hash": { + "value": "6b12e68cd707b54afa63173dc9b68809349394e3", + "compare": "==", + "level": "warning" + }, + "synth__netlist__hash": { + "value": "76d24f74e29d36d114cd57742d6e911876d04219", + "compare": "==", + "level": "warning" + }, "synth__design__instance__area__stdcell": { - "value": 168000.0, + "value": 90300.0, "compare": "<=" }, "constraints__clocks__count": { @@ -8,7 +18,7 @@ "compare": "==" }, "placeopt__design__instance__area": { - "value": 196510, + "value": 194602, "compare": "<=" }, "placeopt__design__instance__count__stdcell": { @@ -28,19 +38,19 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -200.0, + "value": -693.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -800.0, + "value": -119000.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -200.0, + "value": -100.0, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -800.0, + "value": -400.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { @@ -48,19 +58,19 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -200.0, + "value": -553.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -800.0, + "value": -78000.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -200.0, + "value": -100.0, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -800.0, + "value": -400.0, "compare": ">=" }, "detailedroute__route__wirelength": { @@ -80,19 +90,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -200.0, + "value": -444.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -800.0, + "value": -41300.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -200.0, + "value": -114.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -800.0, + "value": -540.0, "compare": ">=" }, "finish__design__instance__area": { diff --git a/flow/designs/sky130hs/jpeg/rules-base.json b/flow/designs/sky130hs/jpeg/rules-base.json index 66204ffb93..69f331dae1 100644 --- a/flow/designs/sky130hs/jpeg/rules-base.json +++ b/flow/designs/sky130hs/jpeg/rules-base.json @@ -1,11 +1,11 @@ { "synth__canonical_netlist__hash": { - "value": "17ce8750964fb8436a41017b022516bccfdd8f7a", + "value": "6660baf16fd6c667ca8bf42aa567887cf3dafef2", "compare": "==", "level": "warning" }, "synth__netlist__hash": { - "value": "b371b17cfe3008ecb19b852bfd2edeee7558a563", + "value": "49743a41e69cd9a8456f7f4c00f81ac94c36ab21", "compare": "==", "level": "warning" }, @@ -38,43 +38,43 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -0.2, + "value": -0.528, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -0.8, + "value": -71.6, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -0.2, + "value": -0.175, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -0.8, + "value": -0.7, "compare": ">=" }, "globalroute__antenna_diodes_count": { - "value": 100, + "value": 311, "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -0.267, + "value": -0.761, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -3.0, + "value": -211.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -0.2, + "value": -0.175, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -0.8, + "value": -0.7, "compare": ">=" }, "detailedroute__route__wirelength": { - "value": 1554923, + "value": 1949870, "compare": "<=" }, "detailedroute__route__drc_errors": { @@ -86,23 +86,23 @@ "compare": "<=" }, "detailedroute__antenna_diodes_count": { - "value": 100, + "value": 119, "compare": "<=" }, "finish__timing__setup__ws": { - "value": -0.2, + "value": -0.694, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -0.8, + "value": -108.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -0.2, + "value": -0.175, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -0.8, + "value": -0.7, "compare": ">=" }, "finish__design__instance__area": { From eac8378c16f02c3bf415ac55cb0332a3d88f5932 Mon Sep 17 00:00:00 2001 From: Jorge Ferreira Date: Wed, 26 Aug 2026 21:32:25 +0000 Subject: [PATCH 3/4] Trigger CI Signed-off-by: Jorge Ferreira From 4344d6f503a4262f6ad21540f2cb0ef8947f4d46 Mon Sep 17 00:00:00 2001 From: Jorge Ferreira Date: Fri, 28 Aug 2026 20:47:49 +0000 Subject: [PATCH 4/4] Update asap7 swerv_wrapper config, constraint, and rules-base Signed-off-by: Jorge Ferreira --- flow/designs/asap7/swerv_wrapper/config.mk | 5 ++-- .../asap7/swerv_wrapper/constraint.sdc | 2 +- .../asap7/swerv_wrapper/rules-base.json | 24 +++++++++---------- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/flow/designs/asap7/swerv_wrapper/config.mk b/flow/designs/asap7/swerv_wrapper/config.mk index 77bdc1800d..055969887d 100644 --- a/flow/designs/asap7/swerv_wrapper/config.mk +++ b/flow/designs/asap7/swerv_wrapper/config.mk @@ -42,8 +42,7 @@ export SYNTH_KEEP_MODULES ?= \ ram_256x34 -#export LIB_MODEL = CCS -export LIB_MODEL = NLDM +export LIB_MODEL = CCS export VERILOG_FILES = $(DESIGN_HOME)/src/swerv/swerv_wrapper.sv2v.v \ $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/macros.v \ @@ -56,7 +55,7 @@ export ADDITIONAL_LIBS = $(sort $(wildcard $(DESIGN_HOME)/$(PLATFORM)/swerv_wrap export CORE_UTILIZATION = 55 export IO_CONSTRAINTS = $(DESIGN_HOME)/$(PLATFORM)/swerv_wrapper/io.tcl -export PLACE_DENSITY_LB_ADDON = 0.20 +export PLACE_DENSITY_LB_ADDON = 0.30 export ROUTING_LAYER_ADJUSTMENT = 0.2 diff --git a/flow/designs/asap7/swerv_wrapper/constraint.sdc b/flow/designs/asap7/swerv_wrapper/constraint.sdc index b900446bfb..0a7782de70 100644 --- a/flow/designs/asap7/swerv_wrapper/constraint.sdc +++ b/flow/designs/asap7/swerv_wrapper/constraint.sdc @@ -2,7 +2,7 @@ current_design swerv_wrapper set clk_name core_clock set clk_port_name clk -set clk_period 1300 +set clk_period 1100 # Match the old set_input/output_delay = 0.2 * clk_period budget, as # optimization targets only (no set_input/output_delay — see rationale in diff --git a/flow/designs/asap7/swerv_wrapper/rules-base.json b/flow/designs/asap7/swerv_wrapper/rules-base.json index 938ef3dbd1..c50f6983f1 100644 --- a/flow/designs/asap7/swerv_wrapper/rules-base.json +++ b/flow/designs/asap7/swerv_wrapper/rules-base.json @@ -38,19 +38,19 @@ "compare": "<=" }, "cts__timing__setup__ws": { - "value": -168.0, + "value": -401.0, "compare": ">=" }, "cts__timing__setup__tns": { - "value": -2010.0, + "value": -61200.0, "compare": ">=" }, "cts__timing__hold__ws": { - "value": -65.0, + "value": -55.0, "compare": ">=" }, "cts__timing__hold__tns": { - "value": -260.0, + "value": -220.0, "compare": ">=" }, "globalroute__antenna_diodes_count": { @@ -58,19 +58,19 @@ "compare": "<=" }, "globalroute__timing__setup__ws": { - "value": -204.0, + "value": -395.0, "compare": ">=" }, "globalroute__timing__setup__tns": { - "value": -3000.0, + "value": -51200.0, "compare": ">=" }, "globalroute__timing__hold__ws": { - "value": -65.0, + "value": -55.0, "compare": ">=" }, "globalroute__timing__hold__tns": { - "value": -260.0, + "value": -220.0, "compare": ">=" }, "detailedroute__route__wirelength": { @@ -90,19 +90,19 @@ "compare": "<=" }, "finish__timing__setup__ws": { - "value": -170.0, + "value": -375.0, "compare": ">=" }, "finish__timing__setup__tns": { - "value": -2470.0, + "value": -49100.0, "compare": ">=" }, "finish__timing__hold__ws": { - "value": -65.0, + "value": -55.0, "compare": ">=" }, "finish__timing__hold__tns": { - "value": -260.0, + "value": -220.0, "compare": ">=" }, "finish__design__instance__area": {