diff --git a/flow/designs/asap7/coralnpu/config.mk b/flow/designs/asap7/coralnpu/config.mk new file mode 100644 index 0000000000..b7fd9d9a6f --- /dev/null +++ b/flow/designs/asap7/coralnpu/config.mk @@ -0,0 +1,28 @@ +export PLATFORM = asap7 + +export DESIGN_NICKNAME = coralnpu +export DESIGN_NAME = CoreMiniAxi + +export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sv \ + $(PLATFORM_DIR)/verilog/fakeram_512x128.sv \ + $(PLATFORM_DIR)/verilog/fakeram_2048x128.sv + +export VERILOG_DEFINES += -D USE_ASAP7 + +export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram_512x128.lef \ + $(PLATFORM_DIR)/lef/fakeram_2048x128.lef + +export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/NLDM/fakeram_512x128.lib \ + $(PLATFORM_DIR)/lib/NLDM/fakeram_2048x128.lib + +export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc + +export SYNTH_HDL_FRONTEND ?= slang + +export CORE_UTILIZATION = 65 + +export SYNTH_HIERARCHICAL = 1 +export SYNTH_MINIMUM_KEEP_SIZE = 40000 + +export MACRO_PLACE_HALO = 2 2 + diff --git a/flow/designs/asap7/coralnpu/constraint.sdc b/flow/designs/asap7/coralnpu/constraint.sdc new file mode 100644 index 0000000000..efcf203d0e --- /dev/null +++ b/flow/designs/asap7/coralnpu/constraint.sdc @@ -0,0 +1,9 @@ +current_design CoreMiniAxi + +set clk_name io_aclk +set clk_port_name io_aclk +set clk_period 10.00 + +set clk_port [get_ports $clk_port_name] + +create_clock -period $clk_period -name $clk_name $clk_port diff --git a/flow/designs/asap7/coralnpu/rules-base.json b/flow/designs/asap7/coralnpu/rules-base.json new file mode 100644 index 0000000000..f3b66ed60e --- /dev/null +++ b/flow/designs/asap7/coralnpu/rules-base.json @@ -0,0 +1,112 @@ +{ + "synth__canonical_netlist__hash": { + "value": "5b7726241a901a54348af6b0ce1c968587bb8a7e", + "compare": "==", + "level": "warning" + }, + "synth__netlist__hash": { + "value": "6df65a45ac029ad537f0d8e4702bad13af94c54e", + "compare": "==", + "level": "warning" + }, + "synth__design__instance__area__stdcell": { + "value": 17800.0, + "compare": "<=" + }, + "constraints__clocks__count": { + "value": 1, + "compare": "==" + }, + "placeopt__design__instance__area": { + "value": 37543, + "compare": "<=" + }, + "placeopt__design__instance__count__stdcell": { + "value": 198708, + "compare": "<=" + }, + "detailedplace__design__violations": { + "value": 0, + "compare": "==" + }, + "cts__design__instance__count__setup_buffer": { + "value": 17279, + "compare": "<=" + }, + "cts__design__instance__count__hold_buffer": { + "value": 17279, + "compare": "<=" + }, + "cts__timing__setup__ws": { + "value": -1980.0, + "compare": ">=" + }, + "cts__timing__setup__tns": { + "value": -10200000.0, + "compare": ">=" + }, + "cts__timing__hold__ws": { + "value": -0.5, + "compare": ">=" + }, + "cts__timing__hold__tns": { + "value": -2.0, + "compare": ">=" + }, + "globalroute__antenna_diodes_count": { + "value": 174, + "compare": "<=" + }, + "globalroute__timing__setup__ws": { + "value": -2030.0, + "compare": ">=" + }, + "globalroute__timing__setup__tns": { + "value": -10500000.0, + "compare": ">=" + }, + "globalroute__timing__hold__ws": { + "value": -0.5, + "compare": ">=" + }, + "globalroute__timing__hold__tns": { + "value": -2.0, + "compare": ">=" + }, + "detailedroute__route__wirelength": { + "value": 1540518, + "compare": "<=" + }, + "detailedroute__route__drc_errors": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna__violating__nets": { + "value": 0, + "compare": "<=" + }, + "detailedroute__antenna_diodes_count": { + "value": 174, + "compare": "<=" + }, + "finish__timing__setup__ws": { + "value": -2070.0, + "compare": ">=" + }, + "finish__timing__setup__tns": { + "value": -10800000.0, + "compare": ">=" + }, + "finish__timing__hold__ws": { + "value": -0.5, + "compare": ">=" + }, + "finish__timing__hold__tns": { + "value": -2.0, + "compare": ">=" + }, + "finish__design__instance__area": { + "value": 37931, + "compare": "<=" + } +} \ No newline at end of file diff --git a/flow/designs/src/coralnpu/CoreMiniAxi.sv b/flow/designs/src/coralnpu/CoreMiniAxi.sv new file mode 100644 index 0000000000..cbe4d16144 --- /dev/null +++ b/flow/designs/src/coralnpu/CoreMiniAxi.sv @@ -0,0 +1,30628 @@ +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Include register initializers in init blocks unless synthesis is set +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Standard header to adapt well known macros for register randomization. + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ +module CoreCSR( + input clock, + reset, + input [31:0] io_fabric_readDataAddr_bits, + output io_fabric_readData_valid, + output [127:0] io_fabric_readData_bits, + input io_fabric_writeDataAddr_valid, + input [31:0] io_fabric_writeDataAddr_bits, + input [127:0] io_fabric_writeDataBits, + output io_fabric_writeResp, + io_reset, + io_cg, + output [31:0] io_pcStart, + input io_halted, + io_fault, + input [31:0] io_coralnpu_csr_value_0, + io_coralnpu_csr_value_1, + io_coralnpu_csr_value_2, + io_coralnpu_csr_value_3, + io_coralnpu_csr_value_4, + io_coralnpu_csr_value_5, + io_coralnpu_csr_value_6, + io_coralnpu_csr_value_7 +); + + reg [31:0] resetReg; + reg [31:0] pcStartReg; + reg [31:0] statusReg; + wire readDataValid = + io_fabric_readDataAddr_bits == 32'h108 | io_fabric_readDataAddr_bits == 32'h118 + | io_fabric_readDataAddr_bits == 32'h104 | io_fabric_readDataAddr_bits == 32'h10C + | io_fabric_readDataAddr_bits == 32'h0 | io_fabric_readDataAddr_bits == 32'h110 + | io_fabric_readDataAddr_bits == 32'h114 | io_fabric_readDataAddr_bits == 32'h100 + | io_fabric_readDataAddr_bits == 32'h4 | io_fabric_readDataAddr_bits == 32'h11C + | io_fabric_readDataAddr_bits == 32'h8; + reg readDataNext_pipe_v; + reg [127:0] readDataNext_pipe_b; + wire _io_fabric_writeResp_T_1 = io_fabric_writeDataAddr_bits == 32'h0; + wire _io_fabric_writeResp_T_2 = io_fabric_writeDataAddr_bits == 32'h4; + always @(posedge clock or posedge reset) begin + if (reset) begin + resetReg <= 32'h3; + pcStartReg <= 32'h0; + statusReg <= 32'h0; + readDataNext_pipe_v <= 1'h0; + end + else begin + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_1) + resetReg <= io_fabric_writeDataBits[31:0]; + if (io_fabric_writeDataAddr_valid & _io_fabric_writeResp_T_2) + pcStartReg <= io_fabric_writeDataBits[63:32]; + statusReg <= {30'h0, io_fault, io_halted}; + readDataNext_pipe_v <= readDataValid; + end + end // always @(posedge, posedge) + wire _GEN = io_fabric_readDataAddr_bits[31:4] == 28'h0; + wire _GEN_0 = io_fabric_readDataAddr_bits[31:4] == 28'h10; + wire _GEN_1 = io_fabric_readDataAddr_bits[31:4] == 28'h11; + always @(posedge clock) begin + if (readDataValid) + readDataNext_pipe_b <= + {_GEN_1 ? io_coralnpu_csr_value_7 : _GEN_0 ? io_coralnpu_csr_value_3 : 32'h0, + _GEN_1 + ? io_coralnpu_csr_value_6 + : _GEN_0 ? io_coralnpu_csr_value_2 : _GEN ? statusReg : 32'h0, + _GEN_1 + ? io_coralnpu_csr_value_5 + : _GEN_0 ? io_coralnpu_csr_value_1 : _GEN ? pcStartReg : 32'h0, + _GEN_1 + ? io_coralnpu_csr_value_4 + : _GEN_0 ? io_coralnpu_csr_value_0 : _GEN ? resetReg : 32'h0}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:7]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin + _RANDOM[i[2:0]] = `RANDOM; + end + resetReg = _RANDOM[3'h0]; + pcStartReg = _RANDOM[3'h1]; + statusReg = _RANDOM[3'h2]; + readDataNext_pipe_v = _RANDOM[3'h3][0]; + readDataNext_pipe_b = + {_RANDOM[3'h3][31:1], + _RANDOM[3'h4], + _RANDOM[3'h5], + _RANDOM[3'h6], + _RANDOM[3'h7][0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + resetReg = 32'h3; + pcStartReg = 32'h0; + statusReg = 32'h0; + readDataNext_pipe_v = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_fabric_readData_valid = readDataNext_pipe_v; + assign io_fabric_readData_bits = readDataNext_pipe_b; + assign io_fabric_writeResp = + io_fabric_writeDataAddr_valid & (_io_fabric_writeResp_T_2 | _io_fabric_writeResp_T_1); + assign io_reset = resetReg[0]; + assign io_cg = resetReg[1]; + assign io_pcStart = pcStartReg; +endmodule + +module Regfile( + input clock, + reset, + io_readAddr_0_valid, + input [4:0] io_readAddr_0_addr, + input io_readAddr_1_valid, + input [4:0] io_readAddr_1_addr, + input io_readAddr_2_valid, + input [4:0] io_readAddr_2_addr, + input io_readAddr_3_valid, + input [4:0] io_readAddr_3_addr, + input io_readAddr_4_valid, + input [4:0] io_readAddr_4_addr, + input io_readAddr_5_valid, + input [4:0] io_readAddr_5_addr, + input io_readAddr_6_valid, + input [4:0] io_readAddr_6_addr, + input io_readAddr_7_valid, + input [4:0] io_readAddr_7_addr, + input io_readSet_0_valid, + input [31:0] io_readSet_0_value, + input io_readSet_1_valid, + input [31:0] io_readSet_1_value, + input io_readSet_2_valid, + input [31:0] io_readSet_2_value, + input io_readSet_3_valid, + input [31:0] io_readSet_3_value, + input io_readSet_4_valid, + input [31:0] io_readSet_4_value, + input io_readSet_5_valid, + input [31:0] io_readSet_5_value, + input io_readSet_6_valid, + input [31:0] io_readSet_6_value, + input io_readSet_7_valid, + input [31:0] io_readSet_7_value, + input io_writeAddr_0_valid, + input [4:0] io_writeAddr_0_addr, + input io_writeAddr_1_valid, + input [4:0] io_writeAddr_1_addr, + input io_writeAddr_2_valid, + input [4:0] io_writeAddr_2_addr, + input io_writeAddr_3_valid, + input [4:0] io_writeAddr_3_addr, + input io_busAddr_0_bypass, + io_busAddr_0_immen, + input [31:0] io_busAddr_0_immed, + input io_busAddr_1_bypass, + input [31:0] io_busAddr_1_immed, + input io_busAddr_2_bypass, + input [31:0] io_busAddr_2_immed, + input io_busAddr_3_bypass, + input [31:0] io_busAddr_3_immed, + output [31:0] io_target_0_data, + io_target_1_data, + io_target_2_data, + io_target_3_data, + io_busPort_addr_0, + io_busPort_addr_1, + io_busPort_addr_2, + io_busPort_addr_3, + io_busPort_data_0, + io_busPort_data_1, + io_busPort_data_2, + io_busPort_data_3, + output io_readData_0_valid, + output [31:0] io_readData_0_data, + output io_readData_1_valid, + output [31:0] io_readData_1_data, + output io_readData_2_valid, + output [31:0] io_readData_2_data, + output io_readData_3_valid, + output [31:0] io_readData_3_data, + output io_readData_4_valid, + output [31:0] io_readData_4_data, + output io_readData_5_valid, + output [31:0] io_readData_5_data, + output io_readData_6_valid, + output [31:0] io_readData_6_data, + output io_readData_7_valid, + output [31:0] io_readData_7_data, + input io_writeData_0_valid, + input [4:0] io_writeData_0_bits_addr, + input [31:0] io_writeData_0_bits_data, + input io_writeData_1_valid, + input [4:0] io_writeData_1_bits_addr, + input [31:0] io_writeData_1_bits_data, + input io_writeData_2_valid, + input [4:0] io_writeData_2_bits_addr, + input [31:0] io_writeData_2_bits_data, + input io_writeData_3_valid, + input [4:0] io_writeData_3_bits_addr, + input [31:0] io_writeData_3_bits_data, + input io_writeData_4_valid, + input [4:0] io_writeData_4_bits_addr, + input [31:0] io_writeData_4_bits_data, + input io_writeData_5_valid, + input [4:0] io_writeData_5_bits_addr, + input [31:0] io_writeData_5_bits_data, + input io_writeMask_1_valid, + io_writeMask_2_valid, + io_writeMask_3_valid, + output [31:0] io_scoreboard_regd, + io_scoreboard_comb, + output [5:0] io_rfwriteCount +); + + reg [31:0] regfile_1; + reg [31:0] regfile_2; + reg [31:0] regfile_3; + reg [31:0] regfile_4; + reg [31:0] regfile_5; + reg [31:0] regfile_6; + reg [31:0] regfile_7; + reg [31:0] regfile_8; + reg [31:0] regfile_9; + reg [31:0] regfile_10; + reg [31:0] regfile_11; + reg [31:0] regfile_12; + reg [31:0] regfile_13; + reg [31:0] regfile_14; + reg [31:0] regfile_15; + reg [31:0] regfile_16; + reg [31:0] regfile_17; + reg [31:0] regfile_18; + reg [31:0] regfile_19; + reg [31:0] regfile_20; + reg [31:0] regfile_21; + reg [31:0] regfile_22; + reg [31:0] regfile_23; + reg [31:0] regfile_24; + reg [31:0] regfile_25; + reg [31:0] regfile_26; + reg [31:0] regfile_27; + reg [31:0] regfile_28; + reg [31:0] regfile_29; + reg [31:0] regfile_30; + reg [31:0] regfile_31; + reg [31:0] scoreboard; + wire [31:0] _scoreboard_clr0_T_1 = 32'h1 << io_writeData_0_bits_addr; + wire [31:0] _scoreboard_clr0_T_4 = 32'h1 << io_writeData_1_bits_addr; + wire [31:0] _scoreboard_clr0_T_7 = 32'h1 << io_writeData_2_bits_addr; + wire [31:0] _scoreboard_clr0_T_10 = 32'h1 << io_writeData_3_bits_addr; + wire [31:0] _scoreboard_clr0_T_13 = 32'h1 << io_writeData_4_bits_addr; + wire [31:0] _scoreboard_clr0_T_16 = 32'h1 << io_writeData_5_bits_addr; + wire [30:0] scoreboard_clr0 = + (io_writeData_0_valid ? _scoreboard_clr0_T_1[31:1] : 31'h0) + | (io_writeData_1_valid ? _scoreboard_clr0_T_4[31:1] : 31'h0) + | (io_writeData_2_valid ? _scoreboard_clr0_T_7[31:1] : 31'h0) + | (io_writeData_3_valid ? _scoreboard_clr0_T_10[31:1] : 31'h0) + | (io_writeData_4_valid ? _scoreboard_clr0_T_13[31:1] : 31'h0) + | (io_writeData_5_valid ? _scoreboard_clr0_T_16[31:1] : 31'h0); + reg readDataReady_0; + reg readDataReady_1; + reg readDataReady_2; + reg readDataReady_3; + reg readDataReady_4; + reg readDataReady_5; + reg readDataReady_6; + reg readDataReady_7; + reg [31:0] readDataBits_0; + reg [31:0] readDataBits_1; + reg [31:0] readDataBits_2; + reg [31:0] readDataBits_3; + reg [31:0] readDataBits_4; + reg [31:0] readDataBits_5; + reg [31:0] readDataBits_6; + reg [31:0] readDataBits_7; + wire _valid_T = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1; + wire valid_1 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1 & ~io_writeMask_1_valid; + wire valid_2 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1 & ~io_writeMask_2_valid; + wire valid_3 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1 & ~io_writeMask_3_valid; + wire _valid_T_8 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1; + wire _valid_T_10 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1; + wire [31:0] data = + (_valid_T ? io_writeData_0_bits_data : 32'h0) + | (valid_1 ? io_writeData_1_bits_data : 32'h0) + | (valid_2 ? io_writeData_2_bits_data : 32'h0) + | (valid_3 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_8 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_10 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_1_T = + {_valid_T, valid_1, valid_2, valid_3, _valid_T_8, _valid_T_10}; + wire _valid_T_12 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h2; + wire valid_1_1 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h2 & ~io_writeMask_1_valid; + wire valid_2_1 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h2 & ~io_writeMask_2_valid; + wire valid_3_1 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h2 & ~io_writeMask_3_valid; + wire _valid_T_20 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h2; + wire _valid_T_22 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h2; + wire [31:0] data_1 = + (_valid_T_12 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_1 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_1 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_1 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_20 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_22 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_2_T = + {_valid_T_12, valid_1_1, valid_2_1, valid_3_1, _valid_T_20, _valid_T_22}; + wire _valid_T_24 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h3; + wire valid_1_2 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h3 & ~io_writeMask_1_valid; + wire valid_2_2 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h3 & ~io_writeMask_2_valid; + wire valid_3_2 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h3 & ~io_writeMask_3_valid; + wire _valid_T_32 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h3; + wire _valid_T_34 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h3; + wire [31:0] data_2 = + (_valid_T_24 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_2 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_2 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_2 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_32 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_34 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_3_T = + {_valid_T_24, valid_1_2, valid_2_2, valid_3_2, _valid_T_32, _valid_T_34}; + wire _valid_T_36 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h4; + wire valid_1_3 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h4 & ~io_writeMask_1_valid; + wire valid_2_3 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h4 & ~io_writeMask_2_valid; + wire valid_3_3 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h4 & ~io_writeMask_3_valid; + wire _valid_T_44 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h4; + wire _valid_T_46 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h4; + wire [31:0] data_3 = + (_valid_T_36 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_3 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_3 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_3 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_44 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_46 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_4_T = + {_valid_T_36, valid_1_3, valid_2_3, valid_3_3, _valid_T_44, _valid_T_46}; + wire _valid_T_48 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h5; + wire valid_1_4 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h5 & ~io_writeMask_1_valid; + wire valid_2_4 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h5 & ~io_writeMask_2_valid; + wire valid_3_4 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h5 & ~io_writeMask_3_valid; + wire _valid_T_56 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h5; + wire _valid_T_58 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h5; + wire [31:0] data_4 = + (_valid_T_48 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_4 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_4 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_4 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_56 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_58 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_5_T = + {_valid_T_48, valid_1_4, valid_2_4, valid_3_4, _valid_T_56, _valid_T_58}; + wire _valid_T_60 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h6; + wire valid_1_5 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h6 & ~io_writeMask_1_valid; + wire valid_2_5 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h6 & ~io_writeMask_2_valid; + wire valid_3_5 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h6 & ~io_writeMask_3_valid; + wire _valid_T_68 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h6; + wire _valid_T_70 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h6; + wire [31:0] data_5 = + (_valid_T_60 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_5 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_5 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_5 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_68 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_70 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_6_T = + {_valid_T_60, valid_1_5, valid_2_5, valid_3_5, _valid_T_68, _valid_T_70}; + wire _valid_T_72 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h7; + wire valid_1_6 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h7 & ~io_writeMask_1_valid; + wire valid_2_6 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h7 & ~io_writeMask_2_valid; + wire valid_3_6 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h7 & ~io_writeMask_3_valid; + wire _valid_T_80 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h7; + wire _valid_T_82 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h7; + wire [31:0] data_6 = + (_valid_T_72 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_6 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_6 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_6 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_80 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_82 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_7_T = + {_valid_T_72, valid_1_6, valid_2_6, valid_3_6, _valid_T_80, _valid_T_82}; + wire _valid_T_84 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h8; + wire valid_1_7 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h8 & ~io_writeMask_1_valid; + wire valid_2_7 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h8 & ~io_writeMask_2_valid; + wire valid_3_7 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h8 & ~io_writeMask_3_valid; + wire _valid_T_92 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h8; + wire _valid_T_94 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h8; + wire [31:0] data_7 = + (_valid_T_84 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_7 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_7 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_7 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_92 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_94 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_8_T = + {_valid_T_84, valid_1_7, valid_2_7, valid_3_7, _valid_T_92, _valid_T_94}; + wire _valid_T_96 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h9; + wire valid_1_8 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h9 & ~io_writeMask_1_valid; + wire valid_2_8 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h9 & ~io_writeMask_2_valid; + wire valid_3_8 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h9 & ~io_writeMask_3_valid; + wire _valid_T_104 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h9; + wire _valid_T_106 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h9; + wire [31:0] data_8 = + (_valid_T_96 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_8 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_8 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_8 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_104 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_106 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_9_T = + {_valid_T_96, valid_1_8, valid_2_8, valid_3_8, _valid_T_104, _valid_T_106}; + wire _valid_T_108 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hA; + wire valid_1_9 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hA & ~io_writeMask_1_valid; + wire valid_2_9 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hA & ~io_writeMask_2_valid; + wire valid_3_9 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hA & ~io_writeMask_3_valid; + wire _valid_T_116 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hA; + wire _valid_T_118 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hA; + wire [31:0] data_9 = + (_valid_T_108 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_9 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_9 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_9 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_116 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_118 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_10_T = + {_valid_T_108, valid_1_9, valid_2_9, valid_3_9, _valid_T_116, _valid_T_118}; + wire _valid_T_120 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hB; + wire valid_1_10 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hB & ~io_writeMask_1_valid; + wire valid_2_10 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hB & ~io_writeMask_2_valid; + wire valid_3_10 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hB & ~io_writeMask_3_valid; + wire _valid_T_128 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hB; + wire _valid_T_130 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hB; + wire [31:0] data_10 = + (_valid_T_120 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_10 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_10 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_10 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_128 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_130 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_11_T = + {_valid_T_120, valid_1_10, valid_2_10, valid_3_10, _valid_T_128, _valid_T_130}; + wire _valid_T_132 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hC; + wire valid_1_11 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hC & ~io_writeMask_1_valid; + wire valid_2_11 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hC & ~io_writeMask_2_valid; + wire valid_3_11 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hC & ~io_writeMask_3_valid; + wire _valid_T_140 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hC; + wire _valid_T_142 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hC; + wire [31:0] data_11 = + (_valid_T_132 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_11 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_11 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_11 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_140 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_142 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_12_T = + {_valid_T_132, valid_1_11, valid_2_11, valid_3_11, _valid_T_140, _valid_T_142}; + wire _valid_T_144 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hD; + wire valid_1_12 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hD & ~io_writeMask_1_valid; + wire valid_2_12 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hD & ~io_writeMask_2_valid; + wire valid_3_12 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hD & ~io_writeMask_3_valid; + wire _valid_T_152 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hD; + wire _valid_T_154 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hD; + wire [31:0] data_12 = + (_valid_T_144 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_12 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_12 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_12 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_152 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_154 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_13_T = + {_valid_T_144, valid_1_12, valid_2_12, valid_3_12, _valid_T_152, _valid_T_154}; + wire _valid_T_156 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hE; + wire valid_1_13 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hE & ~io_writeMask_1_valid; + wire valid_2_13 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hE & ~io_writeMask_2_valid; + wire valid_3_13 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hE & ~io_writeMask_3_valid; + wire _valid_T_164 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hE; + wire _valid_T_166 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hE; + wire [31:0] data_13 = + (_valid_T_156 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_13 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_13 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_13 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_164 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_166 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_14_T = + {_valid_T_156, valid_1_13, valid_2_13, valid_3_13, _valid_T_164, _valid_T_166}; + wire _valid_T_168 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'hF; + wire valid_1_14 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'hF & ~io_writeMask_1_valid; + wire valid_2_14 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'hF & ~io_writeMask_2_valid; + wire valid_3_14 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'hF & ~io_writeMask_3_valid; + wire _valid_T_176 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'hF; + wire _valid_T_178 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'hF; + wire [31:0] data_14 = + (_valid_T_168 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_14 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_14 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_14 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_176 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_178 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_15_T = + {_valid_T_168, valid_1_14, valid_2_14, valid_3_14, _valid_T_176, _valid_T_178}; + wire _valid_T_180 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h10; + wire valid_1_15 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h10 & ~io_writeMask_1_valid; + wire valid_2_15 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h10 & ~io_writeMask_2_valid; + wire valid_3_15 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h10 & ~io_writeMask_3_valid; + wire _valid_T_188 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h10; + wire _valid_T_190 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h10; + wire [31:0] data_15 = + (_valid_T_180 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_15 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_15 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_15 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_188 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_190 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_16_T = + {_valid_T_180, valid_1_15, valid_2_15, valid_3_15, _valid_T_188, _valid_T_190}; + wire _valid_T_192 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h11; + wire valid_1_16 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h11 & ~io_writeMask_1_valid; + wire valid_2_16 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h11 & ~io_writeMask_2_valid; + wire valid_3_16 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h11 & ~io_writeMask_3_valid; + wire _valid_T_200 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h11; + wire _valid_T_202 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h11; + wire [31:0] data_16 = + (_valid_T_192 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_16 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_16 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_16 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_200 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_202 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_17_T = + {_valid_T_192, valid_1_16, valid_2_16, valid_3_16, _valid_T_200, _valid_T_202}; + wire _valid_T_204 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h12; + wire valid_1_17 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h12 & ~io_writeMask_1_valid; + wire valid_2_17 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h12 & ~io_writeMask_2_valid; + wire valid_3_17 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h12 & ~io_writeMask_3_valid; + wire _valid_T_212 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h12; + wire _valid_T_214 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h12; + wire [31:0] data_17 = + (_valid_T_204 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_17 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_17 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_17 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_212 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_214 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_18_T = + {_valid_T_204, valid_1_17, valid_2_17, valid_3_17, _valid_T_212, _valid_T_214}; + wire _valid_T_216 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h13; + wire valid_1_18 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h13 & ~io_writeMask_1_valid; + wire valid_2_18 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h13 & ~io_writeMask_2_valid; + wire valid_3_18 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h13 & ~io_writeMask_3_valid; + wire _valid_T_224 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h13; + wire _valid_T_226 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h13; + wire [31:0] data_18 = + (_valid_T_216 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_18 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_18 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_18 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_224 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_226 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_19_T = + {_valid_T_216, valid_1_18, valid_2_18, valid_3_18, _valid_T_224, _valid_T_226}; + wire _valid_T_228 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h14; + wire valid_1_19 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h14 & ~io_writeMask_1_valid; + wire valid_2_19 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h14 & ~io_writeMask_2_valid; + wire valid_3_19 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h14 & ~io_writeMask_3_valid; + wire _valid_T_236 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h14; + wire _valid_T_238 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h14; + wire [31:0] data_19 = + (_valid_T_228 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_19 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_19 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_19 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_236 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_238 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_20_T = + {_valid_T_228, valid_1_19, valid_2_19, valid_3_19, _valid_T_236, _valid_T_238}; + wire _valid_T_240 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h15; + wire valid_1_20 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h15 & ~io_writeMask_1_valid; + wire valid_2_20 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h15 & ~io_writeMask_2_valid; + wire valid_3_20 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h15 & ~io_writeMask_3_valid; + wire _valid_T_248 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h15; + wire _valid_T_250 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h15; + wire [31:0] data_20 = + (_valid_T_240 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_20 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_20 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_20 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_248 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_250 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_21_T = + {_valid_T_240, valid_1_20, valid_2_20, valid_3_20, _valid_T_248, _valid_T_250}; + wire _valid_T_252 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h16; + wire valid_1_21 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h16 & ~io_writeMask_1_valid; + wire valid_2_21 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h16 & ~io_writeMask_2_valid; + wire valid_3_21 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h16 & ~io_writeMask_3_valid; + wire _valid_T_260 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h16; + wire _valid_T_262 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h16; + wire [31:0] data_21 = + (_valid_T_252 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_21 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_21 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_21 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_260 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_262 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_22_T = + {_valid_T_252, valid_1_21, valid_2_21, valid_3_21, _valid_T_260, _valid_T_262}; + wire _valid_T_264 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h17; + wire valid_1_22 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h17 & ~io_writeMask_1_valid; + wire valid_2_22 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h17 & ~io_writeMask_2_valid; + wire valid_3_22 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h17 & ~io_writeMask_3_valid; + wire _valid_T_272 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h17; + wire _valid_T_274 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h17; + wire [31:0] data_22 = + (_valid_T_264 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_22 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_22 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_22 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_272 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_274 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_23_T = + {_valid_T_264, valid_1_22, valid_2_22, valid_3_22, _valid_T_272, _valid_T_274}; + wire _valid_T_276 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h18; + wire valid_1_23 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h18 & ~io_writeMask_1_valid; + wire valid_2_23 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h18 & ~io_writeMask_2_valid; + wire valid_3_23 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h18 & ~io_writeMask_3_valid; + wire _valid_T_284 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h18; + wire _valid_T_286 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h18; + wire [31:0] data_23 = + (_valid_T_276 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_23 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_23 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_23 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_284 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_286 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_24_T = + {_valid_T_276, valid_1_23, valid_2_23, valid_3_23, _valid_T_284, _valid_T_286}; + wire _valid_T_288 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h19; + wire valid_1_24 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h19 & ~io_writeMask_1_valid; + wire valid_2_24 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h19 & ~io_writeMask_2_valid; + wire valid_3_24 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h19 & ~io_writeMask_3_valid; + wire _valid_T_296 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h19; + wire _valid_T_298 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h19; + wire [31:0] data_24 = + (_valid_T_288 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_24 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_24 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_24 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_296 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_298 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_25_T = + {_valid_T_288, valid_1_24, valid_2_24, valid_3_24, _valid_T_296, _valid_T_298}; + wire _valid_T_300 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1A; + wire valid_1_25 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1A & ~io_writeMask_1_valid; + wire valid_2_25 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1A & ~io_writeMask_2_valid; + wire valid_3_25 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1A & ~io_writeMask_3_valid; + wire _valid_T_308 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1A; + wire _valid_T_310 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1A; + wire [31:0] data_25 = + (_valid_T_300 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_25 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_25 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_25 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_308 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_310 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_26_T = + {_valid_T_300, valid_1_25, valid_2_25, valid_3_25, _valid_T_308, _valid_T_310}; + wire _valid_T_312 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1B; + wire valid_1_26 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1B & ~io_writeMask_1_valid; + wire valid_2_26 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1B & ~io_writeMask_2_valid; + wire valid_3_26 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1B & ~io_writeMask_3_valid; + wire _valid_T_320 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1B; + wire _valid_T_322 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1B; + wire [31:0] data_26 = + (_valid_T_312 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_26 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_26 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_26 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_320 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_322 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_27_T = + {_valid_T_312, valid_1_26, valid_2_26, valid_3_26, _valid_T_320, _valid_T_322}; + wire _valid_T_324 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1C; + wire valid_1_27 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1C & ~io_writeMask_1_valid; + wire valid_2_27 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1C & ~io_writeMask_2_valid; + wire valid_3_27 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1C & ~io_writeMask_3_valid; + wire _valid_T_332 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1C; + wire _valid_T_334 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1C; + wire [31:0] data_27 = + (_valid_T_324 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_27 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_27 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_27 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_332 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_334 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_28_T = + {_valid_T_324, valid_1_27, valid_2_27, valid_3_27, _valid_T_332, _valid_T_334}; + wire _valid_T_336 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1D; + wire valid_1_28 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1D & ~io_writeMask_1_valid; + wire valid_2_28 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1D & ~io_writeMask_2_valid; + wire valid_3_28 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1D & ~io_writeMask_3_valid; + wire _valid_T_344 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1D; + wire _valid_T_346 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1D; + wire [31:0] data_28 = + (_valid_T_336 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_28 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_28 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_28 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_344 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_346 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_29_T = + {_valid_T_336, valid_1_28, valid_2_28, valid_3_28, _valid_T_344, _valid_T_346}; + wire _valid_T_348 = io_writeData_0_valid & io_writeData_0_bits_addr == 5'h1E; + wire valid_1_29 = + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h1E & ~io_writeMask_1_valid; + wire valid_2_29 = + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h1E & ~io_writeMask_2_valid; + wire valid_3_29 = + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h1E & ~io_writeMask_3_valid; + wire _valid_T_356 = io_writeData_4_valid & io_writeData_4_bits_addr == 5'h1E; + wire _valid_T_358 = io_writeData_5_valid & io_writeData_5_bits_addr == 5'h1E; + wire [31:0] data_29 = + (_valid_T_348 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_29 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_29 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_29 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_356 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_358 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_30_T = + {_valid_T_348, valid_1_29, valid_2_29, valid_3_29, _valid_T_356, _valid_T_358}; + wire _valid_T_360 = io_writeData_0_valid & (&io_writeData_0_bits_addr); + wire valid_1_30 = + io_writeData_1_valid & (&io_writeData_1_bits_addr) & ~io_writeMask_1_valid; + wire valid_2_30 = + io_writeData_2_valid & (&io_writeData_2_bits_addr) & ~io_writeMask_2_valid; + wire valid_3_30 = + io_writeData_3_valid & (&io_writeData_3_bits_addr) & ~io_writeMask_3_valid; + wire _valid_T_368 = io_writeData_4_valid & (&io_writeData_4_bits_addr); + wire _valid_T_370 = io_writeData_5_valid & (&io_writeData_5_bits_addr); + wire [31:0] data_30 = + (_valid_T_360 ? io_writeData_0_bits_data : 32'h0) + | (valid_1_30 ? io_writeData_1_bits_data : 32'h0) + | (valid_2_30 ? io_writeData_2_bits_data : 32'h0) + | (valid_3_30 ? io_writeData_3_bits_data : 32'h0) + | (_valid_T_368 ? io_writeData_4_bits_data : 32'h0) + | (_valid_T_370 ? io_writeData_5_bits_data : 32'h0); + wire [5:0] _writeValid_31_T = + {_valid_T_360, valid_1_30, valid_2_30, valid_3_30, _valid_T_368, _valid_T_370}; + wire _wdata_0_value_1_T = io_readAddr_0_addr == 5'h1; + wire _wdata_0_value_2_T = io_readAddr_0_addr == 5'h2; + wire _wdata_0_value_3_T = io_readAddr_0_addr == 5'h3; + wire _wdata_0_value_4_T = io_readAddr_0_addr == 5'h4; + wire _wdata_0_value_5_T = io_readAddr_0_addr == 5'h5; + wire _wdata_0_value_6_T = io_readAddr_0_addr == 5'h6; + wire _wdata_0_value_7_T = io_readAddr_0_addr == 5'h7; + wire _wdata_0_value_8_T = io_readAddr_0_addr == 5'h8; + wire _wdata_0_value_9_T = io_readAddr_0_addr == 5'h9; + wire _wdata_0_value_10_T = io_readAddr_0_addr == 5'hA; + wire _wdata_0_value_11_T = io_readAddr_0_addr == 5'hB; + wire _wdata_0_value_12_T = io_readAddr_0_addr == 5'hC; + wire _wdata_0_value_13_T = io_readAddr_0_addr == 5'hD; + wire _wdata_0_value_14_T = io_readAddr_0_addr == 5'hE; + wire _wdata_0_value_15_T = io_readAddr_0_addr == 5'hF; + wire _wdata_0_value_16_T = io_readAddr_0_addr == 5'h10; + wire _wdata_0_value_17_T = io_readAddr_0_addr == 5'h11; + wire _wdata_0_value_18_T = io_readAddr_0_addr == 5'h12; + wire _wdata_0_value_19_T = io_readAddr_0_addr == 5'h13; + wire _wdata_0_value_20_T = io_readAddr_0_addr == 5'h14; + wire _wdata_0_value_21_T = io_readAddr_0_addr == 5'h15; + wire _wdata_0_value_22_T = io_readAddr_0_addr == 5'h16; + wire _wdata_0_value_23_T = io_readAddr_0_addr == 5'h17; + wire _wdata_0_value_24_T = io_readAddr_0_addr == 5'h18; + wire _wdata_0_value_25_T = io_readAddr_0_addr == 5'h19; + wire _wdata_0_value_26_T = io_readAddr_0_addr == 5'h1A; + wire _wdata_0_value_27_T = io_readAddr_0_addr == 5'h1B; + wire _wdata_0_value_28_T = io_readAddr_0_addr == 5'h1C; + wire _wdata_0_value_29_T = io_readAddr_0_addr == 5'h1D; + wire _wdata_0_value_30_T = io_readAddr_0_addr == 5'h1E; + wire [31:0] rdata_0_value_5_0 = + (_wdata_0_value_1_T ? regfile_1 : 32'h0) | (_wdata_0_value_2_T ? regfile_2 : 32'h0) + | (_wdata_0_value_3_T ? regfile_3 : 32'h0) | (_wdata_0_value_4_T ? regfile_4 : 32'h0) + | (_wdata_0_value_5_T ? regfile_5 : 32'h0) | (_wdata_0_value_6_T ? regfile_6 : 32'h0) + | (_wdata_0_value_7_T ? regfile_7 : 32'h0) | (_wdata_0_value_8_T ? regfile_8 : 32'h0) + | (_wdata_0_value_9_T ? regfile_9 : 32'h0) + | (_wdata_0_value_10_T ? regfile_10 : 32'h0) + | (_wdata_0_value_11_T ? regfile_11 : 32'h0) + | (_wdata_0_value_12_T ? regfile_12 : 32'h0) + | (_wdata_0_value_13_T ? regfile_13 : 32'h0) + | (_wdata_0_value_14_T ? regfile_14 : 32'h0) + | (_wdata_0_value_15_T ? regfile_15 : 32'h0) + | (_wdata_0_value_16_T ? regfile_16 : 32'h0) + | (_wdata_0_value_17_T ? regfile_17 : 32'h0) + | (_wdata_0_value_18_T ? regfile_18 : 32'h0) + | (_wdata_0_value_19_T ? regfile_19 : 32'h0) + | (_wdata_0_value_20_T ? regfile_20 : 32'h0) + | (_wdata_0_value_21_T ? regfile_21 : 32'h0) + | (_wdata_0_value_22_T ? regfile_22 : 32'h0) + | (_wdata_0_value_23_T ? regfile_23 : 32'h0) + | (_wdata_0_value_24_T ? regfile_24 : 32'h0) + | (_wdata_0_value_25_T ? regfile_25 : 32'h0) + | (_wdata_0_value_26_T ? regfile_26 : 32'h0) + | (_wdata_0_value_27_T ? regfile_27 : 32'h0) + | (_wdata_0_value_28_T ? regfile_28 : 32'h0) + | (_wdata_0_value_29_T ? regfile_29 : 32'h0) + | (_wdata_0_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_0_addr) ? regfile_31 : 32'h0); + wire [31:0] rwdata_0 = + io_readAddr_0_addr == 5'h0 | _wdata_0_value_1_T & (|_writeValid_1_T) + | _wdata_0_value_2_T & (|_writeValid_2_T) | _wdata_0_value_3_T & (|_writeValid_3_T) + | _wdata_0_value_4_T & (|_writeValid_4_T) | _wdata_0_value_5_T & (|_writeValid_5_T) + | _wdata_0_value_6_T & (|_writeValid_6_T) | _wdata_0_value_7_T & (|_writeValid_7_T) + | _wdata_0_value_8_T & (|_writeValid_8_T) | _wdata_0_value_9_T & (|_writeValid_9_T) + | _wdata_0_value_10_T & (|_writeValid_10_T) | _wdata_0_value_11_T + & (|_writeValid_11_T) | _wdata_0_value_12_T & (|_writeValid_12_T) + | _wdata_0_value_13_T & (|_writeValid_13_T) | _wdata_0_value_14_T + & (|_writeValid_14_T) | _wdata_0_value_15_T & (|_writeValid_15_T) + | _wdata_0_value_16_T & (|_writeValid_16_T) | _wdata_0_value_17_T + & (|_writeValid_17_T) | _wdata_0_value_18_T & (|_writeValid_18_T) + | _wdata_0_value_19_T & (|_writeValid_19_T) | _wdata_0_value_20_T + & (|_writeValid_20_T) | _wdata_0_value_21_T & (|_writeValid_21_T) + | _wdata_0_value_22_T & (|_writeValid_22_T) | _wdata_0_value_23_T + & (|_writeValid_23_T) | _wdata_0_value_24_T & (|_writeValid_24_T) + | _wdata_0_value_25_T & (|_writeValid_25_T) | _wdata_0_value_26_T + & (|_writeValid_26_T) | _wdata_0_value_27_T & (|_writeValid_27_T) + | _wdata_0_value_28_T & (|_writeValid_28_T) | _wdata_0_value_29_T + & (|_writeValid_29_T) | _wdata_0_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_0_addr) & (|_writeValid_31_T) + ? (_wdata_0_value_1_T ? data : 32'h0) | (_wdata_0_value_2_T ? data_1 : 32'h0) + | (_wdata_0_value_3_T ? data_2 : 32'h0) | (_wdata_0_value_4_T ? data_3 : 32'h0) + | (_wdata_0_value_5_T ? data_4 : 32'h0) | (_wdata_0_value_6_T ? data_5 : 32'h0) + | (_wdata_0_value_7_T ? data_6 : 32'h0) | (_wdata_0_value_8_T ? data_7 : 32'h0) + | (_wdata_0_value_9_T ? data_8 : 32'h0) | (_wdata_0_value_10_T ? data_9 : 32'h0) + | (_wdata_0_value_11_T ? data_10 : 32'h0) + | (_wdata_0_value_12_T ? data_11 : 32'h0) + | (_wdata_0_value_13_T ? data_12 : 32'h0) + | (_wdata_0_value_14_T ? data_13 : 32'h0) + | (_wdata_0_value_15_T ? data_14 : 32'h0) + | (_wdata_0_value_16_T ? data_15 : 32'h0) + | (_wdata_0_value_17_T ? data_16 : 32'h0) + | (_wdata_0_value_18_T ? data_17 : 32'h0) + | (_wdata_0_value_19_T ? data_18 : 32'h0) + | (_wdata_0_value_20_T ? data_19 : 32'h0) + | (_wdata_0_value_21_T ? data_20 : 32'h0) + | (_wdata_0_value_22_T ? data_21 : 32'h0) + | (_wdata_0_value_23_T ? data_22 : 32'h0) + | (_wdata_0_value_24_T ? data_23 : 32'h0) + | (_wdata_0_value_25_T ? data_24 : 32'h0) + | (_wdata_0_value_26_T ? data_25 : 32'h0) + | (_wdata_0_value_27_T ? data_26 : 32'h0) + | (_wdata_0_value_28_T ? data_27 : 32'h0) + | (_wdata_0_value_29_T ? data_28 : 32'h0) + | (_wdata_0_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_0_addr) ? data_30 : 32'h0) + : rdata_0_value_5_0; + wire _wdata_1_value_1_T = io_readAddr_1_addr == 5'h1; + wire _wdata_1_value_2_T = io_readAddr_1_addr == 5'h2; + wire _wdata_1_value_3_T = io_readAddr_1_addr == 5'h3; + wire _wdata_1_value_4_T = io_readAddr_1_addr == 5'h4; + wire _wdata_1_value_5_T = io_readAddr_1_addr == 5'h5; + wire _wdata_1_value_6_T = io_readAddr_1_addr == 5'h6; + wire _wdata_1_value_7_T = io_readAddr_1_addr == 5'h7; + wire _wdata_1_value_8_T = io_readAddr_1_addr == 5'h8; + wire _wdata_1_value_9_T = io_readAddr_1_addr == 5'h9; + wire _wdata_1_value_10_T = io_readAddr_1_addr == 5'hA; + wire _wdata_1_value_11_T = io_readAddr_1_addr == 5'hB; + wire _wdata_1_value_12_T = io_readAddr_1_addr == 5'hC; + wire _wdata_1_value_13_T = io_readAddr_1_addr == 5'hD; + wire _wdata_1_value_14_T = io_readAddr_1_addr == 5'hE; + wire _wdata_1_value_15_T = io_readAddr_1_addr == 5'hF; + wire _wdata_1_value_16_T = io_readAddr_1_addr == 5'h10; + wire _wdata_1_value_17_T = io_readAddr_1_addr == 5'h11; + wire _wdata_1_value_18_T = io_readAddr_1_addr == 5'h12; + wire _wdata_1_value_19_T = io_readAddr_1_addr == 5'h13; + wire _wdata_1_value_20_T = io_readAddr_1_addr == 5'h14; + wire _wdata_1_value_21_T = io_readAddr_1_addr == 5'h15; + wire _wdata_1_value_22_T = io_readAddr_1_addr == 5'h16; + wire _wdata_1_value_23_T = io_readAddr_1_addr == 5'h17; + wire _wdata_1_value_24_T = io_readAddr_1_addr == 5'h18; + wire _wdata_1_value_25_T = io_readAddr_1_addr == 5'h19; + wire _wdata_1_value_26_T = io_readAddr_1_addr == 5'h1A; + wire _wdata_1_value_27_T = io_readAddr_1_addr == 5'h1B; + wire _wdata_1_value_28_T = io_readAddr_1_addr == 5'h1C; + wire _wdata_1_value_29_T = io_readAddr_1_addr == 5'h1D; + wire _wdata_1_value_30_T = io_readAddr_1_addr == 5'h1E; + wire [31:0] rwdata_1 = + io_readAddr_1_addr == 5'h0 | _wdata_1_value_1_T & (|_writeValid_1_T) + | _wdata_1_value_2_T & (|_writeValid_2_T) | _wdata_1_value_3_T & (|_writeValid_3_T) + | _wdata_1_value_4_T & (|_writeValid_4_T) | _wdata_1_value_5_T & (|_writeValid_5_T) + | _wdata_1_value_6_T & (|_writeValid_6_T) | _wdata_1_value_7_T & (|_writeValid_7_T) + | _wdata_1_value_8_T & (|_writeValid_8_T) | _wdata_1_value_9_T & (|_writeValid_9_T) + | _wdata_1_value_10_T & (|_writeValid_10_T) | _wdata_1_value_11_T + & (|_writeValid_11_T) | _wdata_1_value_12_T & (|_writeValid_12_T) + | _wdata_1_value_13_T & (|_writeValid_13_T) | _wdata_1_value_14_T + & (|_writeValid_14_T) | _wdata_1_value_15_T & (|_writeValid_15_T) + | _wdata_1_value_16_T & (|_writeValid_16_T) | _wdata_1_value_17_T + & (|_writeValid_17_T) | _wdata_1_value_18_T & (|_writeValid_18_T) + | _wdata_1_value_19_T & (|_writeValid_19_T) | _wdata_1_value_20_T + & (|_writeValid_20_T) | _wdata_1_value_21_T & (|_writeValid_21_T) + | _wdata_1_value_22_T & (|_writeValid_22_T) | _wdata_1_value_23_T + & (|_writeValid_23_T) | _wdata_1_value_24_T & (|_writeValid_24_T) + | _wdata_1_value_25_T & (|_writeValid_25_T) | _wdata_1_value_26_T + & (|_writeValid_26_T) | _wdata_1_value_27_T & (|_writeValid_27_T) + | _wdata_1_value_28_T & (|_writeValid_28_T) | _wdata_1_value_29_T + & (|_writeValid_29_T) | _wdata_1_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_1_addr) & (|_writeValid_31_T) + ? (_wdata_1_value_1_T ? data : 32'h0) | (_wdata_1_value_2_T ? data_1 : 32'h0) + | (_wdata_1_value_3_T ? data_2 : 32'h0) | (_wdata_1_value_4_T ? data_3 : 32'h0) + | (_wdata_1_value_5_T ? data_4 : 32'h0) | (_wdata_1_value_6_T ? data_5 : 32'h0) + | (_wdata_1_value_7_T ? data_6 : 32'h0) | (_wdata_1_value_8_T ? data_7 : 32'h0) + | (_wdata_1_value_9_T ? data_8 : 32'h0) | (_wdata_1_value_10_T ? data_9 : 32'h0) + | (_wdata_1_value_11_T ? data_10 : 32'h0) + | (_wdata_1_value_12_T ? data_11 : 32'h0) + | (_wdata_1_value_13_T ? data_12 : 32'h0) + | (_wdata_1_value_14_T ? data_13 : 32'h0) + | (_wdata_1_value_15_T ? data_14 : 32'h0) + | (_wdata_1_value_16_T ? data_15 : 32'h0) + | (_wdata_1_value_17_T ? data_16 : 32'h0) + | (_wdata_1_value_18_T ? data_17 : 32'h0) + | (_wdata_1_value_19_T ? data_18 : 32'h0) + | (_wdata_1_value_20_T ? data_19 : 32'h0) + | (_wdata_1_value_21_T ? data_20 : 32'h0) + | (_wdata_1_value_22_T ? data_21 : 32'h0) + | (_wdata_1_value_23_T ? data_22 : 32'h0) + | (_wdata_1_value_24_T ? data_23 : 32'h0) + | (_wdata_1_value_25_T ? data_24 : 32'h0) + | (_wdata_1_value_26_T ? data_25 : 32'h0) + | (_wdata_1_value_27_T ? data_26 : 32'h0) + | (_wdata_1_value_28_T ? data_27 : 32'h0) + | (_wdata_1_value_29_T ? data_28 : 32'h0) + | (_wdata_1_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_1_addr) ? data_30 : 32'h0) + : (_wdata_1_value_1_T ? regfile_1 : 32'h0) + | (_wdata_1_value_2_T ? regfile_2 : 32'h0) + | (_wdata_1_value_3_T ? regfile_3 : 32'h0) + | (_wdata_1_value_4_T ? regfile_4 : 32'h0) + | (_wdata_1_value_5_T ? regfile_5 : 32'h0) + | (_wdata_1_value_6_T ? regfile_6 : 32'h0) + | (_wdata_1_value_7_T ? regfile_7 : 32'h0) + | (_wdata_1_value_8_T ? regfile_8 : 32'h0) + | (_wdata_1_value_9_T ? regfile_9 : 32'h0) + | (_wdata_1_value_10_T ? regfile_10 : 32'h0) + | (_wdata_1_value_11_T ? regfile_11 : 32'h0) + | (_wdata_1_value_12_T ? regfile_12 : 32'h0) + | (_wdata_1_value_13_T ? regfile_13 : 32'h0) + | (_wdata_1_value_14_T ? regfile_14 : 32'h0) + | (_wdata_1_value_15_T ? regfile_15 : 32'h0) + | (_wdata_1_value_16_T ? regfile_16 : 32'h0) + | (_wdata_1_value_17_T ? regfile_17 : 32'h0) + | (_wdata_1_value_18_T ? regfile_18 : 32'h0) + | (_wdata_1_value_19_T ? regfile_19 : 32'h0) + | (_wdata_1_value_20_T ? regfile_20 : 32'h0) + | (_wdata_1_value_21_T ? regfile_21 : 32'h0) + | (_wdata_1_value_22_T ? regfile_22 : 32'h0) + | (_wdata_1_value_23_T ? regfile_23 : 32'h0) + | (_wdata_1_value_24_T ? regfile_24 : 32'h0) + | (_wdata_1_value_25_T ? regfile_25 : 32'h0) + | (_wdata_1_value_26_T ? regfile_26 : 32'h0) + | (_wdata_1_value_27_T ? regfile_27 : 32'h0) + | (_wdata_1_value_28_T ? regfile_28 : 32'h0) + | (_wdata_1_value_29_T ? regfile_29 : 32'h0) + | (_wdata_1_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_1_addr) ? regfile_31 : 32'h0); + wire _wdata_2_value_1_T = io_readAddr_2_addr == 5'h1; + wire _wdata_2_value_2_T = io_readAddr_2_addr == 5'h2; + wire _wdata_2_value_3_T = io_readAddr_2_addr == 5'h3; + wire _wdata_2_value_4_T = io_readAddr_2_addr == 5'h4; + wire _wdata_2_value_5_T = io_readAddr_2_addr == 5'h5; + wire _wdata_2_value_6_T = io_readAddr_2_addr == 5'h6; + wire _wdata_2_value_7_T = io_readAddr_2_addr == 5'h7; + wire _wdata_2_value_8_T = io_readAddr_2_addr == 5'h8; + wire _wdata_2_value_9_T = io_readAddr_2_addr == 5'h9; + wire _wdata_2_value_10_T = io_readAddr_2_addr == 5'hA; + wire _wdata_2_value_11_T = io_readAddr_2_addr == 5'hB; + wire _wdata_2_value_12_T = io_readAddr_2_addr == 5'hC; + wire _wdata_2_value_13_T = io_readAddr_2_addr == 5'hD; + wire _wdata_2_value_14_T = io_readAddr_2_addr == 5'hE; + wire _wdata_2_value_15_T = io_readAddr_2_addr == 5'hF; + wire _wdata_2_value_16_T = io_readAddr_2_addr == 5'h10; + wire _wdata_2_value_17_T = io_readAddr_2_addr == 5'h11; + wire _wdata_2_value_18_T = io_readAddr_2_addr == 5'h12; + wire _wdata_2_value_19_T = io_readAddr_2_addr == 5'h13; + wire _wdata_2_value_20_T = io_readAddr_2_addr == 5'h14; + wire _wdata_2_value_21_T = io_readAddr_2_addr == 5'h15; + wire _wdata_2_value_22_T = io_readAddr_2_addr == 5'h16; + wire _wdata_2_value_23_T = io_readAddr_2_addr == 5'h17; + wire _wdata_2_value_24_T = io_readAddr_2_addr == 5'h18; + wire _wdata_2_value_25_T = io_readAddr_2_addr == 5'h19; + wire _wdata_2_value_26_T = io_readAddr_2_addr == 5'h1A; + wire _wdata_2_value_27_T = io_readAddr_2_addr == 5'h1B; + wire _wdata_2_value_28_T = io_readAddr_2_addr == 5'h1C; + wire _wdata_2_value_29_T = io_readAddr_2_addr == 5'h1D; + wire _wdata_2_value_30_T = io_readAddr_2_addr == 5'h1E; + wire [31:0] rdata_2_value_5_0 = + (_wdata_2_value_1_T ? regfile_1 : 32'h0) | (_wdata_2_value_2_T ? regfile_2 : 32'h0) + | (_wdata_2_value_3_T ? regfile_3 : 32'h0) | (_wdata_2_value_4_T ? regfile_4 : 32'h0) + | (_wdata_2_value_5_T ? regfile_5 : 32'h0) | (_wdata_2_value_6_T ? regfile_6 : 32'h0) + | (_wdata_2_value_7_T ? regfile_7 : 32'h0) | (_wdata_2_value_8_T ? regfile_8 : 32'h0) + | (_wdata_2_value_9_T ? regfile_9 : 32'h0) + | (_wdata_2_value_10_T ? regfile_10 : 32'h0) + | (_wdata_2_value_11_T ? regfile_11 : 32'h0) + | (_wdata_2_value_12_T ? regfile_12 : 32'h0) + | (_wdata_2_value_13_T ? regfile_13 : 32'h0) + | (_wdata_2_value_14_T ? regfile_14 : 32'h0) + | (_wdata_2_value_15_T ? regfile_15 : 32'h0) + | (_wdata_2_value_16_T ? regfile_16 : 32'h0) + | (_wdata_2_value_17_T ? regfile_17 : 32'h0) + | (_wdata_2_value_18_T ? regfile_18 : 32'h0) + | (_wdata_2_value_19_T ? regfile_19 : 32'h0) + | (_wdata_2_value_20_T ? regfile_20 : 32'h0) + | (_wdata_2_value_21_T ? regfile_21 : 32'h0) + | (_wdata_2_value_22_T ? regfile_22 : 32'h0) + | (_wdata_2_value_23_T ? regfile_23 : 32'h0) + | (_wdata_2_value_24_T ? regfile_24 : 32'h0) + | (_wdata_2_value_25_T ? regfile_25 : 32'h0) + | (_wdata_2_value_26_T ? regfile_26 : 32'h0) + | (_wdata_2_value_27_T ? regfile_27 : 32'h0) + | (_wdata_2_value_28_T ? regfile_28 : 32'h0) + | (_wdata_2_value_29_T ? regfile_29 : 32'h0) + | (_wdata_2_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_2_addr) ? regfile_31 : 32'h0); + wire [31:0] rwdata_2 = + io_readAddr_2_addr == 5'h0 | _wdata_2_value_1_T & (|_writeValid_1_T) + | _wdata_2_value_2_T & (|_writeValid_2_T) | _wdata_2_value_3_T & (|_writeValid_3_T) + | _wdata_2_value_4_T & (|_writeValid_4_T) | _wdata_2_value_5_T & (|_writeValid_5_T) + | _wdata_2_value_6_T & (|_writeValid_6_T) | _wdata_2_value_7_T & (|_writeValid_7_T) + | _wdata_2_value_8_T & (|_writeValid_8_T) | _wdata_2_value_9_T & (|_writeValid_9_T) + | _wdata_2_value_10_T & (|_writeValid_10_T) | _wdata_2_value_11_T + & (|_writeValid_11_T) | _wdata_2_value_12_T & (|_writeValid_12_T) + | _wdata_2_value_13_T & (|_writeValid_13_T) | _wdata_2_value_14_T + & (|_writeValid_14_T) | _wdata_2_value_15_T & (|_writeValid_15_T) + | _wdata_2_value_16_T & (|_writeValid_16_T) | _wdata_2_value_17_T + & (|_writeValid_17_T) | _wdata_2_value_18_T & (|_writeValid_18_T) + | _wdata_2_value_19_T & (|_writeValid_19_T) | _wdata_2_value_20_T + & (|_writeValid_20_T) | _wdata_2_value_21_T & (|_writeValid_21_T) + | _wdata_2_value_22_T & (|_writeValid_22_T) | _wdata_2_value_23_T + & (|_writeValid_23_T) | _wdata_2_value_24_T & (|_writeValid_24_T) + | _wdata_2_value_25_T & (|_writeValid_25_T) | _wdata_2_value_26_T + & (|_writeValid_26_T) | _wdata_2_value_27_T & (|_writeValid_27_T) + | _wdata_2_value_28_T & (|_writeValid_28_T) | _wdata_2_value_29_T + & (|_writeValid_29_T) | _wdata_2_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_2_addr) & (|_writeValid_31_T) + ? (_wdata_2_value_1_T ? data : 32'h0) | (_wdata_2_value_2_T ? data_1 : 32'h0) + | (_wdata_2_value_3_T ? data_2 : 32'h0) | (_wdata_2_value_4_T ? data_3 : 32'h0) + | (_wdata_2_value_5_T ? data_4 : 32'h0) | (_wdata_2_value_6_T ? data_5 : 32'h0) + | (_wdata_2_value_7_T ? data_6 : 32'h0) | (_wdata_2_value_8_T ? data_7 : 32'h0) + | (_wdata_2_value_9_T ? data_8 : 32'h0) | (_wdata_2_value_10_T ? data_9 : 32'h0) + | (_wdata_2_value_11_T ? data_10 : 32'h0) + | (_wdata_2_value_12_T ? data_11 : 32'h0) + | (_wdata_2_value_13_T ? data_12 : 32'h0) + | (_wdata_2_value_14_T ? data_13 : 32'h0) + | (_wdata_2_value_15_T ? data_14 : 32'h0) + | (_wdata_2_value_16_T ? data_15 : 32'h0) + | (_wdata_2_value_17_T ? data_16 : 32'h0) + | (_wdata_2_value_18_T ? data_17 : 32'h0) + | (_wdata_2_value_19_T ? data_18 : 32'h0) + | (_wdata_2_value_20_T ? data_19 : 32'h0) + | (_wdata_2_value_21_T ? data_20 : 32'h0) + | (_wdata_2_value_22_T ? data_21 : 32'h0) + | (_wdata_2_value_23_T ? data_22 : 32'h0) + | (_wdata_2_value_24_T ? data_23 : 32'h0) + | (_wdata_2_value_25_T ? data_24 : 32'h0) + | (_wdata_2_value_26_T ? data_25 : 32'h0) + | (_wdata_2_value_27_T ? data_26 : 32'h0) + | (_wdata_2_value_28_T ? data_27 : 32'h0) + | (_wdata_2_value_29_T ? data_28 : 32'h0) + | (_wdata_2_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_2_addr) ? data_30 : 32'h0) + : rdata_2_value_5_0; + wire _wdata_3_value_1_T = io_readAddr_3_addr == 5'h1; + wire _wdata_3_value_2_T = io_readAddr_3_addr == 5'h2; + wire _wdata_3_value_3_T = io_readAddr_3_addr == 5'h3; + wire _wdata_3_value_4_T = io_readAddr_3_addr == 5'h4; + wire _wdata_3_value_5_T = io_readAddr_3_addr == 5'h5; + wire _wdata_3_value_6_T = io_readAddr_3_addr == 5'h6; + wire _wdata_3_value_7_T = io_readAddr_3_addr == 5'h7; + wire _wdata_3_value_8_T = io_readAddr_3_addr == 5'h8; + wire _wdata_3_value_9_T = io_readAddr_3_addr == 5'h9; + wire _wdata_3_value_10_T = io_readAddr_3_addr == 5'hA; + wire _wdata_3_value_11_T = io_readAddr_3_addr == 5'hB; + wire _wdata_3_value_12_T = io_readAddr_3_addr == 5'hC; + wire _wdata_3_value_13_T = io_readAddr_3_addr == 5'hD; + wire _wdata_3_value_14_T = io_readAddr_3_addr == 5'hE; + wire _wdata_3_value_15_T = io_readAddr_3_addr == 5'hF; + wire _wdata_3_value_16_T = io_readAddr_3_addr == 5'h10; + wire _wdata_3_value_17_T = io_readAddr_3_addr == 5'h11; + wire _wdata_3_value_18_T = io_readAddr_3_addr == 5'h12; + wire _wdata_3_value_19_T = io_readAddr_3_addr == 5'h13; + wire _wdata_3_value_20_T = io_readAddr_3_addr == 5'h14; + wire _wdata_3_value_21_T = io_readAddr_3_addr == 5'h15; + wire _wdata_3_value_22_T = io_readAddr_3_addr == 5'h16; + wire _wdata_3_value_23_T = io_readAddr_3_addr == 5'h17; + wire _wdata_3_value_24_T = io_readAddr_3_addr == 5'h18; + wire _wdata_3_value_25_T = io_readAddr_3_addr == 5'h19; + wire _wdata_3_value_26_T = io_readAddr_3_addr == 5'h1A; + wire _wdata_3_value_27_T = io_readAddr_3_addr == 5'h1B; + wire _wdata_3_value_28_T = io_readAddr_3_addr == 5'h1C; + wire _wdata_3_value_29_T = io_readAddr_3_addr == 5'h1D; + wire _wdata_3_value_30_T = io_readAddr_3_addr == 5'h1E; + wire [31:0] rwdata_3 = + io_readAddr_3_addr == 5'h0 | _wdata_3_value_1_T & (|_writeValid_1_T) + | _wdata_3_value_2_T & (|_writeValid_2_T) | _wdata_3_value_3_T & (|_writeValid_3_T) + | _wdata_3_value_4_T & (|_writeValid_4_T) | _wdata_3_value_5_T & (|_writeValid_5_T) + | _wdata_3_value_6_T & (|_writeValid_6_T) | _wdata_3_value_7_T & (|_writeValid_7_T) + | _wdata_3_value_8_T & (|_writeValid_8_T) | _wdata_3_value_9_T & (|_writeValid_9_T) + | _wdata_3_value_10_T & (|_writeValid_10_T) | _wdata_3_value_11_T + & (|_writeValid_11_T) | _wdata_3_value_12_T & (|_writeValid_12_T) + | _wdata_3_value_13_T & (|_writeValid_13_T) | _wdata_3_value_14_T + & (|_writeValid_14_T) | _wdata_3_value_15_T & (|_writeValid_15_T) + | _wdata_3_value_16_T & (|_writeValid_16_T) | _wdata_3_value_17_T + & (|_writeValid_17_T) | _wdata_3_value_18_T & (|_writeValid_18_T) + | _wdata_3_value_19_T & (|_writeValid_19_T) | _wdata_3_value_20_T + & (|_writeValid_20_T) | _wdata_3_value_21_T & (|_writeValid_21_T) + | _wdata_3_value_22_T & (|_writeValid_22_T) | _wdata_3_value_23_T + & (|_writeValid_23_T) | _wdata_3_value_24_T & (|_writeValid_24_T) + | _wdata_3_value_25_T & (|_writeValid_25_T) | _wdata_3_value_26_T + & (|_writeValid_26_T) | _wdata_3_value_27_T & (|_writeValid_27_T) + | _wdata_3_value_28_T & (|_writeValid_28_T) | _wdata_3_value_29_T + & (|_writeValid_29_T) | _wdata_3_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_3_addr) & (|_writeValid_31_T) + ? (_wdata_3_value_1_T ? data : 32'h0) | (_wdata_3_value_2_T ? data_1 : 32'h0) + | (_wdata_3_value_3_T ? data_2 : 32'h0) | (_wdata_3_value_4_T ? data_3 : 32'h0) + | (_wdata_3_value_5_T ? data_4 : 32'h0) | (_wdata_3_value_6_T ? data_5 : 32'h0) + | (_wdata_3_value_7_T ? data_6 : 32'h0) | (_wdata_3_value_8_T ? data_7 : 32'h0) + | (_wdata_3_value_9_T ? data_8 : 32'h0) | (_wdata_3_value_10_T ? data_9 : 32'h0) + | (_wdata_3_value_11_T ? data_10 : 32'h0) + | (_wdata_3_value_12_T ? data_11 : 32'h0) + | (_wdata_3_value_13_T ? data_12 : 32'h0) + | (_wdata_3_value_14_T ? data_13 : 32'h0) + | (_wdata_3_value_15_T ? data_14 : 32'h0) + | (_wdata_3_value_16_T ? data_15 : 32'h0) + | (_wdata_3_value_17_T ? data_16 : 32'h0) + | (_wdata_3_value_18_T ? data_17 : 32'h0) + | (_wdata_3_value_19_T ? data_18 : 32'h0) + | (_wdata_3_value_20_T ? data_19 : 32'h0) + | (_wdata_3_value_21_T ? data_20 : 32'h0) + | (_wdata_3_value_22_T ? data_21 : 32'h0) + | (_wdata_3_value_23_T ? data_22 : 32'h0) + | (_wdata_3_value_24_T ? data_23 : 32'h0) + | (_wdata_3_value_25_T ? data_24 : 32'h0) + | (_wdata_3_value_26_T ? data_25 : 32'h0) + | (_wdata_3_value_27_T ? data_26 : 32'h0) + | (_wdata_3_value_28_T ? data_27 : 32'h0) + | (_wdata_3_value_29_T ? data_28 : 32'h0) + | (_wdata_3_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_3_addr) ? data_30 : 32'h0) + : (_wdata_3_value_1_T ? regfile_1 : 32'h0) + | (_wdata_3_value_2_T ? regfile_2 : 32'h0) + | (_wdata_3_value_3_T ? regfile_3 : 32'h0) + | (_wdata_3_value_4_T ? regfile_4 : 32'h0) + | (_wdata_3_value_5_T ? regfile_5 : 32'h0) + | (_wdata_3_value_6_T ? regfile_6 : 32'h0) + | (_wdata_3_value_7_T ? regfile_7 : 32'h0) + | (_wdata_3_value_8_T ? regfile_8 : 32'h0) + | (_wdata_3_value_9_T ? regfile_9 : 32'h0) + | (_wdata_3_value_10_T ? regfile_10 : 32'h0) + | (_wdata_3_value_11_T ? regfile_11 : 32'h0) + | (_wdata_3_value_12_T ? regfile_12 : 32'h0) + | (_wdata_3_value_13_T ? regfile_13 : 32'h0) + | (_wdata_3_value_14_T ? regfile_14 : 32'h0) + | (_wdata_3_value_15_T ? regfile_15 : 32'h0) + | (_wdata_3_value_16_T ? regfile_16 : 32'h0) + | (_wdata_3_value_17_T ? regfile_17 : 32'h0) + | (_wdata_3_value_18_T ? regfile_18 : 32'h0) + | (_wdata_3_value_19_T ? regfile_19 : 32'h0) + | (_wdata_3_value_20_T ? regfile_20 : 32'h0) + | (_wdata_3_value_21_T ? regfile_21 : 32'h0) + | (_wdata_3_value_22_T ? regfile_22 : 32'h0) + | (_wdata_3_value_23_T ? regfile_23 : 32'h0) + | (_wdata_3_value_24_T ? regfile_24 : 32'h0) + | (_wdata_3_value_25_T ? regfile_25 : 32'h0) + | (_wdata_3_value_26_T ? regfile_26 : 32'h0) + | (_wdata_3_value_27_T ? regfile_27 : 32'h0) + | (_wdata_3_value_28_T ? regfile_28 : 32'h0) + | (_wdata_3_value_29_T ? regfile_29 : 32'h0) + | (_wdata_3_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_3_addr) ? regfile_31 : 32'h0); + wire _wdata_4_value_1_T = io_readAddr_4_addr == 5'h1; + wire _wdata_4_value_2_T = io_readAddr_4_addr == 5'h2; + wire _wdata_4_value_3_T = io_readAddr_4_addr == 5'h3; + wire _wdata_4_value_4_T = io_readAddr_4_addr == 5'h4; + wire _wdata_4_value_5_T = io_readAddr_4_addr == 5'h5; + wire _wdata_4_value_6_T = io_readAddr_4_addr == 5'h6; + wire _wdata_4_value_7_T = io_readAddr_4_addr == 5'h7; + wire _wdata_4_value_8_T = io_readAddr_4_addr == 5'h8; + wire _wdata_4_value_9_T = io_readAddr_4_addr == 5'h9; + wire _wdata_4_value_10_T = io_readAddr_4_addr == 5'hA; + wire _wdata_4_value_11_T = io_readAddr_4_addr == 5'hB; + wire _wdata_4_value_12_T = io_readAddr_4_addr == 5'hC; + wire _wdata_4_value_13_T = io_readAddr_4_addr == 5'hD; + wire _wdata_4_value_14_T = io_readAddr_4_addr == 5'hE; + wire _wdata_4_value_15_T = io_readAddr_4_addr == 5'hF; + wire _wdata_4_value_16_T = io_readAddr_4_addr == 5'h10; + wire _wdata_4_value_17_T = io_readAddr_4_addr == 5'h11; + wire _wdata_4_value_18_T = io_readAddr_4_addr == 5'h12; + wire _wdata_4_value_19_T = io_readAddr_4_addr == 5'h13; + wire _wdata_4_value_20_T = io_readAddr_4_addr == 5'h14; + wire _wdata_4_value_21_T = io_readAddr_4_addr == 5'h15; + wire _wdata_4_value_22_T = io_readAddr_4_addr == 5'h16; + wire _wdata_4_value_23_T = io_readAddr_4_addr == 5'h17; + wire _wdata_4_value_24_T = io_readAddr_4_addr == 5'h18; + wire _wdata_4_value_25_T = io_readAddr_4_addr == 5'h19; + wire _wdata_4_value_26_T = io_readAddr_4_addr == 5'h1A; + wire _wdata_4_value_27_T = io_readAddr_4_addr == 5'h1B; + wire _wdata_4_value_28_T = io_readAddr_4_addr == 5'h1C; + wire _wdata_4_value_29_T = io_readAddr_4_addr == 5'h1D; + wire _wdata_4_value_30_T = io_readAddr_4_addr == 5'h1E; + wire [31:0] rdata_4_value_5_0 = + (_wdata_4_value_1_T ? regfile_1 : 32'h0) | (_wdata_4_value_2_T ? regfile_2 : 32'h0) + | (_wdata_4_value_3_T ? regfile_3 : 32'h0) | (_wdata_4_value_4_T ? regfile_4 : 32'h0) + | (_wdata_4_value_5_T ? regfile_5 : 32'h0) | (_wdata_4_value_6_T ? regfile_6 : 32'h0) + | (_wdata_4_value_7_T ? regfile_7 : 32'h0) | (_wdata_4_value_8_T ? regfile_8 : 32'h0) + | (_wdata_4_value_9_T ? regfile_9 : 32'h0) + | (_wdata_4_value_10_T ? regfile_10 : 32'h0) + | (_wdata_4_value_11_T ? regfile_11 : 32'h0) + | (_wdata_4_value_12_T ? regfile_12 : 32'h0) + | (_wdata_4_value_13_T ? regfile_13 : 32'h0) + | (_wdata_4_value_14_T ? regfile_14 : 32'h0) + | (_wdata_4_value_15_T ? regfile_15 : 32'h0) + | (_wdata_4_value_16_T ? regfile_16 : 32'h0) + | (_wdata_4_value_17_T ? regfile_17 : 32'h0) + | (_wdata_4_value_18_T ? regfile_18 : 32'h0) + | (_wdata_4_value_19_T ? regfile_19 : 32'h0) + | (_wdata_4_value_20_T ? regfile_20 : 32'h0) + | (_wdata_4_value_21_T ? regfile_21 : 32'h0) + | (_wdata_4_value_22_T ? regfile_22 : 32'h0) + | (_wdata_4_value_23_T ? regfile_23 : 32'h0) + | (_wdata_4_value_24_T ? regfile_24 : 32'h0) + | (_wdata_4_value_25_T ? regfile_25 : 32'h0) + | (_wdata_4_value_26_T ? regfile_26 : 32'h0) + | (_wdata_4_value_27_T ? regfile_27 : 32'h0) + | (_wdata_4_value_28_T ? regfile_28 : 32'h0) + | (_wdata_4_value_29_T ? regfile_29 : 32'h0) + | (_wdata_4_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_4_addr) ? regfile_31 : 32'h0); + wire [31:0] rwdata_4 = + io_readAddr_4_addr == 5'h0 | _wdata_4_value_1_T & (|_writeValid_1_T) + | _wdata_4_value_2_T & (|_writeValid_2_T) | _wdata_4_value_3_T & (|_writeValid_3_T) + | _wdata_4_value_4_T & (|_writeValid_4_T) | _wdata_4_value_5_T & (|_writeValid_5_T) + | _wdata_4_value_6_T & (|_writeValid_6_T) | _wdata_4_value_7_T & (|_writeValid_7_T) + | _wdata_4_value_8_T & (|_writeValid_8_T) | _wdata_4_value_9_T & (|_writeValid_9_T) + | _wdata_4_value_10_T & (|_writeValid_10_T) | _wdata_4_value_11_T + & (|_writeValid_11_T) | _wdata_4_value_12_T & (|_writeValid_12_T) + | _wdata_4_value_13_T & (|_writeValid_13_T) | _wdata_4_value_14_T + & (|_writeValid_14_T) | _wdata_4_value_15_T & (|_writeValid_15_T) + | _wdata_4_value_16_T & (|_writeValid_16_T) | _wdata_4_value_17_T + & (|_writeValid_17_T) | _wdata_4_value_18_T & (|_writeValid_18_T) + | _wdata_4_value_19_T & (|_writeValid_19_T) | _wdata_4_value_20_T + & (|_writeValid_20_T) | _wdata_4_value_21_T & (|_writeValid_21_T) + | _wdata_4_value_22_T & (|_writeValid_22_T) | _wdata_4_value_23_T + & (|_writeValid_23_T) | _wdata_4_value_24_T & (|_writeValid_24_T) + | _wdata_4_value_25_T & (|_writeValid_25_T) | _wdata_4_value_26_T + & (|_writeValid_26_T) | _wdata_4_value_27_T & (|_writeValid_27_T) + | _wdata_4_value_28_T & (|_writeValid_28_T) | _wdata_4_value_29_T + & (|_writeValid_29_T) | _wdata_4_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_4_addr) & (|_writeValid_31_T) + ? (_wdata_4_value_1_T ? data : 32'h0) | (_wdata_4_value_2_T ? data_1 : 32'h0) + | (_wdata_4_value_3_T ? data_2 : 32'h0) | (_wdata_4_value_4_T ? data_3 : 32'h0) + | (_wdata_4_value_5_T ? data_4 : 32'h0) | (_wdata_4_value_6_T ? data_5 : 32'h0) + | (_wdata_4_value_7_T ? data_6 : 32'h0) | (_wdata_4_value_8_T ? data_7 : 32'h0) + | (_wdata_4_value_9_T ? data_8 : 32'h0) | (_wdata_4_value_10_T ? data_9 : 32'h0) + | (_wdata_4_value_11_T ? data_10 : 32'h0) + | (_wdata_4_value_12_T ? data_11 : 32'h0) + | (_wdata_4_value_13_T ? data_12 : 32'h0) + | (_wdata_4_value_14_T ? data_13 : 32'h0) + | (_wdata_4_value_15_T ? data_14 : 32'h0) + | (_wdata_4_value_16_T ? data_15 : 32'h0) + | (_wdata_4_value_17_T ? data_16 : 32'h0) + | (_wdata_4_value_18_T ? data_17 : 32'h0) + | (_wdata_4_value_19_T ? data_18 : 32'h0) + | (_wdata_4_value_20_T ? data_19 : 32'h0) + | (_wdata_4_value_21_T ? data_20 : 32'h0) + | (_wdata_4_value_22_T ? data_21 : 32'h0) + | (_wdata_4_value_23_T ? data_22 : 32'h0) + | (_wdata_4_value_24_T ? data_23 : 32'h0) + | (_wdata_4_value_25_T ? data_24 : 32'h0) + | (_wdata_4_value_26_T ? data_25 : 32'h0) + | (_wdata_4_value_27_T ? data_26 : 32'h0) + | (_wdata_4_value_28_T ? data_27 : 32'h0) + | (_wdata_4_value_29_T ? data_28 : 32'h0) + | (_wdata_4_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_4_addr) ? data_30 : 32'h0) + : rdata_4_value_5_0; + wire _wdata_5_value_1_T = io_readAddr_5_addr == 5'h1; + wire _wdata_5_value_2_T = io_readAddr_5_addr == 5'h2; + wire _wdata_5_value_3_T = io_readAddr_5_addr == 5'h3; + wire _wdata_5_value_4_T = io_readAddr_5_addr == 5'h4; + wire _wdata_5_value_5_T = io_readAddr_5_addr == 5'h5; + wire _wdata_5_value_6_T = io_readAddr_5_addr == 5'h6; + wire _wdata_5_value_7_T = io_readAddr_5_addr == 5'h7; + wire _wdata_5_value_8_T = io_readAddr_5_addr == 5'h8; + wire _wdata_5_value_9_T = io_readAddr_5_addr == 5'h9; + wire _wdata_5_value_10_T = io_readAddr_5_addr == 5'hA; + wire _wdata_5_value_11_T = io_readAddr_5_addr == 5'hB; + wire _wdata_5_value_12_T = io_readAddr_5_addr == 5'hC; + wire _wdata_5_value_13_T = io_readAddr_5_addr == 5'hD; + wire _wdata_5_value_14_T = io_readAddr_5_addr == 5'hE; + wire _wdata_5_value_15_T = io_readAddr_5_addr == 5'hF; + wire _wdata_5_value_16_T = io_readAddr_5_addr == 5'h10; + wire _wdata_5_value_17_T = io_readAddr_5_addr == 5'h11; + wire _wdata_5_value_18_T = io_readAddr_5_addr == 5'h12; + wire _wdata_5_value_19_T = io_readAddr_5_addr == 5'h13; + wire _wdata_5_value_20_T = io_readAddr_5_addr == 5'h14; + wire _wdata_5_value_21_T = io_readAddr_5_addr == 5'h15; + wire _wdata_5_value_22_T = io_readAddr_5_addr == 5'h16; + wire _wdata_5_value_23_T = io_readAddr_5_addr == 5'h17; + wire _wdata_5_value_24_T = io_readAddr_5_addr == 5'h18; + wire _wdata_5_value_25_T = io_readAddr_5_addr == 5'h19; + wire _wdata_5_value_26_T = io_readAddr_5_addr == 5'h1A; + wire _wdata_5_value_27_T = io_readAddr_5_addr == 5'h1B; + wire _wdata_5_value_28_T = io_readAddr_5_addr == 5'h1C; + wire _wdata_5_value_29_T = io_readAddr_5_addr == 5'h1D; + wire _wdata_5_value_30_T = io_readAddr_5_addr == 5'h1E; + wire [31:0] rwdata_5 = + io_readAddr_5_addr == 5'h0 | _wdata_5_value_1_T & (|_writeValid_1_T) + | _wdata_5_value_2_T & (|_writeValid_2_T) | _wdata_5_value_3_T & (|_writeValid_3_T) + | _wdata_5_value_4_T & (|_writeValid_4_T) | _wdata_5_value_5_T & (|_writeValid_5_T) + | _wdata_5_value_6_T & (|_writeValid_6_T) | _wdata_5_value_7_T & (|_writeValid_7_T) + | _wdata_5_value_8_T & (|_writeValid_8_T) | _wdata_5_value_9_T & (|_writeValid_9_T) + | _wdata_5_value_10_T & (|_writeValid_10_T) | _wdata_5_value_11_T + & (|_writeValid_11_T) | _wdata_5_value_12_T & (|_writeValid_12_T) + | _wdata_5_value_13_T & (|_writeValid_13_T) | _wdata_5_value_14_T + & (|_writeValid_14_T) | _wdata_5_value_15_T & (|_writeValid_15_T) + | _wdata_5_value_16_T & (|_writeValid_16_T) | _wdata_5_value_17_T + & (|_writeValid_17_T) | _wdata_5_value_18_T & (|_writeValid_18_T) + | _wdata_5_value_19_T & (|_writeValid_19_T) | _wdata_5_value_20_T + & (|_writeValid_20_T) | _wdata_5_value_21_T & (|_writeValid_21_T) + | _wdata_5_value_22_T & (|_writeValid_22_T) | _wdata_5_value_23_T + & (|_writeValid_23_T) | _wdata_5_value_24_T & (|_writeValid_24_T) + | _wdata_5_value_25_T & (|_writeValid_25_T) | _wdata_5_value_26_T + & (|_writeValid_26_T) | _wdata_5_value_27_T & (|_writeValid_27_T) + | _wdata_5_value_28_T & (|_writeValid_28_T) | _wdata_5_value_29_T + & (|_writeValid_29_T) | _wdata_5_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_5_addr) & (|_writeValid_31_T) + ? (_wdata_5_value_1_T ? data : 32'h0) | (_wdata_5_value_2_T ? data_1 : 32'h0) + | (_wdata_5_value_3_T ? data_2 : 32'h0) | (_wdata_5_value_4_T ? data_3 : 32'h0) + | (_wdata_5_value_5_T ? data_4 : 32'h0) | (_wdata_5_value_6_T ? data_5 : 32'h0) + | (_wdata_5_value_7_T ? data_6 : 32'h0) | (_wdata_5_value_8_T ? data_7 : 32'h0) + | (_wdata_5_value_9_T ? data_8 : 32'h0) | (_wdata_5_value_10_T ? data_9 : 32'h0) + | (_wdata_5_value_11_T ? data_10 : 32'h0) + | (_wdata_5_value_12_T ? data_11 : 32'h0) + | (_wdata_5_value_13_T ? data_12 : 32'h0) + | (_wdata_5_value_14_T ? data_13 : 32'h0) + | (_wdata_5_value_15_T ? data_14 : 32'h0) + | (_wdata_5_value_16_T ? data_15 : 32'h0) + | (_wdata_5_value_17_T ? data_16 : 32'h0) + | (_wdata_5_value_18_T ? data_17 : 32'h0) + | (_wdata_5_value_19_T ? data_18 : 32'h0) + | (_wdata_5_value_20_T ? data_19 : 32'h0) + | (_wdata_5_value_21_T ? data_20 : 32'h0) + | (_wdata_5_value_22_T ? data_21 : 32'h0) + | (_wdata_5_value_23_T ? data_22 : 32'h0) + | (_wdata_5_value_24_T ? data_23 : 32'h0) + | (_wdata_5_value_25_T ? data_24 : 32'h0) + | (_wdata_5_value_26_T ? data_25 : 32'h0) + | (_wdata_5_value_27_T ? data_26 : 32'h0) + | (_wdata_5_value_28_T ? data_27 : 32'h0) + | (_wdata_5_value_29_T ? data_28 : 32'h0) + | (_wdata_5_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_5_addr) ? data_30 : 32'h0) + : (_wdata_5_value_1_T ? regfile_1 : 32'h0) + | (_wdata_5_value_2_T ? regfile_2 : 32'h0) + | (_wdata_5_value_3_T ? regfile_3 : 32'h0) + | (_wdata_5_value_4_T ? regfile_4 : 32'h0) + | (_wdata_5_value_5_T ? regfile_5 : 32'h0) + | (_wdata_5_value_6_T ? regfile_6 : 32'h0) + | (_wdata_5_value_7_T ? regfile_7 : 32'h0) + | (_wdata_5_value_8_T ? regfile_8 : 32'h0) + | (_wdata_5_value_9_T ? regfile_9 : 32'h0) + | (_wdata_5_value_10_T ? regfile_10 : 32'h0) + | (_wdata_5_value_11_T ? regfile_11 : 32'h0) + | (_wdata_5_value_12_T ? regfile_12 : 32'h0) + | (_wdata_5_value_13_T ? regfile_13 : 32'h0) + | (_wdata_5_value_14_T ? regfile_14 : 32'h0) + | (_wdata_5_value_15_T ? regfile_15 : 32'h0) + | (_wdata_5_value_16_T ? regfile_16 : 32'h0) + | (_wdata_5_value_17_T ? regfile_17 : 32'h0) + | (_wdata_5_value_18_T ? regfile_18 : 32'h0) + | (_wdata_5_value_19_T ? regfile_19 : 32'h0) + | (_wdata_5_value_20_T ? regfile_20 : 32'h0) + | (_wdata_5_value_21_T ? regfile_21 : 32'h0) + | (_wdata_5_value_22_T ? regfile_22 : 32'h0) + | (_wdata_5_value_23_T ? regfile_23 : 32'h0) + | (_wdata_5_value_24_T ? regfile_24 : 32'h0) + | (_wdata_5_value_25_T ? regfile_25 : 32'h0) + | (_wdata_5_value_26_T ? regfile_26 : 32'h0) + | (_wdata_5_value_27_T ? regfile_27 : 32'h0) + | (_wdata_5_value_28_T ? regfile_28 : 32'h0) + | (_wdata_5_value_29_T ? regfile_29 : 32'h0) + | (_wdata_5_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_5_addr) ? regfile_31 : 32'h0); + wire _wdata_6_value_1_T = io_readAddr_6_addr == 5'h1; + wire _wdata_6_value_2_T = io_readAddr_6_addr == 5'h2; + wire _wdata_6_value_3_T = io_readAddr_6_addr == 5'h3; + wire _wdata_6_value_4_T = io_readAddr_6_addr == 5'h4; + wire _wdata_6_value_5_T = io_readAddr_6_addr == 5'h5; + wire _wdata_6_value_6_T = io_readAddr_6_addr == 5'h6; + wire _wdata_6_value_7_T = io_readAddr_6_addr == 5'h7; + wire _wdata_6_value_8_T = io_readAddr_6_addr == 5'h8; + wire _wdata_6_value_9_T = io_readAddr_6_addr == 5'h9; + wire _wdata_6_value_10_T = io_readAddr_6_addr == 5'hA; + wire _wdata_6_value_11_T = io_readAddr_6_addr == 5'hB; + wire _wdata_6_value_12_T = io_readAddr_6_addr == 5'hC; + wire _wdata_6_value_13_T = io_readAddr_6_addr == 5'hD; + wire _wdata_6_value_14_T = io_readAddr_6_addr == 5'hE; + wire _wdata_6_value_15_T = io_readAddr_6_addr == 5'hF; + wire _wdata_6_value_16_T = io_readAddr_6_addr == 5'h10; + wire _wdata_6_value_17_T = io_readAddr_6_addr == 5'h11; + wire _wdata_6_value_18_T = io_readAddr_6_addr == 5'h12; + wire _wdata_6_value_19_T = io_readAddr_6_addr == 5'h13; + wire _wdata_6_value_20_T = io_readAddr_6_addr == 5'h14; + wire _wdata_6_value_21_T = io_readAddr_6_addr == 5'h15; + wire _wdata_6_value_22_T = io_readAddr_6_addr == 5'h16; + wire _wdata_6_value_23_T = io_readAddr_6_addr == 5'h17; + wire _wdata_6_value_24_T = io_readAddr_6_addr == 5'h18; + wire _wdata_6_value_25_T = io_readAddr_6_addr == 5'h19; + wire _wdata_6_value_26_T = io_readAddr_6_addr == 5'h1A; + wire _wdata_6_value_27_T = io_readAddr_6_addr == 5'h1B; + wire _wdata_6_value_28_T = io_readAddr_6_addr == 5'h1C; + wire _wdata_6_value_29_T = io_readAddr_6_addr == 5'h1D; + wire _wdata_6_value_30_T = io_readAddr_6_addr == 5'h1E; + wire [31:0] rdata_6_value_5_0 = + (_wdata_6_value_1_T ? regfile_1 : 32'h0) | (_wdata_6_value_2_T ? regfile_2 : 32'h0) + | (_wdata_6_value_3_T ? regfile_3 : 32'h0) | (_wdata_6_value_4_T ? regfile_4 : 32'h0) + | (_wdata_6_value_5_T ? regfile_5 : 32'h0) | (_wdata_6_value_6_T ? regfile_6 : 32'h0) + | (_wdata_6_value_7_T ? regfile_7 : 32'h0) | (_wdata_6_value_8_T ? regfile_8 : 32'h0) + | (_wdata_6_value_9_T ? regfile_9 : 32'h0) + | (_wdata_6_value_10_T ? regfile_10 : 32'h0) + | (_wdata_6_value_11_T ? regfile_11 : 32'h0) + | (_wdata_6_value_12_T ? regfile_12 : 32'h0) + | (_wdata_6_value_13_T ? regfile_13 : 32'h0) + | (_wdata_6_value_14_T ? regfile_14 : 32'h0) + | (_wdata_6_value_15_T ? regfile_15 : 32'h0) + | (_wdata_6_value_16_T ? regfile_16 : 32'h0) + | (_wdata_6_value_17_T ? regfile_17 : 32'h0) + | (_wdata_6_value_18_T ? regfile_18 : 32'h0) + | (_wdata_6_value_19_T ? regfile_19 : 32'h0) + | (_wdata_6_value_20_T ? regfile_20 : 32'h0) + | (_wdata_6_value_21_T ? regfile_21 : 32'h0) + | (_wdata_6_value_22_T ? regfile_22 : 32'h0) + | (_wdata_6_value_23_T ? regfile_23 : 32'h0) + | (_wdata_6_value_24_T ? regfile_24 : 32'h0) + | (_wdata_6_value_25_T ? regfile_25 : 32'h0) + | (_wdata_6_value_26_T ? regfile_26 : 32'h0) + | (_wdata_6_value_27_T ? regfile_27 : 32'h0) + | (_wdata_6_value_28_T ? regfile_28 : 32'h0) + | (_wdata_6_value_29_T ? regfile_29 : 32'h0) + | (_wdata_6_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_6_addr) ? regfile_31 : 32'h0); + wire [31:0] rwdata_6 = + io_readAddr_6_addr == 5'h0 | _wdata_6_value_1_T & (|_writeValid_1_T) + | _wdata_6_value_2_T & (|_writeValid_2_T) | _wdata_6_value_3_T & (|_writeValid_3_T) + | _wdata_6_value_4_T & (|_writeValid_4_T) | _wdata_6_value_5_T & (|_writeValid_5_T) + | _wdata_6_value_6_T & (|_writeValid_6_T) | _wdata_6_value_7_T & (|_writeValid_7_T) + | _wdata_6_value_8_T & (|_writeValid_8_T) | _wdata_6_value_9_T & (|_writeValid_9_T) + | _wdata_6_value_10_T & (|_writeValid_10_T) | _wdata_6_value_11_T + & (|_writeValid_11_T) | _wdata_6_value_12_T & (|_writeValid_12_T) + | _wdata_6_value_13_T & (|_writeValid_13_T) | _wdata_6_value_14_T + & (|_writeValid_14_T) | _wdata_6_value_15_T & (|_writeValid_15_T) + | _wdata_6_value_16_T & (|_writeValid_16_T) | _wdata_6_value_17_T + & (|_writeValid_17_T) | _wdata_6_value_18_T & (|_writeValid_18_T) + | _wdata_6_value_19_T & (|_writeValid_19_T) | _wdata_6_value_20_T + & (|_writeValid_20_T) | _wdata_6_value_21_T & (|_writeValid_21_T) + | _wdata_6_value_22_T & (|_writeValid_22_T) | _wdata_6_value_23_T + & (|_writeValid_23_T) | _wdata_6_value_24_T & (|_writeValid_24_T) + | _wdata_6_value_25_T & (|_writeValid_25_T) | _wdata_6_value_26_T + & (|_writeValid_26_T) | _wdata_6_value_27_T & (|_writeValid_27_T) + | _wdata_6_value_28_T & (|_writeValid_28_T) | _wdata_6_value_29_T + & (|_writeValid_29_T) | _wdata_6_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_6_addr) & (|_writeValid_31_T) + ? (_wdata_6_value_1_T ? data : 32'h0) | (_wdata_6_value_2_T ? data_1 : 32'h0) + | (_wdata_6_value_3_T ? data_2 : 32'h0) | (_wdata_6_value_4_T ? data_3 : 32'h0) + | (_wdata_6_value_5_T ? data_4 : 32'h0) | (_wdata_6_value_6_T ? data_5 : 32'h0) + | (_wdata_6_value_7_T ? data_6 : 32'h0) | (_wdata_6_value_8_T ? data_7 : 32'h0) + | (_wdata_6_value_9_T ? data_8 : 32'h0) | (_wdata_6_value_10_T ? data_9 : 32'h0) + | (_wdata_6_value_11_T ? data_10 : 32'h0) + | (_wdata_6_value_12_T ? data_11 : 32'h0) + | (_wdata_6_value_13_T ? data_12 : 32'h0) + | (_wdata_6_value_14_T ? data_13 : 32'h0) + | (_wdata_6_value_15_T ? data_14 : 32'h0) + | (_wdata_6_value_16_T ? data_15 : 32'h0) + | (_wdata_6_value_17_T ? data_16 : 32'h0) + | (_wdata_6_value_18_T ? data_17 : 32'h0) + | (_wdata_6_value_19_T ? data_18 : 32'h0) + | (_wdata_6_value_20_T ? data_19 : 32'h0) + | (_wdata_6_value_21_T ? data_20 : 32'h0) + | (_wdata_6_value_22_T ? data_21 : 32'h0) + | (_wdata_6_value_23_T ? data_22 : 32'h0) + | (_wdata_6_value_24_T ? data_23 : 32'h0) + | (_wdata_6_value_25_T ? data_24 : 32'h0) + | (_wdata_6_value_26_T ? data_25 : 32'h0) + | (_wdata_6_value_27_T ? data_26 : 32'h0) + | (_wdata_6_value_28_T ? data_27 : 32'h0) + | (_wdata_6_value_29_T ? data_28 : 32'h0) + | (_wdata_6_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_6_addr) ? data_30 : 32'h0) + : rdata_6_value_5_0; + wire _wdata_7_value_1_T = io_readAddr_7_addr == 5'h1; + wire _wdata_7_value_2_T = io_readAddr_7_addr == 5'h2; + wire _wdata_7_value_3_T = io_readAddr_7_addr == 5'h3; + wire _wdata_7_value_4_T = io_readAddr_7_addr == 5'h4; + wire _wdata_7_value_5_T = io_readAddr_7_addr == 5'h5; + wire _wdata_7_value_6_T = io_readAddr_7_addr == 5'h6; + wire _wdata_7_value_7_T = io_readAddr_7_addr == 5'h7; + wire _wdata_7_value_8_T = io_readAddr_7_addr == 5'h8; + wire _wdata_7_value_9_T = io_readAddr_7_addr == 5'h9; + wire _wdata_7_value_10_T = io_readAddr_7_addr == 5'hA; + wire _wdata_7_value_11_T = io_readAddr_7_addr == 5'hB; + wire _wdata_7_value_12_T = io_readAddr_7_addr == 5'hC; + wire _wdata_7_value_13_T = io_readAddr_7_addr == 5'hD; + wire _wdata_7_value_14_T = io_readAddr_7_addr == 5'hE; + wire _wdata_7_value_15_T = io_readAddr_7_addr == 5'hF; + wire _wdata_7_value_16_T = io_readAddr_7_addr == 5'h10; + wire _wdata_7_value_17_T = io_readAddr_7_addr == 5'h11; + wire _wdata_7_value_18_T = io_readAddr_7_addr == 5'h12; + wire _wdata_7_value_19_T = io_readAddr_7_addr == 5'h13; + wire _wdata_7_value_20_T = io_readAddr_7_addr == 5'h14; + wire _wdata_7_value_21_T = io_readAddr_7_addr == 5'h15; + wire _wdata_7_value_22_T = io_readAddr_7_addr == 5'h16; + wire _wdata_7_value_23_T = io_readAddr_7_addr == 5'h17; + wire _wdata_7_value_24_T = io_readAddr_7_addr == 5'h18; + wire _wdata_7_value_25_T = io_readAddr_7_addr == 5'h19; + wire _wdata_7_value_26_T = io_readAddr_7_addr == 5'h1A; + wire _wdata_7_value_27_T = io_readAddr_7_addr == 5'h1B; + wire _wdata_7_value_28_T = io_readAddr_7_addr == 5'h1C; + wire _wdata_7_value_29_T = io_readAddr_7_addr == 5'h1D; + wire _wdata_7_value_30_T = io_readAddr_7_addr == 5'h1E; + wire [31:0] rwdata_7 = + io_readAddr_7_addr == 5'h0 | _wdata_7_value_1_T & (|_writeValid_1_T) + | _wdata_7_value_2_T & (|_writeValid_2_T) | _wdata_7_value_3_T & (|_writeValid_3_T) + | _wdata_7_value_4_T & (|_writeValid_4_T) | _wdata_7_value_5_T & (|_writeValid_5_T) + | _wdata_7_value_6_T & (|_writeValid_6_T) | _wdata_7_value_7_T & (|_writeValid_7_T) + | _wdata_7_value_8_T & (|_writeValid_8_T) | _wdata_7_value_9_T & (|_writeValid_9_T) + | _wdata_7_value_10_T & (|_writeValid_10_T) | _wdata_7_value_11_T + & (|_writeValid_11_T) | _wdata_7_value_12_T & (|_writeValid_12_T) + | _wdata_7_value_13_T & (|_writeValid_13_T) | _wdata_7_value_14_T + & (|_writeValid_14_T) | _wdata_7_value_15_T & (|_writeValid_15_T) + | _wdata_7_value_16_T & (|_writeValid_16_T) | _wdata_7_value_17_T + & (|_writeValid_17_T) | _wdata_7_value_18_T & (|_writeValid_18_T) + | _wdata_7_value_19_T & (|_writeValid_19_T) | _wdata_7_value_20_T + & (|_writeValid_20_T) | _wdata_7_value_21_T & (|_writeValid_21_T) + | _wdata_7_value_22_T & (|_writeValid_22_T) | _wdata_7_value_23_T + & (|_writeValid_23_T) | _wdata_7_value_24_T & (|_writeValid_24_T) + | _wdata_7_value_25_T & (|_writeValid_25_T) | _wdata_7_value_26_T + & (|_writeValid_26_T) | _wdata_7_value_27_T & (|_writeValid_27_T) + | _wdata_7_value_28_T & (|_writeValid_28_T) | _wdata_7_value_29_T + & (|_writeValid_29_T) | _wdata_7_value_30_T & (|_writeValid_30_T) + | (&io_readAddr_7_addr) & (|_writeValid_31_T) + ? (_wdata_7_value_1_T ? data : 32'h0) | (_wdata_7_value_2_T ? data_1 : 32'h0) + | (_wdata_7_value_3_T ? data_2 : 32'h0) | (_wdata_7_value_4_T ? data_3 : 32'h0) + | (_wdata_7_value_5_T ? data_4 : 32'h0) | (_wdata_7_value_6_T ? data_5 : 32'h0) + | (_wdata_7_value_7_T ? data_6 : 32'h0) | (_wdata_7_value_8_T ? data_7 : 32'h0) + | (_wdata_7_value_9_T ? data_8 : 32'h0) | (_wdata_7_value_10_T ? data_9 : 32'h0) + | (_wdata_7_value_11_T ? data_10 : 32'h0) + | (_wdata_7_value_12_T ? data_11 : 32'h0) + | (_wdata_7_value_13_T ? data_12 : 32'h0) + | (_wdata_7_value_14_T ? data_13 : 32'h0) + | (_wdata_7_value_15_T ? data_14 : 32'h0) + | (_wdata_7_value_16_T ? data_15 : 32'h0) + | (_wdata_7_value_17_T ? data_16 : 32'h0) + | (_wdata_7_value_18_T ? data_17 : 32'h0) + | (_wdata_7_value_19_T ? data_18 : 32'h0) + | (_wdata_7_value_20_T ? data_19 : 32'h0) + | (_wdata_7_value_21_T ? data_20 : 32'h0) + | (_wdata_7_value_22_T ? data_21 : 32'h0) + | (_wdata_7_value_23_T ? data_22 : 32'h0) + | (_wdata_7_value_24_T ? data_23 : 32'h0) + | (_wdata_7_value_25_T ? data_24 : 32'h0) + | (_wdata_7_value_26_T ? data_25 : 32'h0) + | (_wdata_7_value_27_T ? data_26 : 32'h0) + | (_wdata_7_value_28_T ? data_27 : 32'h0) + | (_wdata_7_value_29_T ? data_28 : 32'h0) + | (_wdata_7_value_30_T ? data_29 : 32'h0) + | ((&io_readAddr_7_addr) ? data_30 : 32'h0) + : (_wdata_7_value_1_T ? regfile_1 : 32'h0) + | (_wdata_7_value_2_T ? regfile_2 : 32'h0) + | (_wdata_7_value_3_T ? regfile_3 : 32'h0) + | (_wdata_7_value_4_T ? regfile_4 : 32'h0) + | (_wdata_7_value_5_T ? regfile_5 : 32'h0) + | (_wdata_7_value_6_T ? regfile_6 : 32'h0) + | (_wdata_7_value_7_T ? regfile_7 : 32'h0) + | (_wdata_7_value_8_T ? regfile_8 : 32'h0) + | (_wdata_7_value_9_T ? regfile_9 : 32'h0) + | (_wdata_7_value_10_T ? regfile_10 : 32'h0) + | (_wdata_7_value_11_T ? regfile_11 : 32'h0) + | (_wdata_7_value_12_T ? regfile_12 : 32'h0) + | (_wdata_7_value_13_T ? regfile_13 : 32'h0) + | (_wdata_7_value_14_T ? regfile_14 : 32'h0) + | (_wdata_7_value_15_T ? regfile_15 : 32'h0) + | (_wdata_7_value_16_T ? regfile_16 : 32'h0) + | (_wdata_7_value_17_T ? regfile_17 : 32'h0) + | (_wdata_7_value_18_T ? regfile_18 : 32'h0) + | (_wdata_7_value_19_T ? regfile_19 : 32'h0) + | (_wdata_7_value_20_T ? regfile_20 : 32'h0) + | (_wdata_7_value_21_T ? regfile_21 : 32'h0) + | (_wdata_7_value_22_T ? regfile_22 : 32'h0) + | (_wdata_7_value_23_T ? regfile_23 : 32'h0) + | (_wdata_7_value_24_T ? regfile_24 : 32'h0) + | (_wdata_7_value_25_T ? regfile_25 : 32'h0) + | (_wdata_7_value_26_T ? regfile_26 : 32'h0) + | (_wdata_7_value_27_T ? regfile_27 : 32'h0) + | (_wdata_7_value_28_T ? regfile_28 : 32'h0) + | (_wdata_7_value_29_T ? regfile_29 : 32'h0) + | (_wdata_7_value_30_T ? regfile_30 : 32'h0) + | ((&io_readAddr_7_addr) ? regfile_31 : 32'h0); + wire [31:0] busAddr_0 = + io_busAddr_0_bypass + ? rwdata_0 + : io_busAddr_0_immen ? rdata_0_value_5_0 + io_busAddr_0_immed : rdata_0_value_5_0; + wire [31:0] busAddr_1 = + io_busAddr_1_bypass ? rwdata_2 : rdata_2_value_5_0 + io_busAddr_1_immed; + wire [31:0] busAddr_2 = + io_busAddr_2_bypass ? rwdata_4 : rdata_4_value_5_0 + io_busAddr_2_immed; + wire [31:0] busAddr_3 = + io_busAddr_3_bypass ? rwdata_6 : rdata_6_value_5_0 + io_busAddr_3_immed; + reg write_fail; + reg write_fail_1; + reg write_fail_2; + reg write_fail_3; + reg write_fail_4; + reg write_fail_5; + reg write_fail_6; + reg write_fail_7; + reg write_fail_8; + reg write_fail_9; + reg write_fail_10; + reg write_fail_11; + reg write_fail_12; + reg write_fail_13; + reg write_fail_14; + reg scoreboard_error; + wire [31:0] scoreboard_set = + (io_writeAddr_0_valid ? 32'h1 << io_writeAddr_0_addr : 32'h0) + | (io_writeAddr_1_valid ? 32'h1 << io_writeAddr_1_addr : 32'h0) + | (io_writeAddr_2_valid ? 32'h1 << io_writeAddr_2_addr : 32'h0) + | (io_writeAddr_3_valid ? 32'h1 << io_writeAddr_3_addr : 32'h0); + wire [31:0] scoreboard_clr = {scoreboard_clr0, 1'h0}; + always @(posedge clock or posedge reset) begin + if (reset) begin + regfile_1 <= 32'h0; + regfile_2 <= 32'h0; + regfile_3 <= 32'h0; + regfile_4 <= 32'h0; + regfile_5 <= 32'h0; + regfile_6 <= 32'h0; + regfile_7 <= 32'h0; + regfile_8 <= 32'h0; + regfile_9 <= 32'h0; + regfile_10 <= 32'h0; + regfile_11 <= 32'h0; + regfile_12 <= 32'h0; + regfile_13 <= 32'h0; + regfile_14 <= 32'h0; + regfile_15 <= 32'h0; + regfile_16 <= 32'h0; + regfile_17 <= 32'h0; + regfile_18 <= 32'h0; + regfile_19 <= 32'h0; + regfile_20 <= 32'h0; + regfile_21 <= 32'h0; + regfile_22 <= 32'h0; + regfile_23 <= 32'h0; + regfile_24 <= 32'h0; + regfile_25 <= 32'h0; + regfile_26 <= 32'h0; + regfile_27 <= 32'h0; + regfile_28 <= 32'h0; + regfile_29 <= 32'h0; + regfile_30 <= 32'h0; + regfile_31 <= 32'h0; + scoreboard <= 32'h0; + readDataReady_0 <= 1'h0; + readDataReady_1 <= 1'h0; + readDataReady_2 <= 1'h0; + readDataReady_3 <= 1'h0; + readDataReady_4 <= 1'h0; + readDataReady_5 <= 1'h0; + readDataReady_6 <= 1'h0; + readDataReady_7 <= 1'h0; + readDataBits_0 <= 32'h0; + readDataBits_1 <= 32'h0; + readDataBits_2 <= 32'h0; + readDataBits_3 <= 32'h0; + readDataBits_4 <= 32'h0; + readDataBits_5 <= 32'h0; + readDataBits_6 <= 32'h0; + readDataBits_7 <= 32'h0; + write_fail <= 1'h0; + write_fail_1 <= 1'h0; + write_fail_2 <= 1'h0; + write_fail_3 <= 1'h0; + write_fail_4 <= 1'h0; + write_fail_5 <= 1'h0; + write_fail_6 <= 1'h0; + write_fail_7 <= 1'h0; + write_fail_8 <= 1'h0; + write_fail_9 <= 1'h0; + write_fail_10 <= 1'h0; + write_fail_11 <= 1'h0; + write_fail_12 <= 1'h0; + write_fail_13 <= 1'h0; + write_fail_14 <= 1'h0; + scoreboard_error <= 1'h0; + end + else begin + if (|_writeValid_1_T) + regfile_1 <= data; + if (|_writeValid_2_T) + regfile_2 <= data_1; + if (|_writeValid_3_T) + regfile_3 <= data_2; + if (|_writeValid_4_T) + regfile_4 <= data_3; + if (|_writeValid_5_T) + regfile_5 <= data_4; + if (|_writeValid_6_T) + regfile_6 <= data_5; + if (|_writeValid_7_T) + regfile_7 <= data_6; + if (|_writeValid_8_T) + regfile_8 <= data_7; + if (|_writeValid_9_T) + regfile_9 <= data_8; + if (|_writeValid_10_T) + regfile_10 <= data_9; + if (|_writeValid_11_T) + regfile_11 <= data_10; + if (|_writeValid_12_T) + regfile_12 <= data_11; + if (|_writeValid_13_T) + regfile_13 <= data_12; + if (|_writeValid_14_T) + regfile_14 <= data_13; + if (|_writeValid_15_T) + regfile_15 <= data_14; + if (|_writeValid_16_T) + regfile_16 <= data_15; + if (|_writeValid_17_T) + regfile_17 <= data_16; + if (|_writeValid_18_T) + regfile_18 <= data_17; + if (|_writeValid_19_T) + regfile_19 <= data_18; + if (|_writeValid_20_T) + regfile_20 <= data_19; + if (|_writeValid_21_T) + regfile_21 <= data_20; + if (|_writeValid_22_T) + regfile_22 <= data_21; + if (|_writeValid_23_T) + regfile_23 <= data_22; + if (|_writeValid_24_T) + regfile_24 <= data_23; + if (|_writeValid_25_T) + regfile_25 <= data_24; + if (|_writeValid_26_T) + regfile_26 <= data_25; + if (|_writeValid_27_T) + regfile_27 <= data_26; + if (|_writeValid_28_T) + regfile_28 <= data_27; + if (|_writeValid_29_T) + regfile_29 <= data_28; + if (|_writeValid_30_T) + regfile_30 <= data_29; + if (|_writeValid_31_T) + regfile_31 <= data_30; + if (|{scoreboard_set, scoreboard_clr0}) + scoreboard <= {scoreboard[31:1] & ~scoreboard_clr0 | scoreboard_set[31:1], 1'h0}; + readDataReady_0 <= io_readAddr_0_valid | io_readSet_0_valid; + readDataReady_1 <= io_readAddr_1_valid | io_readSet_1_valid; + readDataReady_2 <= io_readAddr_2_valid | io_readSet_2_valid; + readDataReady_3 <= io_readAddr_3_valid | io_readSet_3_valid; + readDataReady_4 <= io_readAddr_4_valid | io_readSet_4_valid; + readDataReady_5 <= io_readAddr_5_valid | io_readSet_5_valid; + readDataReady_6 <= io_readAddr_6_valid | io_readSet_6_valid; + readDataReady_7 <= io_readAddr_7_valid | io_readSet_7_valid; + if (io_readSet_0_valid) + readDataBits_0 <= io_readSet_0_value; + else if (io_readAddr_0_valid) + readDataBits_0 <= rwdata_0; + if (io_readSet_1_valid) + readDataBits_1 <= io_readSet_1_value; + else if (io_readAddr_1_valid) + readDataBits_1 <= rwdata_1; + if (io_readSet_2_valid) + readDataBits_2 <= io_readSet_2_value; + else if (io_readAddr_2_valid) + readDataBits_2 <= rwdata_2; + if (io_readSet_3_valid) + readDataBits_3 <= io_readSet_3_value; + else if (io_readAddr_3_valid) + readDataBits_3 <= rwdata_3; + if (io_readSet_4_valid) + readDataBits_4 <= io_readSet_4_value; + else if (io_readAddr_4_valid) + readDataBits_4 <= rwdata_4; + if (io_readSet_5_valid) + readDataBits_5 <= io_readSet_5_value; + else if (io_readAddr_5_valid) + readDataBits_5 <= rwdata_5; + if (io_readSet_6_valid) + readDataBits_6 <= io_readSet_6_value; + else if (io_readAddr_6_valid) + readDataBits_6 <= rwdata_6; + if (io_readSet_7_valid) + readDataBits_7 <= io_readSet_7_value; + else if (io_readAddr_7_valid) + readDataBits_7 <= rwdata_7; + write_fail <= + io_writeData_0_valid & io_writeData_1_valid + & io_writeData_0_bits_addr == io_writeData_1_bits_addr + & (|io_writeData_0_bits_addr); + write_fail_1 <= + io_writeData_0_valid & io_writeData_2_valid + & io_writeData_0_bits_addr == io_writeData_2_bits_addr + & (|io_writeData_0_bits_addr); + write_fail_2 <= + io_writeData_0_valid & io_writeData_3_valid + & io_writeData_0_bits_addr == io_writeData_3_bits_addr + & (|io_writeData_0_bits_addr); + write_fail_3 <= + io_writeData_0_valid & io_writeData_4_valid + & io_writeData_0_bits_addr == io_writeData_4_bits_addr + & (|io_writeData_0_bits_addr); + write_fail_4 <= + io_writeData_0_valid & io_writeData_5_valid + & io_writeData_0_bits_addr == io_writeData_5_bits_addr + & (|io_writeData_0_bits_addr); + write_fail_5 <= + io_writeData_1_valid & io_writeData_2_valid + & io_writeData_1_bits_addr == io_writeData_2_bits_addr + & (|io_writeData_1_bits_addr); + write_fail_6 <= + io_writeData_1_valid & io_writeData_3_valid + & io_writeData_1_bits_addr == io_writeData_3_bits_addr + & (|io_writeData_1_bits_addr); + write_fail_7 <= + io_writeData_1_valid & io_writeData_4_valid + & io_writeData_1_bits_addr == io_writeData_4_bits_addr + & (|io_writeData_1_bits_addr); + write_fail_8 <= + io_writeData_1_valid & io_writeData_5_valid + & io_writeData_1_bits_addr == io_writeData_5_bits_addr + & (|io_writeData_1_bits_addr); + write_fail_9 <= + io_writeData_2_valid & io_writeData_3_valid + & io_writeData_2_bits_addr == io_writeData_3_bits_addr + & (|io_writeData_2_bits_addr); + write_fail_10 <= + io_writeData_2_valid & io_writeData_4_valid + & io_writeData_2_bits_addr == io_writeData_4_bits_addr + & (|io_writeData_2_bits_addr); + write_fail_11 <= + io_writeData_2_valid & io_writeData_5_valid + & io_writeData_2_bits_addr == io_writeData_5_bits_addr + & (|io_writeData_2_bits_addr); + write_fail_12 <= + io_writeData_3_valid & io_writeData_4_valid + & io_writeData_3_bits_addr == io_writeData_4_bits_addr + & (|io_writeData_3_bits_addr); + write_fail_13 <= + io_writeData_3_valid & io_writeData_5_valid + & io_writeData_3_bits_addr == io_writeData_5_bits_addr + & (|io_writeData_3_bits_addr); + write_fail_14 <= + io_writeData_4_valid & io_writeData_5_valid + & io_writeData_4_bits_addr == io_writeData_5_bits_addr + & (|io_writeData_4_bits_addr); + scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:41]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [5:0] i = 6'h0; i < 6'h2A; i += 6'h1) begin + _RANDOM[i] = `RANDOM; + end + regfile_1 = _RANDOM[6'h1]; + regfile_2 = _RANDOM[6'h2]; + regfile_3 = _RANDOM[6'h3]; + regfile_4 = _RANDOM[6'h4]; + regfile_5 = _RANDOM[6'h5]; + regfile_6 = _RANDOM[6'h6]; + regfile_7 = _RANDOM[6'h7]; + regfile_8 = _RANDOM[6'h8]; + regfile_9 = _RANDOM[6'h9]; + regfile_10 = _RANDOM[6'hA]; + regfile_11 = _RANDOM[6'hB]; + regfile_12 = _RANDOM[6'hC]; + regfile_13 = _RANDOM[6'hD]; + regfile_14 = _RANDOM[6'hE]; + regfile_15 = _RANDOM[6'hF]; + regfile_16 = _RANDOM[6'h10]; + regfile_17 = _RANDOM[6'h11]; + regfile_18 = _RANDOM[6'h12]; + regfile_19 = _RANDOM[6'h13]; + regfile_20 = _RANDOM[6'h14]; + regfile_21 = _RANDOM[6'h15]; + regfile_22 = _RANDOM[6'h16]; + regfile_23 = _RANDOM[6'h17]; + regfile_24 = _RANDOM[6'h18]; + regfile_25 = _RANDOM[6'h19]; + regfile_26 = _RANDOM[6'h1A]; + regfile_27 = _RANDOM[6'h1B]; + regfile_28 = _RANDOM[6'h1C]; + regfile_29 = _RANDOM[6'h1D]; + regfile_30 = _RANDOM[6'h1E]; + regfile_31 = _RANDOM[6'h1F]; + scoreboard = _RANDOM[6'h20]; + readDataReady_0 = _RANDOM[6'h21][0]; + readDataReady_1 = _RANDOM[6'h21][1]; + readDataReady_2 = _RANDOM[6'h21][2]; + readDataReady_3 = _RANDOM[6'h21][3]; + readDataReady_4 = _RANDOM[6'h21][4]; + readDataReady_5 = _RANDOM[6'h21][5]; + readDataReady_6 = _RANDOM[6'h21][6]; + readDataReady_7 = _RANDOM[6'h21][7]; + readDataBits_0 = {_RANDOM[6'h21][31:8], _RANDOM[6'h22][7:0]}; + readDataBits_1 = {_RANDOM[6'h22][31:8], _RANDOM[6'h23][7:0]}; + readDataBits_2 = {_RANDOM[6'h23][31:8], _RANDOM[6'h24][7:0]}; + readDataBits_3 = {_RANDOM[6'h24][31:8], _RANDOM[6'h25][7:0]}; + readDataBits_4 = {_RANDOM[6'h25][31:8], _RANDOM[6'h26][7:0]}; + readDataBits_5 = {_RANDOM[6'h26][31:8], _RANDOM[6'h27][7:0]}; + readDataBits_6 = {_RANDOM[6'h27][31:8], _RANDOM[6'h28][7:0]}; + readDataBits_7 = {_RANDOM[6'h28][31:8], _RANDOM[6'h29][7:0]}; + write_fail = _RANDOM[6'h29][8]; + write_fail_1 = _RANDOM[6'h29][9]; + write_fail_2 = _RANDOM[6'h29][10]; + write_fail_3 = _RANDOM[6'h29][11]; + write_fail_4 = _RANDOM[6'h29][12]; + write_fail_5 = _RANDOM[6'h29][13]; + write_fail_6 = _RANDOM[6'h29][14]; + write_fail_7 = _RANDOM[6'h29][15]; + write_fail_8 = _RANDOM[6'h29][16]; + write_fail_9 = _RANDOM[6'h29][17]; + write_fail_10 = _RANDOM[6'h29][18]; + write_fail_11 = _RANDOM[6'h29][19]; + write_fail_12 = _RANDOM[6'h29][20]; + write_fail_13 = _RANDOM[6'h29][21]; + write_fail_14 = _RANDOM[6'h29][22]; + scoreboard_error = _RANDOM[6'h29][23]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + regfile_1 = 32'h0; + regfile_2 = 32'h0; + regfile_3 = 32'h0; + regfile_4 = 32'h0; + regfile_5 = 32'h0; + regfile_6 = 32'h0; + regfile_7 = 32'h0; + regfile_8 = 32'h0; + regfile_9 = 32'h0; + regfile_10 = 32'h0; + regfile_11 = 32'h0; + regfile_12 = 32'h0; + regfile_13 = 32'h0; + regfile_14 = 32'h0; + regfile_15 = 32'h0; + regfile_16 = 32'h0; + regfile_17 = 32'h0; + regfile_18 = 32'h0; + regfile_19 = 32'h0; + regfile_20 = 32'h0; + regfile_21 = 32'h0; + regfile_22 = 32'h0; + regfile_23 = 32'h0; + regfile_24 = 32'h0; + regfile_25 = 32'h0; + regfile_26 = 32'h0; + regfile_27 = 32'h0; + regfile_28 = 32'h0; + regfile_29 = 32'h0; + regfile_30 = 32'h0; + regfile_31 = 32'h0; + scoreboard = 32'h0; + readDataReady_0 = 1'h0; + readDataReady_1 = 1'h0; + readDataReady_2 = 1'h0; + readDataReady_3 = 1'h0; + readDataReady_4 = 1'h0; + readDataReady_5 = 1'h0; + readDataReady_6 = 1'h0; + readDataReady_7 = 1'h0; + readDataBits_0 = 32'h0; + readDataBits_1 = 32'h0; + readDataBits_2 = 32'h0; + readDataBits_3 = 32'h0; + readDataBits_4 = 32'h0; + readDataBits_5 = 32'h0; + readDataBits_6 = 32'h0; + readDataBits_7 = 32'h0; + write_fail = 1'h0; + write_fail_1 = 1'h0; + write_fail_2 = 1'h0; + write_fail_3 = 1'h0; + write_fail_4 = 1'h0; + write_fail_5 = 1'h0; + write_fail_6 = 1'h0; + write_fail_7 = 1'h0; + write_fail_8 = 1'h0; + write_fail_9 = 1'h0; + write_fail_10 = 1'h0; + write_fail_11 = 1'h0; + write_fail_12 = 1'h0; + write_fail_13 = 1'h0; + write_fail_14 = 1'h0; + scoreboard_error = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_target_0_data = busAddr_0; + assign io_target_1_data = busAddr_1; + assign io_target_2_data = busAddr_2; + assign io_target_3_data = busAddr_3; + assign io_busPort_addr_0 = busAddr_0; + assign io_busPort_addr_1 = busAddr_1; + assign io_busPort_addr_2 = busAddr_2; + assign io_busPort_addr_3 = busAddr_3; + assign io_busPort_data_0 = io_readSet_1_valid ? io_readSet_1_value : rwdata_1; + assign io_busPort_data_1 = io_readSet_3_valid ? io_readSet_3_value : rwdata_3; + assign io_busPort_data_2 = io_readSet_5_valid ? io_readSet_5_value : rwdata_5; + assign io_busPort_data_3 = io_readSet_7_valid ? io_readSet_7_value : rwdata_7; + assign io_readData_0_valid = readDataReady_0; + assign io_readData_0_data = readDataBits_0; + assign io_readData_1_valid = readDataReady_1; + assign io_readData_1_data = readDataBits_1; + assign io_readData_2_valid = readDataReady_2; + assign io_readData_2_data = readDataBits_2; + assign io_readData_3_valid = readDataReady_3; + assign io_readData_3_data = readDataBits_3; + assign io_readData_4_valid = readDataReady_4; + assign io_readData_4_data = readDataBits_4; + assign io_readData_5_valid = readDataReady_5; + assign io_readData_5_data = readDataBits_5; + assign io_readData_6_valid = readDataReady_6; + assign io_readData_6_data = readDataBits_6; + assign io_readData_7_valid = readDataReady_7; + assign io_readData_7_data = readDataBits_7; + assign io_scoreboard_regd = scoreboard; + assign io_scoreboard_comb = scoreboard & {~scoreboard_clr0, 1'h1}; + assign io_rfwriteCount = + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, |_writeValid_1_T} + 2'h1} + + {1'h0, {1'h0, |_writeValid_2_T} + {1'h0, |_writeValid_3_T}}} + + {1'h0, + {1'h0, {1'h0, |_writeValid_4_T} + {1'h0, |_writeValid_5_T}} + + {1'h0, {1'h0, |_writeValid_6_T} + {1'h0, |_writeValid_7_T}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, |_writeValid_8_T} + {1'h0, |_writeValid_9_T}} + + {1'h0, {1'h0, |_writeValid_10_T} + {1'h0, |_writeValid_11_T}}} + + {1'h0, + {1'h0, {1'h0, |_writeValid_12_T} + {1'h0, |_writeValid_13_T}} + + {1'h0, {1'h0, |_writeValid_14_T} + {1'h0, |_writeValid_15_T}}}}} + + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, |_writeValid_16_T} + {1'h0, |_writeValid_17_T}} + + {1'h0, {1'h0, |_writeValid_18_T} + {1'h0, |_writeValid_19_T}}} + + {1'h0, + {1'h0, {1'h0, |_writeValid_20_T} + {1'h0, |_writeValid_21_T}} + + {1'h0, {1'h0, |_writeValid_22_T} + {1'h0, |_writeValid_23_T}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, |_writeValid_24_T} + {1'h0, |_writeValid_25_T}} + + {1'h0, {1'h0, |_writeValid_26_T} + {1'h0, |_writeValid_27_T}}} + + {1'h0, + {1'h0, {1'h0, |_writeValid_28_T} + {1'h0, |_writeValid_29_T}} + + {1'h0, {1'h0, |_writeValid_30_T} + {1'h0, |_writeValid_31_T}}}}} + + {3'h0, + {1'h0, + {1'h0, io_writeData_0_valid & io_writeData_0_bits_addr == 5'h0} + + {1'h0, + io_writeData_1_valid & io_writeData_1_bits_addr == 5'h0 + & ~io_writeMask_1_valid}} + + {1'h0, + {1'h0, + io_writeData_2_valid & io_writeData_2_bits_addr == 5'h0 + & ~io_writeMask_2_valid} + + {1'h0, + io_writeData_3_valid & io_writeData_3_bits_addr == 5'h0 + & ~io_writeMask_3_valid}}} - 6'h1; +endmodule + +module FetchControl( + input clock, + reset, + input [31:0] io_csr_value_0, + input io_iflush_valid, + input [31:0] io_iflush_bits, + input io_branch_valid, + input [31:0] io_branch_bits, + input io_fetchData_valid, + input [31:0] io_fetchData_bits_addr, + io_fetchData_bits_inst_0, + io_fetchData_bits_inst_1, + io_fetchData_bits_inst_2, + io_fetchData_bits_inst_3, + output io_fetchAddr_valid, + output [31:0] io_fetchAddr_bits, + output [2:0] io_bufferRequest_nValid, + output [31:0] io_bufferRequest_bits_0_addr, + io_bufferRequest_bits_0_inst, + output io_bufferRequest_bits_0_brchFwd, + output [31:0] io_bufferRequest_bits_1_addr, + io_bufferRequest_bits_1_inst, + output io_bufferRequest_bits_1_brchFwd, + output [31:0] io_bufferRequest_bits_2_addr, + io_bufferRequest_bits_2_inst, + output io_bufferRequest_bits_2_brchFwd, + output [31:0] io_bufferRequest_bits_3_addr, + io_bufferRequest_bits_3_inst, + output io_bufferRequest_bits_3_brchFwd, + input [3:0] io_bufferSpaces +); + + wire [31:0] _GEN = {io_fetchData_bits_addr[31:4], 4'h0}; + wire jumped_3 = + io_fetchData_bits_inst_3[6:0] == 7'h6F | io_fetchData_bits_inst_3[6:0] == 7'h63 + & io_fetchData_bits_inst_3[31] & io_fetchData_bits_inst_3[14:13] != 2'h1; + wire jumped_0 = + io_fetchData_bits_addr[3:2] == 2'h0 + & (io_fetchData_bits_inst_0[6:0] == 7'h6F | io_fetchData_bits_inst_0[6:0] == 7'h63 + & io_fetchData_bits_inst_0[31] & io_fetchData_bits_inst_0[14:13] != 2'h1); + wire jumped_1 = + ~(io_fetchData_bits_addr[3]) + & (io_fetchData_bits_inst_1[6:0] == 7'h6F | io_fetchData_bits_inst_1[6:0] == 7'h63 + & io_fetchData_bits_inst_1[31] & io_fetchData_bits_inst_1[14:13] != 2'h1); + wire jumped_2 = + io_fetchData_bits_addr[3:2] != 2'h3 + & (io_fetchData_bits_inst_2[6:0] == 7'h6F | io_fetchData_bits_inst_2[6:0] == 7'h63 + & io_fetchData_bits_inst_2[31] & io_fetchData_bits_inst_2[14:13] != 2'h1); + wire [2:0] lastInstIdx = + jumped_0 ? 3'h0 : jumped_1 ? 3'h1 : jumped_2 ? 3'h2 : jumped_3 ? 3'h3 : 3'h4; + wire [31:0] nextFetchPc = + jumped_0 + ? _GEN + + {{12{io_fetchData_bits_inst_0[31]}}, + io_fetchData_bits_inst_0[2] + ? {io_fetchData_bits_inst_0[19:12], + io_fetchData_bits_inst_0[20], + io_fetchData_bits_inst_0[30:21]} + : {{8{io_fetchData_bits_inst_0[31]}}, + io_fetchData_bits_inst_0[7], + io_fetchData_bits_inst_0[30:25], + io_fetchData_bits_inst_0[11:8]}, + 1'h0} + : jumped_1 + ? {io_fetchData_bits_addr[31:4], 4'h4} + + {{12{io_fetchData_bits_inst_1[31]}}, + io_fetchData_bits_inst_1[2] + ? {io_fetchData_bits_inst_1[19:12], + io_fetchData_bits_inst_1[20], + io_fetchData_bits_inst_1[30:21]} + : {{8{io_fetchData_bits_inst_1[31]}}, + io_fetchData_bits_inst_1[7], + io_fetchData_bits_inst_1[30:25], + io_fetchData_bits_inst_1[11:8]}, + 1'h0} + : jumped_2 + ? {io_fetchData_bits_addr[31:4], 4'h8} + + {{12{io_fetchData_bits_inst_2[31]}}, + io_fetchData_bits_inst_2[2] + ? {io_fetchData_bits_inst_2[19:12], + io_fetchData_bits_inst_2[20], + io_fetchData_bits_inst_2[30:21]} + : {{8{io_fetchData_bits_inst_2[31]}}, + io_fetchData_bits_inst_2[7], + io_fetchData_bits_inst_2[30:25], + io_fetchData_bits_inst_2[11:8]}, + 1'h0} + : jumped_3 + ? {io_fetchData_bits_addr[31:4], 4'hC} + + {{12{io_fetchData_bits_inst_3[31]}}, + io_fetchData_bits_inst_3[2] + ? {io_fetchData_bits_inst_3[19:12], + io_fetchData_bits_inst_3[20], + io_fetchData_bits_inst_3[30:21]} + : {{8{io_fetchData_bits_inst_3[31]}}, + io_fetchData_bits_inst_3[7], + io_fetchData_bits_inst_3[30:25], + io_fetchData_bits_inst_3[11:8]}, + 1'h0} + : {io_fetchData_bits_addr[31:4] + 28'h1, 4'h0}; + wire [2:0] predecode_startIdx = {1'h0, io_fetchData_bits_addr[3:2]}; + wire [2:0] _GEN_0 = {1'h0, io_fetchData_bits_addr[3:2]}; + wire [2:0] _result_count_T_7 = + lastInstIdx == 3'h4 ? lastInstIdx - _GEN_0 : lastInstIdx + 3'h1 - _GEN_0; + wire [4:0] _predecodeValids_T_10 = + {3'h0, io_fetchData_bits_addr[3:2]} + {2'h0, _result_count_T_7}; + wire selectHot_0 = + io_fetchData_bits_addr[3:2] == 2'h0 & (|_predecodeValids_T_10); + wire predecodeValids_1 = + predecode_startIdx < 3'h2 & (|(_predecodeValids_T_10[4:1])); + wire predecodeValids_2 = + predecode_startIdx < 3'h3 & _predecodeValids_T_10 > 5'h2; + wire selectHot_seenValid_2 = selectHot_0 | predecodeValids_1; + wire selectHot_1 = predecodeValids_1 & ~selectHot_0; + wire selectHot_2 = predecodeValids_2 & ~selectHot_seenValid_2; + wire selectHot_3 = + (|(_predecodeValids_T_10[4:2])) & ~(selectHot_seenValid_2 | predecodeValids_2); + wire [31:0] _io_bufferRequest_bits_3_addr_T_2 = _GEN + 32'h4; + wire [31:0] _io_bufferRequest_bits_3_addr_T_4 = _GEN + 32'h8; + wire [31:0] _io_bufferRequest_bits_3_addr_T_6 = _GEN + 32'hC; + wire selectHot_1_1 = predecodeValids_1 & ~selectHot_1; + wire _GEN_1 = predecodeValids_2 & ~selectHot_2; + wire _GEN_2 = (|(_predecodeValids_T_10[4:2])) & ~selectHot_3; + wire selectHot_1_2 = _GEN_1 & ~selectHot_1_1; + wire selectHot_1_3 = _GEN_2 & ~(selectHot_1_1 | _GEN_1); + wire selectHot_2_2 = _GEN_1 & ~selectHot_1_2; + wire _GEN_3 = _GEN_2 & ~selectHot_1_3; + wire selectHot_2_3 = _GEN_3 & ~selectHot_2_2; + wire selectHot_3_3 = _GEN_3 & ~selectHot_2_3; + reg pastBranchOrFlush; + wire currentBranchOrFlush = io_iflush_valid | io_branch_valid; + wire ongoingBranchOrFlush = pastBranchOrFlush | currentBranchOrFlush; + wire writeToBuffer = io_fetchData_valid & ~ongoingBranchOrFlush; + wire [3:0] nValid = writeToBuffer ? {1'h0, _result_count_T_7} : 4'h0; + reg pc_valid; + reg [31:0] pc_bits; + wire [31:0] _pcNext_T_2 = {io_csr_value_0[31:2], 2'h0}; + wire blockNewFetch = + ~pc_valid | currentBranchOrFlush | {1'h0, io_bufferSpaces} < {1'h0, nValid} + 5'h4; + always @(posedge clock or posedge reset) begin + if (reset) begin + pastBranchOrFlush <= 1'h0; + pc_valid <= 1'h0; + pc_bits <= 32'h0; + end + else begin + pastBranchOrFlush <= ongoingBranchOrFlush & blockNewFetch; + pc_valid <= 1'h1; + if (pc_valid) begin + if (io_iflush_valid) + pc_bits <= io_iflush_bits; + else if (io_branch_valid) + pc_bits <= io_branch_bits; + else if (writeToBuffer) + pc_bits <= nextFetchPc; + end + else + pc_bits <= _pcNext_T_2; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + pastBranchOrFlush = _RANDOM[1'h0][0]; + pc_valid = _RANDOM[1'h0][1]; + pc_bits = {_RANDOM[1'h0][31:2], _RANDOM[1'h1][1:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + pastBranchOrFlush = 1'h0; + pc_valid = 1'h0; + pc_bits = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_fetchAddr_valid = ~blockNewFetch; + assign io_fetchAddr_bits = + blockNewFetch + ? 32'h0 + : pc_valid + ? (io_iflush_valid + ? io_iflush_bits + : io_branch_valid ? io_branch_bits : writeToBuffer ? nextFetchPc : pc_bits) + : _pcNext_T_2; + assign io_bufferRequest_nValid = nValid[2:0]; + assign io_bufferRequest_bits_0_addr = + selectHot_0 + ? {io_fetchData_bits_addr[31:4], 4'h0} + : selectHot_1 + ? _io_bufferRequest_bits_3_addr_T_2 + : selectHot_2 + ? _io_bufferRequest_bits_3_addr_T_4 + : selectHot_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; + assign io_bufferRequest_bits_0_inst = + selectHot_0 + ? io_fetchData_bits_inst_0 + : selectHot_1 + ? io_fetchData_bits_inst_1 + : selectHot_2 + ? io_fetchData_bits_inst_2 + : selectHot_3 ? io_fetchData_bits_inst_3 : 32'h0; + assign io_bufferRequest_bits_0_brchFwd = + selectHot_0 + ? jumped_0 + : selectHot_1 ? jumped_1 : selectHot_2 ? jumped_2 : selectHot_3 & jumped_3; + assign io_bufferRequest_bits_1_addr = + selectHot_1_1 + ? _io_bufferRequest_bits_3_addr_T_2 + : selectHot_1_2 + ? _io_bufferRequest_bits_3_addr_T_4 + : selectHot_1_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; + assign io_bufferRequest_bits_1_inst = + selectHot_1_1 + ? io_fetchData_bits_inst_1 + : selectHot_1_2 + ? io_fetchData_bits_inst_2 + : selectHot_1_3 ? io_fetchData_bits_inst_3 : 32'h0; + assign io_bufferRequest_bits_1_brchFwd = + selectHot_1_1 ? jumped_1 : selectHot_1_2 ? jumped_2 : selectHot_1_3 & jumped_3; + assign io_bufferRequest_bits_2_addr = + selectHot_2_2 + ? _io_bufferRequest_bits_3_addr_T_4 + : selectHot_2_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; + assign io_bufferRequest_bits_2_inst = + selectHot_2_2 + ? io_fetchData_bits_inst_2 + : selectHot_2_3 ? io_fetchData_bits_inst_3 : 32'h0; + assign io_bufferRequest_bits_2_brchFwd = + selectHot_2_2 ? jumped_2 : selectHot_2_3 & jumped_3; + assign io_bufferRequest_bits_3_addr = + selectHot_3_3 ? _io_bufferRequest_bits_3_addr_T_6 : 32'h0; + assign io_bufferRequest_bits_3_inst = selectHot_3_3 ? io_fetchData_bits_inst_3 : 32'h0; + assign io_bufferRequest_bits_3_brchFwd = selectHot_3_3 & jumped_3; +endmodule + +module Fetcher( + input clock, + reset, + io_ctrl_valid, + input [31:0] io_ctrl_bits, + output io_fetch_valid, + output [31:0] io_fetch_bits_addr, + io_fetch_bits_inst_0, + io_fetch_bits_inst_1, + io_fetch_bits_inst_2, + io_fetch_bits_inst_3, + output io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata +); + + reg ibusCmd_valid; + reg [31:0] ibusCmd_bits; + wire ibusFired = io_ctrl_valid & io_ibus_ready; + always @(posedge clock or posedge reset) begin + if (reset) begin + ibusCmd_valid <= 1'h0; + ibusCmd_bits <= 32'h0; + end + else begin + ibusCmd_valid <= ibusFired; + ibusCmd_bits <= ibusFired ? io_ctrl_bits : 32'h0; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + ibusCmd_valid = _RANDOM[1'h0][0]; + ibusCmd_bits = {_RANDOM[1'h0][31:1], _RANDOM[1'h1][0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ibusCmd_valid = 1'h0; + ibusCmd_bits = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_fetch_valid = ibusCmd_valid; + assign io_fetch_bits_addr = ibusCmd_bits; + assign io_fetch_bits_inst_0 = io_ibus_rdata[31:0]; + assign io_fetch_bits_inst_1 = io_ibus_rdata[63:32]; + assign io_fetch_bits_inst_2 = io_ibus_rdata[95:64]; + assign io_fetch_bits_inst_3 = io_ibus_rdata[127:96]; + assign io_ibus_valid = io_ctrl_valid; + assign io_ibus_addr = {io_ctrl_bits[31:4], 4'h0}; +endmodule + +module CircularBufferMulti( + input clock, + reset, + input [2:0] io_enqValid, + input [31:0] io_enqData_0_addr, + io_enqData_0_inst, + input io_enqData_0_brchFwd, + input [31:0] io_enqData_1_addr, + io_enqData_1_inst, + input io_enqData_1_brchFwd, + input [31:0] io_enqData_2_addr, + io_enqData_2_inst, + input io_enqData_2_brchFwd, + input [31:0] io_enqData_3_addr, + io_enqData_3_inst, + input io_enqData_3_brchFwd, + output [3:0] io_nEnqueued, + io_nSpace, + output [31:0] io_dataOut_0_addr, + io_dataOut_0_inst, + output io_dataOut_0_brchFwd, + output [31:0] io_dataOut_1_addr, + io_dataOut_1_inst, + output io_dataOut_1_brchFwd, + output [31:0] io_dataOut_2_addr, + io_dataOut_2_inst, + output io_dataOut_2_brchFwd, + output [31:0] io_dataOut_3_addr, + io_dataOut_3_inst, + output io_dataOut_3_brchFwd, + input [2:0] io_deqReady, + input io_flush +); + + reg [31:0] buffer_0_addr; + reg [31:0] buffer_0_inst; + reg buffer_0_brchFwd; + reg [31:0] buffer_1_addr; + reg [31:0] buffer_1_inst; + reg buffer_1_brchFwd; + reg [31:0] buffer_2_addr; + reg [31:0] buffer_2_inst; + reg buffer_2_brchFwd; + reg [31:0] buffer_3_addr; + reg [31:0] buffer_3_inst; + reg buffer_3_brchFwd; + reg [31:0] buffer_4_addr; + reg [31:0] buffer_4_inst; + reg buffer_4_brchFwd; + reg [31:0] buffer_5_addr; + reg [31:0] buffer_5_inst; + reg buffer_5_brchFwd; + reg [31:0] buffer_6_addr; + reg [31:0] buffer_6_inst; + reg buffer_6_brchFwd; + reg [31:0] buffer_7_addr; + reg [31:0] buffer_7_inst; + reg buffer_7_brchFwd; + reg [2:0] enqPtr; + reg [2:0] deqPtr; + reg [3:0] nEnqueued; + wire [9:0] _outputBufferView_rotated_T_9 = {7'h0, deqPtr} * 10'h41; + wire [519:0] _outputBufferView_rotated_T_23 = + _outputBufferView_rotated_T_9[0] + ? {buffer_0_brchFwd, + buffer_7_addr, + buffer_7_inst, + buffer_7_brchFwd, + buffer_6_addr, + buffer_6_inst, + buffer_6_brchFwd, + buffer_5_addr, + buffer_5_inst, + buffer_5_brchFwd, + buffer_4_addr, + buffer_4_inst, + buffer_4_brchFwd, + buffer_3_addr, + buffer_3_inst, + buffer_3_brchFwd, + buffer_2_addr, + buffer_2_inst, + buffer_2_brchFwd, + buffer_1_addr, + buffer_1_inst, + buffer_1_brchFwd, + buffer_0_addr, + buffer_0_inst} + : {buffer_7_addr, + buffer_7_inst, + buffer_7_brchFwd, + buffer_6_addr, + buffer_6_inst, + buffer_6_brchFwd, + buffer_5_addr, + buffer_5_inst, + buffer_5_brchFwd, + buffer_4_addr, + buffer_4_inst, + buffer_4_brchFwd, + buffer_3_addr, + buffer_3_inst, + buffer_3_brchFwd, + buffer_2_addr, + buffer_2_inst, + buffer_2_brchFwd, + buffer_1_addr, + buffer_1_inst, + buffer_1_brchFwd, + buffer_0_addr, + buffer_0_inst, + buffer_0_brchFwd}; + wire [519:0] _outputBufferView_rotated_T_27 = + _outputBufferView_rotated_T_9[1] + ? {_outputBufferView_rotated_T_23[1:0], _outputBufferView_rotated_T_23[519:2]} + : _outputBufferView_rotated_T_23; + wire [519:0] _outputBufferView_rotated_T_31 = + _outputBufferView_rotated_T_9[2] + ? {_outputBufferView_rotated_T_27[3:0], _outputBufferView_rotated_T_27[519:4]} + : _outputBufferView_rotated_T_27; + wire [519:0] _outputBufferView_rotated_T_35 = + _outputBufferView_rotated_T_9[3] + ? {_outputBufferView_rotated_T_31[7:0], _outputBufferView_rotated_T_31[519:8]} + : _outputBufferView_rotated_T_31; + wire [519:0] _outputBufferView_rotated_T_39 = + _outputBufferView_rotated_T_9[4] + ? {_outputBufferView_rotated_T_35[15:0], _outputBufferView_rotated_T_35[519:16]} + : _outputBufferView_rotated_T_35; + wire [519:0] _outputBufferView_rotated_T_43 = + _outputBufferView_rotated_T_9[5] + ? {_outputBufferView_rotated_T_39[31:0], _outputBufferView_rotated_T_39[519:32]} + : _outputBufferView_rotated_T_39; + wire [519:0] _outputBufferView_rotated_T_47 = + _outputBufferView_rotated_T_9[6] + ? {_outputBufferView_rotated_T_43[63:0], _outputBufferView_rotated_T_43[519:64]} + : _outputBufferView_rotated_T_43; + wire [519:0] _outputBufferView_rotated_T_51 = + _outputBufferView_rotated_T_9[7] + ? {_outputBufferView_rotated_T_47[127:0], _outputBufferView_rotated_T_47[519:128]} + : _outputBufferView_rotated_T_47; + wire [519:0] _outputBufferView_rotated_T_55 = + _outputBufferView_rotated_T_9[8] + ? {_outputBufferView_rotated_T_51[255:0], _outputBufferView_rotated_T_51[519:256]} + : _outputBufferView_rotated_T_51; + wire [259:0] outputBufferView_rotated = + _outputBufferView_rotated_T_9[9] + ? {_outputBufferView_rotated_T_55[251:0], _outputBufferView_rotated_T_55[519:512]} + : _outputBufferView_rotated_T_55[259:0]; + wire expandedInput_2_ret_valid = io_enqValid > 3'h2; + wire [9:0] _rotatedInput_rotated_T_17 = {7'h0, enqPtr} * 10'h42; + wire [527:0] _rotatedInput_rotated_T_31 = + _rotatedInput_rotated_T_17[0] + ? {263'h0, + io_enqValid[2], + io_enqData_3_addr, + io_enqData_3_inst, + io_enqData_3_brchFwd, + expandedInput_2_ret_valid, + io_enqData_2_addr, + io_enqData_2_inst, + io_enqData_2_brchFwd, + |(io_enqValid[2:1]), + io_enqData_1_addr, + io_enqData_1_inst, + io_enqData_1_brchFwd, + |io_enqValid, + io_enqData_0_addr, + io_enqData_0_inst, + io_enqData_0_brchFwd, + 1'h0} + : {264'h0, + io_enqValid[2], + io_enqData_3_addr, + io_enqData_3_inst, + io_enqData_3_brchFwd, + expandedInput_2_ret_valid, + io_enqData_2_addr, + io_enqData_2_inst, + io_enqData_2_brchFwd, + |(io_enqValid[2:1]), + io_enqData_1_addr, + io_enqData_1_inst, + io_enqData_1_brchFwd, + |io_enqValid, + io_enqData_0_addr, + io_enqData_0_inst, + io_enqData_0_brchFwd}; + wire [527:0] _rotatedInput_rotated_T_35 = + _rotatedInput_rotated_T_17[1] + ? {_rotatedInput_rotated_T_31[525:0], _rotatedInput_rotated_T_31[527:526]} + : _rotatedInput_rotated_T_31; + wire [527:0] _rotatedInput_rotated_T_39 = + _rotatedInput_rotated_T_17[2] + ? {_rotatedInput_rotated_T_35[523:0], _rotatedInput_rotated_T_35[527:524]} + : _rotatedInput_rotated_T_35; + wire [527:0] _rotatedInput_rotated_T_43 = + _rotatedInput_rotated_T_17[3] + ? {_rotatedInput_rotated_T_39[519:0], _rotatedInput_rotated_T_39[527:520]} + : _rotatedInput_rotated_T_39; + wire [527:0] _rotatedInput_rotated_T_47 = + _rotatedInput_rotated_T_17[4] + ? {_rotatedInput_rotated_T_43[511:0], _rotatedInput_rotated_T_43[527:512]} + : _rotatedInput_rotated_T_43; + wire [527:0] _rotatedInput_rotated_T_51 = + _rotatedInput_rotated_T_17[5] + ? {_rotatedInput_rotated_T_47[495:0], _rotatedInput_rotated_T_47[527:496]} + : _rotatedInput_rotated_T_47; + wire [527:0] _rotatedInput_rotated_T_55 = + _rotatedInput_rotated_T_17[6] + ? {_rotatedInput_rotated_T_51[463:0], _rotatedInput_rotated_T_51[527:464]} + : _rotatedInput_rotated_T_51; + wire [527:0] _rotatedInput_rotated_T_59 = + _rotatedInput_rotated_T_17[7] + ? {_rotatedInput_rotated_T_55[399:0], _rotatedInput_rotated_T_55[527:400]} + : _rotatedInput_rotated_T_55; + wire [527:0] _rotatedInput_rotated_T_63 = + _rotatedInput_rotated_T_17[8] + ? {_rotatedInput_rotated_T_59[271:0], _rotatedInput_rotated_T_59[527:272]} + : _rotatedInput_rotated_T_59; + wire [527:0] rotatedInput_rotated = + _rotatedInput_rotated_T_17[9] + ? {_rotatedInput_rotated_T_63[15:0], _rotatedInput_rotated_T_63[527:16]} + : _rotatedInput_rotated_T_63; + always @(posedge clock or posedge reset) begin + if (reset) begin + buffer_0_addr <= 32'h0; + buffer_0_inst <= 32'h0; + buffer_0_brchFwd <= 1'h0; + buffer_1_addr <= 32'h0; + buffer_1_inst <= 32'h0; + buffer_1_brchFwd <= 1'h0; + buffer_2_addr <= 32'h0; + buffer_2_inst <= 32'h0; + buffer_2_brchFwd <= 1'h0; + buffer_3_addr <= 32'h0; + buffer_3_inst <= 32'h0; + buffer_3_brchFwd <= 1'h0; + buffer_4_addr <= 32'h0; + buffer_4_inst <= 32'h0; + buffer_4_brchFwd <= 1'h0; + buffer_5_addr <= 32'h0; + buffer_5_inst <= 32'h0; + buffer_5_brchFwd <= 1'h0; + buffer_6_addr <= 32'h0; + buffer_6_inst <= 32'h0; + buffer_6_brchFwd <= 1'h0; + buffer_7_addr <= 32'h0; + buffer_7_inst <= 32'h0; + buffer_7_brchFwd <= 1'h0; + enqPtr <= 3'h0; + deqPtr <= 3'h0; + nEnqueued <= 4'h0; + end + else begin + if (rotatedInput_rotated[65]) begin + buffer_0_addr <= rotatedInput_rotated[64:33]; + buffer_0_inst <= rotatedInput_rotated[32:1]; + buffer_0_brchFwd <= rotatedInput_rotated[0]; + end + if (rotatedInput_rotated[131]) begin + buffer_1_addr <= rotatedInput_rotated[130:99]; + buffer_1_inst <= rotatedInput_rotated[98:67]; + buffer_1_brchFwd <= rotatedInput_rotated[66]; + end + if (rotatedInput_rotated[197]) begin + buffer_2_addr <= rotatedInput_rotated[196:165]; + buffer_2_inst <= rotatedInput_rotated[164:133]; + buffer_2_brchFwd <= rotatedInput_rotated[132]; + end + if (rotatedInput_rotated[263]) begin + buffer_3_addr <= rotatedInput_rotated[262:231]; + buffer_3_inst <= rotatedInput_rotated[230:199]; + buffer_3_brchFwd <= rotatedInput_rotated[198]; + end + if (rotatedInput_rotated[329]) begin + buffer_4_addr <= rotatedInput_rotated[328:297]; + buffer_4_inst <= rotatedInput_rotated[296:265]; + buffer_4_brchFwd <= rotatedInput_rotated[264]; + end + if (rotatedInput_rotated[395]) begin + buffer_5_addr <= rotatedInput_rotated[394:363]; + buffer_5_inst <= rotatedInput_rotated[362:331]; + buffer_5_brchFwd <= rotatedInput_rotated[330]; + end + if (rotatedInput_rotated[461]) begin + buffer_6_addr <= rotatedInput_rotated[460:429]; + buffer_6_inst <= rotatedInput_rotated[428:397]; + buffer_6_brchFwd <= rotatedInput_rotated[396]; + end + if (rotatedInput_rotated[527]) begin + buffer_7_addr <= rotatedInput_rotated[526:495]; + buffer_7_inst <= rotatedInput_rotated[494:463]; + buffer_7_brchFwd <= rotatedInput_rotated[462]; + end + enqPtr <= io_flush ? 3'h0 : enqPtr + io_enqValid; + deqPtr <= io_flush ? 3'h0 : deqPtr + io_deqReady; + nEnqueued <= + io_flush ? 4'h0 : nEnqueued + {1'h0, io_enqValid} - {1'h0, io_deqReady}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:16]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [4:0] i = 5'h0; i < 5'h11; i += 5'h1) begin + _RANDOM[i] = `RANDOM; + end + buffer_0_addr = _RANDOM[5'h0]; + buffer_0_inst = _RANDOM[5'h1]; + buffer_0_brchFwd = _RANDOM[5'h2][0]; + buffer_1_addr = {_RANDOM[5'h2][31:1], _RANDOM[5'h3][0]}; + buffer_1_inst = {_RANDOM[5'h3][31:1], _RANDOM[5'h4][0]}; + buffer_1_brchFwd = _RANDOM[5'h4][1]; + buffer_2_addr = {_RANDOM[5'h4][31:2], _RANDOM[5'h5][1:0]}; + buffer_2_inst = {_RANDOM[5'h5][31:2], _RANDOM[5'h6][1:0]}; + buffer_2_brchFwd = _RANDOM[5'h6][2]; + buffer_3_addr = {_RANDOM[5'h6][31:3], _RANDOM[5'h7][2:0]}; + buffer_3_inst = {_RANDOM[5'h7][31:3], _RANDOM[5'h8][2:0]}; + buffer_3_brchFwd = _RANDOM[5'h8][3]; + buffer_4_addr = {_RANDOM[5'h8][31:4], _RANDOM[5'h9][3:0]}; + buffer_4_inst = {_RANDOM[5'h9][31:4], _RANDOM[5'hA][3:0]}; + buffer_4_brchFwd = _RANDOM[5'hA][4]; + buffer_5_addr = {_RANDOM[5'hA][31:5], _RANDOM[5'hB][4:0]}; + buffer_5_inst = {_RANDOM[5'hB][31:5], _RANDOM[5'hC][4:0]}; + buffer_5_brchFwd = _RANDOM[5'hC][5]; + buffer_6_addr = {_RANDOM[5'hC][31:6], _RANDOM[5'hD][5:0]}; + buffer_6_inst = {_RANDOM[5'hD][31:6], _RANDOM[5'hE][5:0]}; + buffer_6_brchFwd = _RANDOM[5'hE][6]; + buffer_7_addr = {_RANDOM[5'hE][31:7], _RANDOM[5'hF][6:0]}; + buffer_7_inst = {_RANDOM[5'hF][31:7], _RANDOM[5'h10][6:0]}; + buffer_7_brchFwd = _RANDOM[5'h10][7]; + enqPtr = _RANDOM[5'h10][10:8]; + deqPtr = _RANDOM[5'h10][13:11]; + nEnqueued = _RANDOM[5'h10][17:14]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + buffer_0_addr = 32'h0; + buffer_0_inst = 32'h0; + buffer_0_brchFwd = 1'h0; + buffer_1_addr = 32'h0; + buffer_1_inst = 32'h0; + buffer_1_brchFwd = 1'h0; + buffer_2_addr = 32'h0; + buffer_2_inst = 32'h0; + buffer_2_brchFwd = 1'h0; + buffer_3_addr = 32'h0; + buffer_3_inst = 32'h0; + buffer_3_brchFwd = 1'h0; + buffer_4_addr = 32'h0; + buffer_4_inst = 32'h0; + buffer_4_brchFwd = 1'h0; + buffer_5_addr = 32'h0; + buffer_5_inst = 32'h0; + buffer_5_brchFwd = 1'h0; + buffer_6_addr = 32'h0; + buffer_6_inst = 32'h0; + buffer_6_brchFwd = 1'h0; + buffer_7_addr = 32'h0; + buffer_7_inst = 32'h0; + buffer_7_brchFwd = 1'h0; + enqPtr = 3'h0; + deqPtr = 3'h0; + nEnqueued = 4'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_nEnqueued = nEnqueued; + assign io_nSpace = 4'h8 - nEnqueued; + assign io_dataOut_0_addr = outputBufferView_rotated[64:33]; + assign io_dataOut_0_inst = outputBufferView_rotated[32:1]; + assign io_dataOut_0_brchFwd = outputBufferView_rotated[0]; + assign io_dataOut_1_addr = outputBufferView_rotated[129:98]; + assign io_dataOut_1_inst = outputBufferView_rotated[97:66]; + assign io_dataOut_1_brchFwd = outputBufferView_rotated[65]; + assign io_dataOut_2_addr = outputBufferView_rotated[194:163]; + assign io_dataOut_2_inst = outputBufferView_rotated[162:131]; + assign io_dataOut_2_brchFwd = outputBufferView_rotated[130]; + assign io_dataOut_3_addr = outputBufferView_rotated[259:228]; + assign io_dataOut_3_inst = outputBufferView_rotated[227:196]; + assign io_dataOut_3_brchFwd = outputBufferView_rotated[195]; +endmodule + +module InstructionBuffer( + input clock, + reset, + output [2:0] io_feedIn_nReady, + input [2:0] io_feedIn_nValid, + input [31:0] io_feedIn_bits_0_addr, + io_feedIn_bits_0_inst, + input io_feedIn_bits_0_brchFwd, + input [31:0] io_feedIn_bits_1_addr, + io_feedIn_bits_1_inst, + input io_feedIn_bits_1_brchFwd, + input [31:0] io_feedIn_bits_2_addr, + io_feedIn_bits_2_inst, + input io_feedIn_bits_2_brchFwd, + input [31:0] io_feedIn_bits_3_addr, + io_feedIn_bits_3_inst, + input io_feedIn_bits_3_brchFwd, + io_out_0_ready, + output io_out_0_valid, + output [31:0] io_out_0_bits_addr, + io_out_0_bits_inst, + output io_out_0_bits_brchFwd, + input io_out_1_ready, + output io_out_1_valid, + output [31:0] io_out_1_bits_addr, + io_out_1_bits_inst, + output io_out_1_bits_brchFwd, + input io_out_2_ready, + output io_out_2_valid, + output [31:0] io_out_2_bits_addr, + io_out_2_bits_inst, + output io_out_2_bits_brchFwd, + input io_out_3_ready, + output io_out_3_valid, + output [31:0] io_out_3_bits_addr, + io_out_3_bits_inst, + output io_out_3_bits_brchFwd, + input io_flush, + output [3:0] io_nEnqueued, + io_nSpace +); + + wire [3:0] _circularBuffer_io_nEnqueued; + wire [3:0] _circularBuffer_io_nSpace; + wire io_out_0_valid_0 = (|_circularBuffer_io_nEnqueued) & ~io_flush; + wire io_out_1_valid_0 = (|(_circularBuffer_io_nEnqueued[3:1])) & ~io_flush; + wire io_out_2_valid_0 = _circularBuffer_io_nEnqueued > 4'h2 & ~io_flush; + wire io_out_3_valid_0 = (|(_circularBuffer_io_nEnqueued[3:2])) & ~io_flush; + wire _nReady_T = io_out_0_ready & io_out_0_valid_0; + wire _nReady_T_1 = io_out_1_ready & io_out_1_valid_0; + wire _nReady_T_2 = io_out_2_ready & io_out_2_valid_0; + wire _nReady_T_3 = io_out_3_ready & io_out_3_valid_0; + CircularBufferMulti circularBuffer ( + .clock (clock), + .reset (reset), + .io_enqValid (io_feedIn_nValid), + .io_enqData_0_addr (io_feedIn_bits_0_addr), + .io_enqData_0_inst (io_feedIn_bits_0_inst), + .io_enqData_0_brchFwd (io_feedIn_bits_0_brchFwd), + .io_enqData_1_addr (io_feedIn_bits_1_addr), + .io_enqData_1_inst (io_feedIn_bits_1_inst), + .io_enqData_1_brchFwd (io_feedIn_bits_1_brchFwd), + .io_enqData_2_addr (io_feedIn_bits_2_addr), + .io_enqData_2_inst (io_feedIn_bits_2_inst), + .io_enqData_2_brchFwd (io_feedIn_bits_2_brchFwd), + .io_enqData_3_addr (io_feedIn_bits_3_addr), + .io_enqData_3_inst (io_feedIn_bits_3_inst), + .io_enqData_3_brchFwd (io_feedIn_bits_3_brchFwd), + .io_nEnqueued (_circularBuffer_io_nEnqueued), + .io_nSpace (_circularBuffer_io_nSpace), + .io_dataOut_0_addr (io_out_0_bits_addr), + .io_dataOut_0_inst (io_out_0_bits_inst), + .io_dataOut_0_brchFwd (io_out_0_bits_brchFwd), + .io_dataOut_1_addr (io_out_1_bits_addr), + .io_dataOut_1_inst (io_out_1_bits_inst), + .io_dataOut_1_brchFwd (io_out_1_bits_brchFwd), + .io_dataOut_2_addr (io_out_2_bits_addr), + .io_dataOut_2_inst (io_out_2_bits_inst), + .io_dataOut_2_brchFwd (io_out_2_bits_brchFwd), + .io_dataOut_3_addr (io_out_3_bits_addr), + .io_dataOut_3_inst (io_out_3_bits_inst), + .io_dataOut_3_brchFwd (io_out_3_bits_brchFwd), + .io_deqReady + ({1'h0, {1'h0, _nReady_T} + {1'h0, _nReady_T_1}} + + {1'h0, {1'h0, _nReady_T_2} + {1'h0, _nReady_T_3}}), + .io_flush (io_flush) + ); + assign io_feedIn_nReady = + _circularBuffer_io_nSpace < 4'h4 ? _circularBuffer_io_nSpace[2:0] : 3'h4; + assign io_out_0_valid = io_out_0_valid_0; + assign io_out_1_valid = io_out_1_valid_0; + assign io_out_2_valid = io_out_2_valid_0; + assign io_out_3_valid = io_out_3_valid_0; + assign io_nEnqueued = _circularBuffer_io_nEnqueued; + assign io_nSpace = _circularBuffer_io_nSpace; +endmodule + +module UncachedFetch( + input clock, + reset, + input [31:0] io_csr_value_0, + output io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + input io_inst_lanes_0_ready, + output io_inst_lanes_0_valid, + output [31:0] io_inst_lanes_0_bits_addr, + io_inst_lanes_0_bits_inst, + output io_inst_lanes_0_bits_brchFwd, + input io_inst_lanes_1_ready, + output io_inst_lanes_1_valid, + output [31:0] io_inst_lanes_1_bits_addr, + io_inst_lanes_1_bits_inst, + output io_inst_lanes_1_bits_brchFwd, + input io_inst_lanes_2_ready, + output io_inst_lanes_2_valid, + output [31:0] io_inst_lanes_2_bits_addr, + io_inst_lanes_2_bits_inst, + output io_inst_lanes_2_bits_brchFwd, + input io_inst_lanes_3_ready, + output io_inst_lanes_3_valid, + output [31:0] io_inst_lanes_3_bits_addr, + io_inst_lanes_3_bits_inst, + output io_inst_lanes_3_bits_brchFwd, + input io_branch_0_valid, + input [31:0] io_branch_0_value, + input io_branch_1_valid, + input [31:0] io_branch_1_value, + input io_branch_2_valid, + input [31:0] io_branch_2_value, + input io_branch_3_valid, + input [31:0] io_branch_3_value, + input io_iflush_valid, + input [31:0] io_iflush_pcNext, + output [31:0] io_pc +); + + wire _instructionBuffer_io_out_0_valid; + wire [31:0] _instructionBuffer_io_out_0_bits_addr; + wire [3:0] _instructionBuffer_io_nSpace; + wire _fetcher_io_fetch_valid; + wire [31:0] _fetcher_io_fetch_bits_addr; + wire [31:0] _fetcher_io_fetch_bits_inst_0; + wire [31:0] _fetcher_io_fetch_bits_inst_1; + wire [31:0] _fetcher_io_fetch_bits_inst_2; + wire [31:0] _fetcher_io_fetch_bits_inst_3; + wire _ctrl_io_fetchAddr_valid; + wire [31:0] _ctrl_io_fetchAddr_bits; + wire [2:0] _ctrl_io_bufferRequest_nValid; + wire [31:0] _ctrl_io_bufferRequest_bits_0_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_0_inst; + wire _ctrl_io_bufferRequest_bits_0_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_1_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_1_inst; + wire _ctrl_io_bufferRequest_bits_1_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_2_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_2_inst; + wire _ctrl_io_bufferRequest_bits_2_brchFwd; + wire [31:0] _ctrl_io_bufferRequest_bits_3_addr; + wire [31:0] _ctrl_io_bufferRequest_bits_3_inst; + wire _ctrl_io_bufferRequest_bits_3_brchFwd; + wire branch_valid = + io_branch_0_valid | io_branch_1_valid | io_branch_2_valid | io_branch_3_valid; + reg [31:0] pc; + always @(posedge clock or posedge reset) begin + if (reset) + pc <= 32'h0; + else if (_instructionBuffer_io_out_0_valid) + pc <= _instructionBuffer_io_out_0_bits_addr; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + pc = _RANDOM[/*Zero width*/ 1'b0]; + `endif // RANDOMIZE_REG_INIT + if (reset) + pc = 32'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FetchControl ctrl ( + .clock (clock), + .reset (reset), + .io_csr_value_0 (io_csr_value_0), + .io_iflush_valid (io_iflush_valid), + .io_iflush_bits (io_iflush_pcNext), + .io_branch_valid (branch_valid), + .io_branch_bits + (io_branch_0_valid + ? io_branch_0_value + : io_branch_1_valid + ? io_branch_1_value + : io_branch_2_valid + ? io_branch_2_value + : io_branch_3_valid ? io_branch_3_value : 32'h0), + .io_fetchData_valid (_fetcher_io_fetch_valid), + .io_fetchData_bits_addr (_fetcher_io_fetch_bits_addr), + .io_fetchData_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), + .io_fetchData_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), + .io_fetchData_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), + .io_fetchData_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), + .io_fetchAddr_valid (_ctrl_io_fetchAddr_valid), + .io_fetchAddr_bits (_ctrl_io_fetchAddr_bits), + .io_bufferRequest_nValid (_ctrl_io_bufferRequest_nValid), + .io_bufferRequest_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), + .io_bufferRequest_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), + .io_bufferRequest_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_bufferRequest_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), + .io_bufferRequest_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), + .io_bufferRequest_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_bufferRequest_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), + .io_bufferRequest_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), + .io_bufferRequest_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_bufferRequest_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), + .io_bufferRequest_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), + .io_bufferRequest_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd), + .io_bufferSpaces (_instructionBuffer_io_nSpace) + ); + Fetcher fetcher ( + .clock (clock), + .reset (reset), + .io_ctrl_valid (_ctrl_io_fetchAddr_valid), + .io_ctrl_bits (_ctrl_io_fetchAddr_bits), + .io_fetch_valid (_fetcher_io_fetch_valid), + .io_fetch_bits_addr (_fetcher_io_fetch_bits_addr), + .io_fetch_bits_inst_0 (_fetcher_io_fetch_bits_inst_0), + .io_fetch_bits_inst_1 (_fetcher_io_fetch_bits_inst_1), + .io_fetch_bits_inst_2 (_fetcher_io_fetch_bits_inst_2), + .io_fetch_bits_inst_3 (_fetcher_io_fetch_bits_inst_3), + .io_ibus_valid (io_ibus_valid), + .io_ibus_ready (io_ibus_ready), + .io_ibus_addr (io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata) + ); + InstructionBuffer instructionBuffer ( + .clock (clock), + .reset (reset), + .io_feedIn_nReady (/* unused */), + .io_feedIn_nValid (_ctrl_io_bufferRequest_nValid), + .io_feedIn_bits_0_addr (_ctrl_io_bufferRequest_bits_0_addr), + .io_feedIn_bits_0_inst (_ctrl_io_bufferRequest_bits_0_inst), + .io_feedIn_bits_0_brchFwd (_ctrl_io_bufferRequest_bits_0_brchFwd), + .io_feedIn_bits_1_addr (_ctrl_io_bufferRequest_bits_1_addr), + .io_feedIn_bits_1_inst (_ctrl_io_bufferRequest_bits_1_inst), + .io_feedIn_bits_1_brchFwd (_ctrl_io_bufferRequest_bits_1_brchFwd), + .io_feedIn_bits_2_addr (_ctrl_io_bufferRequest_bits_2_addr), + .io_feedIn_bits_2_inst (_ctrl_io_bufferRequest_bits_2_inst), + .io_feedIn_bits_2_brchFwd (_ctrl_io_bufferRequest_bits_2_brchFwd), + .io_feedIn_bits_3_addr (_ctrl_io_bufferRequest_bits_3_addr), + .io_feedIn_bits_3_inst (_ctrl_io_bufferRequest_bits_3_inst), + .io_feedIn_bits_3_brchFwd (_ctrl_io_bufferRequest_bits_3_brchFwd), + .io_out_0_ready (io_inst_lanes_0_ready), + .io_out_0_valid (_instructionBuffer_io_out_0_valid), + .io_out_0_bits_addr (_instructionBuffer_io_out_0_bits_addr), + .io_out_0_bits_inst (io_inst_lanes_0_bits_inst), + .io_out_0_bits_brchFwd (io_inst_lanes_0_bits_brchFwd), + .io_out_1_ready (io_inst_lanes_1_ready), + .io_out_1_valid (io_inst_lanes_1_valid), + .io_out_1_bits_addr (io_inst_lanes_1_bits_addr), + .io_out_1_bits_inst (io_inst_lanes_1_bits_inst), + .io_out_1_bits_brchFwd (io_inst_lanes_1_bits_brchFwd), + .io_out_2_ready (io_inst_lanes_2_ready), + .io_out_2_valid (io_inst_lanes_2_valid), + .io_out_2_bits_addr (io_inst_lanes_2_bits_addr), + .io_out_2_bits_inst (io_inst_lanes_2_bits_inst), + .io_out_2_bits_brchFwd (io_inst_lanes_2_bits_brchFwd), + .io_out_3_ready (io_inst_lanes_3_ready), + .io_out_3_valid (io_inst_lanes_3_valid), + .io_out_3_bits_addr (io_inst_lanes_3_bits_addr), + .io_out_3_bits_inst (io_inst_lanes_3_bits_inst), + .io_out_3_bits_brchFwd (io_inst_lanes_3_bits_brchFwd), + .io_flush (io_iflush_valid | branch_valid), + .io_nEnqueued (/* unused */), + .io_nSpace (_instructionBuffer_io_nSpace) + ); + assign io_inst_lanes_0_valid = _instructionBuffer_io_out_0_valid; + assign io_inst_lanes_0_bits_addr = _instructionBuffer_io_out_0_bits_addr; + assign io_pc = pc; +endmodule + +module Csr( + input clock, + reset, + input [31:0] io_csr_in_value_12, + output [31:0] io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + input io_req_valid, + input [4:0] io_req_bits_addr, + input [11:0] io_req_bits_index, + input [1:0] io_req_bits_op, + input io_rs1_valid, + input [31:0] io_rs1_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + input io_bru_in_mode_valid, + input [1:0] io_bru_in_mode_bits, + input io_bru_in_mcause_valid, + input [31:0] io_bru_in_mcause_bits, + input io_bru_in_mepc_valid, + input [31:0] io_bru_in_mepc_bits, + input io_bru_in_mtval_valid, + input [31:0] io_bru_in_mtval_bits, + input io_bru_in_halt, + io_bru_in_fault, + io_bru_in_wfi, + output [1:0] io_bru_out_mode, + output [31:0] io_bru_out_mepc, + io_bru_out_mtvec, + input io_float_in_fflags_valid, + input [4:0] io_float_in_fflags_bits, + output [2:0] io_float_out_frm, + input [2:0] io_counters_rfwriteCount, + input [1:0] io_counters_storeCount, + input io_counters_branchCount, + output io_halted, + io_fault, + io_wfi, + input io_irq +); + + reg req_pipe_v; + reg [4:0] req_pipe_b_addr; + reg [11:0] req_pipe_b_index; + reg [1:0] req_pipe_b_op; + reg halted; + reg fault; + reg wfi; + reg [1:0] mode; + reg [31:0] mpc; + reg [31:0] msp; + reg [31:0] mcause; + reg [31:0] mtval; + reg [31:0] mcontext0; + reg [31:0] mcontext1; + reg [31:0] mcontext2; + reg [31:0] mcontext3; + reg [31:0] mcontext4; + reg [31:0] mcontext5; + reg [31:0] mcontext6; + reg [31:0] mcontext7; + reg [4:0] fflags; + reg [2:0] frm; + reg mie; + reg [31:0] mtvec; + reg [31:0] mscratch; + reg [31:0] mepc; + reg [1:0] mpp; + reg [63:0] mcycle; + reg [63:0] minstret; + wire fflagsEn = req_pipe_b_index == 12'h1; + wire frmEn = req_pipe_b_index == 12'h2; + wire fcsrEn = req_pipe_b_index == 12'h3; + wire mstatusEn = req_pipe_b_index == 12'h300; + wire misaEn = req_pipe_b_index == 12'h301; + wire mieEn = req_pipe_b_index == 12'h304; + wire mtvecEn = req_pipe_b_index == 12'h305; + wire mscratchEn = req_pipe_b_index == 12'h340; + wire mepcEn = req_pipe_b_index == 12'h341; + wire mcauseEn = req_pipe_b_index == 12'h342; + wire mtvalEn = req_pipe_b_index == 12'h343; + wire mcontext0En = req_pipe_b_index == 12'h7C0; + wire mcontext1En = req_pipe_b_index == 12'h7C1; + wire mcontext2En = req_pipe_b_index == 12'h7C2; + wire mcontext3En = req_pipe_b_index == 12'h7C3; + wire mcontext4En = req_pipe_b_index == 12'h7C4; + wire mcontext5En = req_pipe_b_index == 12'h7C5; + wire mcontext6En = req_pipe_b_index == 12'h7C6; + wire mcontext7En = req_pipe_b_index == 12'h7C7; + wire mpcEn = req_pipe_b_index == 12'h7E0; + wire mspEn = req_pipe_b_index == 12'h7E1; + wire mcycleEn = req_pipe_b_index == 12'hB00; + wire minstretEn = req_pipe_b_index == 12'hB02; + wire mcyclehEn = req_pipe_b_index == 12'hB80; + wire minstrethEn = req_pipe_b_index == 12'hB82; + wire mvendoridEn = req_pipe_b_index == 12'hF11; + wire marchidEn = req_pipe_b_index == 12'hF12; + wire mimpidEn = req_pipe_b_index == 12'hF13; + wire mhartidEn = req_pipe_b_index == 12'hF14; + wire kisaEn = req_pipe_b_index == 12'hFC0; + wire kscm0En = req_pipe_b_index == 12'hFC4; + wire kscm1En = req_pipe_b_index == 12'hFC8; + wire kscm2En = req_pipe_b_index == 12'hFCC; + wire kscm3En = req_pipe_b_index == 12'hFD0; + wire kscm4En = req_pipe_b_index == 12'hFD4; + wire [31:0] rdata = + fflagsEn + ? {27'h0, fflags} + : frmEn + ? {29'h0, frm} + : fcsrEn + ? {24'h0, frm, fflags} + : mstatusEn + ? {19'h0, mpp, 11'h0} + : misaEn + ? 32'h40001120 + : mieEn + ? {31'h0, mie} + : mtvecEn + ? mtvec + : mscratchEn + ? mscratch + : mepcEn + ? mepc + : mcauseEn + ? mcause + : mtvalEn + ? mtval + : mcontext0En + ? mcontext0 + : mcontext1En + ? mcontext1 + : mcontext2En + ? mcontext2 + : mcontext3En + ? mcontext3 + : mcontext4En + ? mcontext4 + : mcontext5En + ? mcontext5 + : mcontext6En + ? mcontext6 + : mcontext7En + ? mcontext7 + : mpcEn + ? mpc + : mspEn + ? msp + : mcycleEn + ? mcycle[31:0] + : mcyclehEn + ? mcycle[63:32] + : minstretEn + ? minstret[31:0] + : minstrethEn + ? minstret[63:32] + : mvendoridEn + ? 32'h426 + : marchidEn + | mimpidEn + | mhartidEn + | kisaEn + ? 32'h0 + : kscm0En + ? 32'hE25C2997 + : kscm1En + ? 32'hA8C4C694 + : kscm2En + ? 32'hF9845884 + : kscm3En + ? 32'h8522A4D6 + : kscm4En + ? 32'hF3300946 + : 32'h0; + wire [3:0][31:0] _GEN = + {{32'h0}, {rdata & ~io_rs1_data}, {rdata | io_rs1_data}, {io_rs1_data}}; + wire [31:0] wdata = _GEN[req_pipe_b_op]; + wire [2:0] _minstretThisCycle_T_2 = + io_counters_rfwriteCount + {1'h0, io_counters_storeCount} + + {2'h0, io_counters_branchCount}; + always @(posedge clock or posedge reset) begin + if (reset) begin + req_pipe_v <= 1'h0; + halted <= 1'h0; + fault <= 1'h0; + wfi <= 1'h0; + mode <= 2'h0; + mpc <= 32'h0; + msp <= 32'h0; + mcause <= 32'h0; + mtval <= 32'h0; + mcontext0 <= 32'h0; + mcontext1 <= 32'h0; + mcontext2 <= 32'h0; + mcontext3 <= 32'h0; + mcontext4 <= 32'h0; + mcontext5 <= 32'h0; + mcontext6 <= 32'h0; + mcontext7 <= 32'h0; + fflags <= 5'h0; + frm <= 3'h0; + mie <= 1'h0; + mtvec <= 32'h0; + mscratch <= 32'h0; + mepc <= 32'h0; + mpp <= 2'h0; + mcycle <= 64'h0; + minstret <= 64'h0; + end + else begin + req_pipe_v <= io_req_valid; + halted <= io_bru_in_halt | halted; + fault <= io_bru_in_fault | fault; + if (wfi) + wfi <= ~io_irq; + else + wfi <= io_bru_in_wfi; + if (io_bru_in_mode_valid) + mode <= io_bru_in_mode_bits; + if (req_pipe_v & mpcEn) + mpc <= wdata; + if (req_pipe_v & mspEn) + msp <= wdata; + if (io_bru_in_mcause_valid) + mcause <= io_bru_in_mcause_bits; + else if (req_pipe_v & mcauseEn) + mcause <= wdata; + if (io_bru_in_mtval_valid) + mtval <= io_bru_in_mtval_bits; + else if (req_pipe_v & mtvalEn) + mtval <= wdata; + if (req_pipe_v & mcontext0En) + mcontext0 <= wdata; + if (req_pipe_v & mcontext1En) + mcontext1 <= wdata; + if (req_pipe_v & mcontext2En) + mcontext2 <= wdata; + if (req_pipe_v & mcontext3En) + mcontext3 <= wdata; + if (req_pipe_v & mcontext4En) + mcontext4 <= wdata; + if (req_pipe_v & mcontext5En) + mcontext5 <= wdata; + if (req_pipe_v & mcontext6En) + mcontext6 <= wdata; + if (req_pipe_v & mcontext7En) + mcontext7 <= wdata; + if (io_float_in_fflags_valid) + fflags <= io_float_in_fflags_bits | fflags; + else if (req_pipe_v) begin + if (fcsrEn) + fflags <= wdata[4:0]; + else if (fflagsEn) + fflags <= wdata[4:0]; + end + if (req_pipe_v) begin + if (fcsrEn) + frm <= wdata[7:5]; + else if (frmEn) + frm <= wdata[2:0]; + minstret <= + {minstrethEn ? wdata : minstret[63:32], minstretEn ? wdata : minstret[31:0]}; + end + else if (|_minstretThisCycle_T_2) + minstret <= minstret + {61'h0, _minstretThisCycle_T_2}; + if (req_pipe_v & mieEn) + mie <= wdata[0]; + if (req_pipe_v & mtvecEn) + mtvec <= wdata; + if (req_pipe_v & mscratchEn) + mscratch <= wdata; + if (io_bru_in_mepc_valid) + mepc <= io_bru_in_mepc_bits; + else if (req_pipe_v & mepcEn) + mepc <= wdata; + if (req_pipe_v & mstatusEn) + mpp <= wdata[12:11]; + mcycle <= + (req_pipe_v + ? {mcyclehEn ? wdata : mcycle[63:32], mcycleEn ? wdata : mcycle[31:0]} + : mcycle) + 64'h1; + end + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_req_valid) begin + req_pipe_b_addr <= io_req_bits_addr; + req_pipe_b_index <= io_req_bits_index; + req_pipe_b_op <= io_req_bits_op; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:21]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [4:0] i = 5'h0; i < 5'h16; i += 5'h1) begin + _RANDOM[i] = `RANDOM; + end + req_pipe_v = _RANDOM[5'h0][0]; + req_pipe_b_addr = _RANDOM[5'h0][5:1]; + req_pipe_b_index = _RANDOM[5'h0][17:6]; + req_pipe_b_op = _RANDOM[5'h0][19:18]; + halted = _RANDOM[5'h0][20]; + fault = _RANDOM[5'h0][21]; + wfi = _RANDOM[5'h0][22]; + mode = _RANDOM[5'h0][24:23]; + mpc = {_RANDOM[5'h0][31:25], _RANDOM[5'h1][24:0]}; + msp = {_RANDOM[5'h1][31:25], _RANDOM[5'h2][24:0]}; + mcause = {_RANDOM[5'h2][31:25], _RANDOM[5'h3][24:0]}; + mtval = {_RANDOM[5'h3][31:25], _RANDOM[5'h4][24:0]}; + mcontext0 = {_RANDOM[5'h4][31:25], _RANDOM[5'h5][24:0]}; + mcontext1 = {_RANDOM[5'h5][31:25], _RANDOM[5'h6][24:0]}; + mcontext2 = {_RANDOM[5'h6][31:25], _RANDOM[5'h7][24:0]}; + mcontext3 = {_RANDOM[5'h7][31:25], _RANDOM[5'h8][24:0]}; + mcontext4 = {_RANDOM[5'h8][31:25], _RANDOM[5'h9][24:0]}; + mcontext5 = {_RANDOM[5'h9][31:25], _RANDOM[5'hA][24:0]}; + mcontext6 = {_RANDOM[5'hA][31:25], _RANDOM[5'hB][24:0]}; + mcontext7 = {_RANDOM[5'hB][31:25], _RANDOM[5'hC][24:0]}; + fflags = _RANDOM[5'hC][29:25]; + frm = {_RANDOM[5'hC][31:30], _RANDOM[5'hD][0]}; + mie = _RANDOM[5'hD][1]; + mtvec = {_RANDOM[5'hD][31:2], _RANDOM[5'hE][1:0]}; + mscratch = {_RANDOM[5'hE][31:2], _RANDOM[5'hF][1:0]}; + mepc = {_RANDOM[5'hF][31:2], _RANDOM[5'h10][1:0]}; + mpp = _RANDOM[5'h10][3:2]; + mcycle = {_RANDOM[5'h11][31:4], _RANDOM[5'h12], _RANDOM[5'h13][3:0]}; + minstret = {_RANDOM[5'h13][31:4], _RANDOM[5'h14], _RANDOM[5'h15][3:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + req_pipe_v = 1'h0; + halted = 1'h0; + fault = 1'h0; + wfi = 1'h0; + mode = 2'h0; + mpc = 32'h0; + msp = 32'h0; + mcause = 32'h0; + mtval = 32'h0; + mcontext0 = 32'h0; + mcontext1 = 32'h0; + mcontext2 = 32'h0; + mcontext3 = 32'h0; + mcontext4 = 32'h0; + mcontext5 = 32'h0; + mcontext6 = 32'h0; + mcontext7 = 32'h0; + fflags = 5'h0; + frm = 3'h0; + mie = 1'h0; + mtvec = 32'h0; + mscratch = 32'h0; + mepc = 32'h0; + mpp = 2'h0; + mcycle = 64'h0; + minstret = 64'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_csr_out_value_0 = io_csr_in_value_12; + assign io_csr_out_value_1 = mepc; + assign io_csr_out_value_2 = mtval; + assign io_csr_out_value_3 = mcause; + assign io_csr_out_value_4 = mcycle[31:0]; + assign io_csr_out_value_5 = mcycle[63:32]; + assign io_csr_out_value_6 = minstret[31:0]; + assign io_csr_out_value_7 = minstret[63:32]; + assign io_rd_valid = req_pipe_v; + assign io_rd_bits_addr = req_pipe_b_addr; + assign io_rd_bits_data = rdata; + assign io_bru_out_mode = mode; + assign io_bru_out_mepc = mepcEn & req_pipe_v ? wdata : mepc; + assign io_bru_out_mtvec = mtvecEn & req_pipe_v ? wdata : mtvec; + assign io_float_out_frm = frmEn & req_pipe_v ? wdata[2:0] : frm; + assign io_halted = halted; + assign io_fault = fault; + assign io_wfi = wfi; +endmodule + +module Decode( + input io_halted, + output io_inst_ready, + input io_inst_valid, + input [31:0] io_inst_bits_addr, + io_inst_bits_inst, + input io_inst_bits_brchFwd, + input [31:0] io_scoreboard_regd, + io_scoreboard_comb, + output [31:0] io_scoreboard_spec, + input [31:0] io_fscoreboard, + input io_lsuActive, + output io_rs1Read_valid, + output [4:0] io_rs1Read_addr, + output io_rs1Set_valid, + output [31:0] io_rs1Set_value, + output io_rs2Read_valid, + output [4:0] io_rs2Read_addr, + output io_rs2Set_valid, + output [31:0] io_rs2Set_value, + output io_rdMark_valid, + output [4:0] io_rdMark_addr, + output io_rdMark_flt_valid, + output [4:0] io_rdMark_flt_addr, + output io_busRead_bypass, + io_busRead_immen, + output [31:0] io_busRead_immed, + output io_jalFault, + io_jalrFault, + io_bxxFault, + io_undefFault, + output [31:0] io_bruTarget, + input [31:0] io_jalrTarget_data, + output io_alu_valid, + output [4:0] io_alu_bits_addr, + io_alu_bits_op, + output io_bru_valid, + io_bru_bits_fwd, + output [3:0] io_bru_bits_op, + output [31:0] io_bru_bits_pc, + io_bru_bits_target, + output [4:0] io_bru_bits_link, + output io_csr_valid, + output [4:0] io_csr_bits_addr, + output [11:0] io_csr_bits_index, + output [1:0] io_csr_bits_op, + output io_csrFault, + input io_lsu_ready, + output io_lsu_valid, + io_lsu_bits_store, + output [4:0] io_lsu_bits_addr, + io_lsu_bits_op, + output [31:0] io_lsu_bits_pc, + output io_mlu_valid, + output [4:0] io_mlu_bits_addr, + output [2:0] io_mlu_bits_op, + input io_dvu_ready, + output io_dvu_valid, + output [4:0] io_dvu_bits_addr, + output [1:0] io_dvu_bits_op, + input io_float_ready, + output io_float_valid, + output [2:0] io_float_bits_opcode, + output [4:0] io_float_bits_funct5, + io_float_bits_rs3, + io_float_bits_rs2, + io_float_bits_rs1, + output [2:0] io_float_bits_rm, + output [31:0] io_float_bits_inst, + io_float_bits_pc, + output io_float_bits_scalar_rd, + io_float_bits_scalar_rs1, + output [4:0] io_float_bits_rd, + output io_float_bits_uses_rs3, + io_float_bits_uses_rs2, + input io_branchTaken, + io_interlock, + output io_serializeOut_mul, + io_serializeOut_jump, + io_serializeOut_brcond, + io_serializeOut_wfi, + io_serializeOut_fence, + io_serializeOut_csr, + io_serializeOut_undef, + io_slog +); + + wire io_inst_ready_0; + wire io_busRead_bypass_0; + wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; + wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; + wire [31:0] d_immcsr = {27'h0, io_inst_bits_inst[19:15]}; + wire d_lui = io_inst_bits_inst[6:0] == 7'h37; + wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; + wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; + wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_jalr = _GEN == 10'h67; + wire d_beq = _GEN == 10'h63; + wire d_bne = _GEN == 10'hE3; + wire d_blt = _GEN == 10'h263; + wire d_bge = _GEN == 10'h2E3; + wire d_bltu = _GEN == 10'h363; + wire d_bgeu = _GEN == 10'h3E3; + wire [8:0] _GEN_0 = {io_inst_bits_inst[13:12], io_inst_bits_inst[6:0]}; + wire d_csrrw = _GEN_0 == 9'hF3; + wire d_csrrs = _GEN_0 == 9'h173; + wire d_csrrc = _GEN_0 == 9'h1F3; + wire d_lb = _GEN == 10'h3; + wire d_lh = _GEN == 10'h83; + wire d_lw = _GEN == 10'h103; + wire d_lbu = _GEN == 10'h203; + wire d_lhu = _GEN == 10'h283; + wire d_sb = _GEN == 10'h23; + wire d_sh = _GEN == 10'hA3; + wire d_sw = _GEN == 10'h123; + wire d_addi = _GEN == 10'h13; + wire d_slti = _GEN == 10'h113; + wire d_sltiu = _GEN == 10'h193; + wire d_xori = _GEN == 10'h213; + wire d_ori = _GEN == 10'h313; + wire d_andi = _GEN == 10'h393; + wire [16:0] _GEN_1 = + {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_slli = _GEN_1 == 17'h93; + wire d_srli = _GEN_1 == 17'h293; + wire d_srai = _GEN_1 == 17'h8293; + wire d_add = _GEN_1 == 17'h33; + wire d_sub = _GEN_1 == 17'h8033; + wire d_slt = _GEN_1 == 17'h133; + wire d_sltu = _GEN_1 == 17'h1B3; + wire d_xor = _GEN_1 == 17'h233; + wire d_or = _GEN_1 == 17'h333; + wire d_and = _GEN_1 == 17'h3B3; + wire d_sll = _GEN_1 == 17'hB3; + wire d_srl = _GEN_1 == 17'h2B3; + wire d_sra = _GEN_1 == 17'h82B3; + wire d_mul = _GEN_1 == 17'h433; + wire d_mulh = _GEN_1 == 17'h4B3; + wire d_mulhsu = _GEN_1 == 17'h533; + wire d_mulhu = _GEN_1 == 17'h5B3; + wire d_div = _GEN_1 == 17'h633; + wire d_divu = _GEN_1 == 17'h6B3; + wire d_rem = _GEN_1 == 17'h733; + wire d_remu = _GEN_1 == 17'h7B3; + wire d_andn = _GEN_1 == 17'h83B3; + wire d_orn = _GEN_1 == 17'h8333; + wire d_xnor = _GEN_1 == 17'h8233; + wire [21:0] _GEN_2 = + {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_clz = _GEN_2 == 22'h180093; + wire d_ctz = _GEN_2 == 22'h180493; + wire d_cpop = _GEN_2 == 22'h180893; + wire d_max = _GEN_1 == 17'h1733; + wire d_maxu = _GEN_1 == 17'h17B3; + wire d_min = _GEN_1 == 17'h1633; + wire d_minu = _GEN_1 == 17'h16B3; + wire d_sextb = _GEN_2 == 22'h181093; + wire d_sexth = _GEN_2 == 22'h181493; + wire d_rol = _GEN_1 == 17'hC0B3; + wire d_ror = _GEN_1 == 17'hC2B3; + wire d_orcb = _GEN_2 == 22'hA1E93; + wire d_rev8 = _GEN_2 == 22'h1A6293; + wire d_zexth = _GEN_2 == 22'h20233; + wire d_rori = _GEN_1 == 17'hC293; + wire d_slog = + {io_inst_bits_inst[31:20], + io_inst_bits_inst[14], + io_inst_bits_inst[11:0]} == 25'hF00077; + wire d_ebreak = io_inst_bits_inst == 32'h100073; + wire d_ecall = io_inst_bits_inst == 32'h73; + wire d_mpause = io_inst_bits_inst == 32'h8000073; + wire d_mret = io_inst_bits_inst == 32'h30200073; + wire d_wfi = io_inst_bits_inst == 32'h10500073; + wire d_fencei = io_inst_bits_inst == 32'h100F; + wire d_flushat = + {io_inst_bits_inst[31:28], + io_inst_bits_inst[24:20], + io_inst_bits_inst[14:0]} == 24'h200077 & (|(io_inst_bits_inst[19:15])); + wire d_flushall = + {io_inst_bits_inst[31:28], io_inst_bits_inst[24:0]} == 29'h4000077; + wire d_d_float_load_store_rm_valid = + io_inst_bits_inst[14:12] == 3'h1 | io_inst_bits_inst[14:12] == 3'h2; + wire _d_d_float_opcode_T_4 = io_inst_bits_inst[6:2] == 5'h9; + wire _d_d_float_opcode_T_6 = io_inst_bits_inst[6:2] == 5'h14; + wire _d_d_float_opcode_T_8 = io_inst_bits_inst[6:2] == 5'h10; + wire _d_d_float_opcode_T_10 = io_inst_bits_inst[6:2] == 5'h11; + wire _d_d_float_opcode_T_12 = io_inst_bits_inst[6:2] == 5'h12; + wire _d_d_float_opcode_T_14 = io_inst_bits_inst[6:2] == 5'h13; + wire [2:0] d_d_float_opcode_bits = + _d_d_float_opcode_T_14 + ? 3'h5 + : _d_d_float_opcode_T_12 + ? 3'h6 + : _d_d_float_opcode_T_10 + ? 3'h4 + : _d_d_float_opcode_T_8 + ? 3'h3 + : _d_d_float_opcode_T_6 + ? 3'h2 + : {2'h0, _d_d_float_opcode_T_4 & d_d_float_load_store_rm_valid}; + wire _d_d_float_uses_rs2_T_5 = io_inst_bits_inst[31:27] == 5'h1C; + wire _d_d_float_uses_rs2_T_7 = io_inst_bits_inst[31:27] == 5'h18; + wire _d_d_float_uses_rs2_T_2 = d_d_float_opcode_bits == 3'h2; + wire d_d_float_scalar_rd = + (_d_d_float_uses_rs2_T_7 | _d_d_float_uses_rs2_T_5 + | io_inst_bits_inst[31:27] == 5'h14) & _d_d_float_uses_rs2_T_2; + wire _d_d_float_uses_rs2_T_9 = io_inst_bits_inst[31:27] == 5'h1E; + wire _d_d_float_uses_rs2_T_11 = io_inst_bits_inst[31:27] == 5'h1A; + wire d_d_float_scalar_rs1 = _d_d_float_uses_rs2_T_11 | _d_d_float_uses_rs2_T_9; + wire _d_d_float_T_1 = d_d_float_opcode_bits == 3'h1; + wire d_d_float_y = + (_d_d_float_opcode_T_14 | _d_d_float_opcode_T_12 | _d_d_float_opcode_T_10 + | _d_d_float_opcode_T_8 | _d_d_float_opcode_T_6 + | (_d_d_float_opcode_T_4 | io_inst_bits_inst[6:2] == 5'h1) + & d_d_float_load_store_rm_valid) + & (d_d_float_opcode_bits == 3'h0 | _d_d_float_T_1 | io_inst_bits_inst[26:25] == 2'h0); + wire d_undef = + {d_lui, + d_auipc, + d_jal, + d_jalr, + d_beq, + d_bne, + d_blt, + d_bge, + d_bltu, + d_bgeu, + d_csrrw, + d_csrrs, + d_csrrc, + d_lb, + d_lh, + d_lw, + d_lbu, + d_lhu, + d_sb, + d_sh, + d_sw, + {io_inst_bits_inst[31:28], io_inst_bits_inst[19:0]} == 24'hF, + d_addi, + d_slti, + d_sltiu, + d_xori, + d_ori, + d_andi, + d_add, + d_sub, + d_slt, + d_sltu, + d_xor, + d_or, + d_and, + d_xnor, + d_orn, + d_andn, + d_slli, + d_srli, + d_srai, + d_sll, + d_srl, + d_sra, + d_mul, + d_mulh, + d_mulhsu, + d_mulhu, + d_div, + d_divu, + d_rem, + d_remu, + d_clz, + d_ctz, + d_cpop, + d_min, + d_minu, + d_max, + d_maxu, + d_sextb, + d_sexth, + d_zexth, + d_rol, + d_ror, + d_orcb, + d_rev8, + d_rori, + d_ebreak, + d_ecall, + d_wfi, + d_mpause, + d_mret, + d_fencei, + d_flushat, + d_flushall, + d_slog, + d_d_float_y} == 77'h0; + wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[11:7]}; + wire [31:0] _floatEn_T_12 = io_scoreboard_comb >> _GEN_3; + wire _io_rs2Read_valid_T_24 = d_sb | d_sh; + wire _io_rs2Read_valid_T = d_beq | d_bne; + wire [31:0] _floatEn_T_18 = io_scoreboard_comb >> d_immcsr; + wire _rdMark_valid_T_5 = d_lb | d_lh; + wire _io_float_valid_T_5 = d_d_float_opcode_bits == 3'h0; + wire _lsu_T_3 = d_d_float_opcode_bits == 3'h1; + wire [31:0] _GEN_4 = {27'h0, io_inst_bits_inst[24:20]}; + wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> _GEN_4; + wire _io_rs2Set_valid_T_5 = d_addi | d_slti; + wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; + wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> d_immcsr; + wire bruEn = + ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 + & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; + wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; + wire _rdMark_valid_T_15 = d_d_float_y & d_d_float_scalar_rd; + wire _io_rs1Read_valid_T_58 = d_d_float_y & d_d_float_scalar_rs1; + wire [31:0] _floatEn_T_25 = io_fscoreboard >> _GEN_3; + wire [31:0] _floatEn_T_32 = io_fscoreboard >> d_immcsr; + wire [31:0] _floatEn_T_37 = io_fscoreboard >> _GEN_4; + wire [31:0] _floatEn_T_42 = io_fscoreboard >> io_inst_bits_inst[31:27]; + wire _io_serializeOut_fence_T = d_fencei | d_ebreak; + wire _alu_T_1 = d_auipc | d_addi | d_add; + wire _alu_T_2 = d_slti | d_slt; + wire _alu_T_3 = d_sltiu | d_sltu; + wire _alu_T_4 = d_xori | d_xor; + wire _alu_T_5 = d_ori | d_or; + wire _alu_T_6 = d_andi | d_and; + wire _alu_T_7 = d_slli | d_sll; + wire _alu_T_8 = d_srli | d_srl; + wire _alu_T_9 = d_srai | d_sra; + wire alu_valid = + _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 + | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop + | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb + | d_rev8 | d_zexth | d_rori; + wire bru_valid = + d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu | d_ebreak | d_ecall + | d_mpause | d_mret | d_wfi; + wire [3:0] bru_bits = + d_jal + ? 4'h0 + : d_jalr + ? 4'h1 + : d_beq + ? 4'h2 + : d_bne + ? 4'h3 + : d_blt + ? 4'h4 + : d_bge + ? 4'h5 + : d_bltu + ? 4'h6 + : d_bgeu + ? 4'h7 + : d_ebreak + ? 4'h8 + : d_ecall + ? 4'h9 + : d_mpause + ? 4'hA + : d_mret ? 4'hB : d_wfi ? 4'hC : 4'h0; + wire [31:0] _bru_target_T_2 = + io_inst_bits_addr + + {{12{io_inst_bits_inst[31]}}, + io_inst_bits_inst[2] + ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} + : {{8{io_inst_bits_inst[31]}}, + io_inst_bits_inst[7], + io_inst_bits_inst[30:25], + io_inst_bits_inst[11:8]}, + 1'h0}; + wire _bxx_fault_T = bruEn & bru_valid; + wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; + wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); + wire bxx_fault = + _bxx_fault_T + & (|{bru_bits == 4'h7, + bru_bits == 4'h6, + bru_bits == 4'h5, + bru_bits == 4'h4, + bru_bits == 4'h3, + bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); + wire _io_inst_ready_T_25 = jalr_fault | jal_fault; + wire csr_valid = d_csrrw | d_csrrs | d_csrrc; + wire _io_rs1Set_value_T = d_csrrw | d_csrrs; + wire csrEn = ~(_io_rs1Set_value_T | d_csrrc) | csr_valid & io_float_ready; + wire _GEN_5 = + csr_valid + & ~(io_inst_bits_inst[31:20] == 12'h1 | io_inst_bits_inst[31:20] == 12'h2 + | io_inst_bits_inst[31:20] == 12'h3 | io_inst_bits_inst[31:20] == 12'h8 + | io_inst_bits_inst[31:20] == 12'h9 | io_inst_bits_inst[31:20] == 12'hA + | io_inst_bits_inst[31:20] == 12'h300 | io_inst_bits_inst[31:20] == 12'h301 + | io_inst_bits_inst[31:20] == 12'h304 | io_inst_bits_inst[31:20] == 12'h305 + | io_inst_bits_inst[31:20] == 12'h340 | io_inst_bits_inst[31:20] == 12'h341 + | io_inst_bits_inst[31:20] == 12'h342 | io_inst_bits_inst[31:20] == 12'h343 + | io_inst_bits_inst[31:20] == 12'h7A0 | io_inst_bits_inst[31:20] == 12'h7A1 + | io_inst_bits_inst[31:20] == 12'h7A2 | io_inst_bits_inst[31:20] == 12'h7A4 + | io_inst_bits_inst[31:20] == 12'h7B0 | io_inst_bits_inst[31:20] == 12'h7B1 + | io_inst_bits_inst[31:20] == 12'h7B2 | io_inst_bits_inst[31:20] == 12'h7B3 + | io_inst_bits_inst[31:20] == 12'h7C0 | io_inst_bits_inst[31:20] == 12'h7C1 + | io_inst_bits_inst[31:20] == 12'h7C2 | io_inst_bits_inst[31:20] == 12'h7C3 + | io_inst_bits_inst[31:20] == 12'h7C4 | io_inst_bits_inst[31:20] == 12'h7C5 + | io_inst_bits_inst[31:20] == 12'h7C6 | io_inst_bits_inst[31:20] == 12'h7C7 + | io_inst_bits_inst[31:20] == 12'h7E0 | io_inst_bits_inst[31:20] == 12'h7E1 + | io_inst_bits_inst[31:20] == 12'hB00 | io_inst_bits_inst[31:20] == 12'hB02 + | io_inst_bits_inst[31:20] == 12'hB80 | io_inst_bits_inst[31:20] == 12'hB82 + | io_inst_bits_inst[31:20] == 12'hC20 | io_inst_bits_inst[31:20] == 12'hC21 + | io_inst_bits_inst[31:20] == 12'hC22 | io_inst_bits_inst[31:20] == 12'hF11 + | io_inst_bits_inst[31:20] == 12'hF12 | io_inst_bits_inst[31:20] == 12'hF13 + | io_inst_bits_inst[31:20] == 12'hF14 | io_inst_bits_inst[31:20] == 12'hFC0 + | io_inst_bits_inst[31:20] == 12'hFC4 | io_inst_bits_inst[31:20] == 12'hFC8 + | io_inst_bits_inst[31:20] == 12'hFCC | io_inst_bits_inst[31:20] == 12'hFD0 + | io_inst_bits_inst[31:20] == 12'hFD4); + wire io_csr_valid_0 = decodeEn & csr_valid & ~_GEN_5; + wire _lsu_T_7_valid = d_d_float_y & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3; + wire lsu_valid = + d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw | d_wfi | d_fencei | d_flushat + | d_flushall | _lsu_T_7_valid; + wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; + wire dvu_valid = d_div | d_divu | d_rem | d_remu; + wire _io_rs2Read_valid_T_5 = d_add | d_sub; + wire _io_rs2Read_valid_T_18 = d_min | d_minu; + wire _io_rs2Read_valid_T_37 = d_div | d_divu; + wire rdMark_valid = + alu_valid | io_csr_valid_0 | mlu_valid | dvu_valid & io_dvu_ready | lsu_valid + & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) | _rdMark_valid_T_15 | bru_valid + & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); + wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_3; + assign io_busRead_bypass_0 = + io_inst_bits_inst[31:25] == 7'h0 + & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] + ? io_inst_bits_inst[24:20] == 5'h0 + : ~(|(io_inst_bits_inst[11:7]))); + assign io_inst_ready_0 = + (~(_floatEn_T_12[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt + | d_bge | d_bltu | d_bgeu) + & (~(_floatEn_T_18[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_flushat | d_flushall | d_d_float_y + & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3 | d_auipc | d_lui) + & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_flushat | d_flushall | d_d_float_y + & _io_float_valid_T_5 | d_d_float_y & _lsu_T_3 | d_auipc | d_lui + | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli | d_srli + | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth + | d_orcb | d_rev8 | d_d_float_y) & bruEn + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw + | d_flushat | d_flushall | d_d_float_y & _io_float_valid_T_5 | d_d_float_y + & _lsu_T_3) | io_lsu_ready + & ~((io_busRead_bypass_0 ? _floatEn_T_18[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] + & (_io_rs2Read_valid_T_24 | d_sw))) & (~dvu_valid | io_dvu_ready) + & ~((_io_serializeOut_fence_T | d_wfi | d_mpause | d_flushat | d_flushall) + & io_lsuActive) + & (~d_d_float_y | d_d_float_y & _io_float_valid_T_5 | io_float_ready & ~io_lsuActive + & ~(_rdMark_valid_T_15 & _floatEn_T_12[0]) + & ~(_io_rs1Read_valid_T_58 & _floatEn_T_18[0]) + & ~(d_d_float_y & ~d_d_float_scalar_rd & _floatEn_T_25[0]) + & ~(d_d_float_y & ~d_d_float_scalar_rs1 & _floatEn_T_32[0]) + & ~(d_d_float_y & _floatEn_T_37[0]) & ~(d_d_float_y & _floatEn_T_42[0])) & csrEn + & ~io_halted & ~io_interlock & ~(_io_inst_ready_T_25 | _GEN_5 | bxx_fault); + assign io_inst_ready = io_inst_ready_0; + assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; + assign io_rs1Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol + | d_ror | _io_rs1Set_value_T | d_csrrc | _io_rs2Read_valid_T_33 | d_mulhsu + | d_mulhu | _io_rs2Read_valid_T_37 | d_rem | d_remu | d_slog | d_jalr + | _io_rs1Read_valid_T_58); + assign io_rs1Read_addr = + io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; + assign io_rs1Set_valid = + decodeEn & (d_auipc | (_io_rs1Set_value_T | d_csrrc) & io_inst_bits_inst[14]); + assign io_rs1Set_value = _io_rs1Set_value_T | d_csrrc ? d_immcsr : io_inst_bits_addr; + assign io_rs2Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror + | _io_rs2Read_valid_T_24 | d_sw | (_io_rs1Set_value_T | d_csrrc) + & ~(io_inst_bits_inst[14]) | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu + | _io_rs2Read_valid_T_37 | d_rem | d_remu | d_slog); + assign io_rs2Read_addr = io_inst_bits_inst[24:20]; + assign io_rs2Set_valid = + decodeEn + & (d_auipc | (_io_rs1Set_value_T | d_csrrc) & io_inst_bits_inst[14] + | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli | d_srli + | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth + | d_orcb | d_rev8 | d_lui); + assign io_rs2Set_value = + d_auipc | d_lui + ? {io_inst_bits_inst[31:12], 12'h0} + : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; + assign io_rdMark_valid = decodeEn & rdMark_valid; + assign io_rdMark_addr = io_inst_bits_inst[11:7]; + assign io_rdMark_flt_valid = + decodeEn & d_d_float_y & ~d_d_float_scalar_rd & d_d_float_opcode_bits != 3'h1; + assign io_rdMark_flt_addr = io_inst_bits_inst[11:7]; + assign io_busRead_bypass = io_busRead_bypass_0; + assign io_busRead_immen = ~d_flushat; + assign io_busRead_immed = + {_d_d_imm12_T_1, + io_inst_bits_inst[31:25], + io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) + ? io_inst_bits_inst[11:7] + : io_inst_bits_inst[24:20]}; + assign io_jalFault = jal_fault; + assign io_jalrFault = jalr_fault; + assign io_bxxFault = bxx_fault; + assign io_undefFault = io_inst_valid & d_undef; + assign io_bruTarget = _bru_target_T_2; + assign io_alu_valid = decodeEn & alu_valid; + assign io_alu_bits_addr = io_inst_bits_inst[11:7]; + assign io_alu_bits_op = + _alu_T_1 + ? 5'h0 + : d_sub + ? 5'h1 + : _alu_T_2 + ? 5'h2 + : _alu_T_3 + ? 5'h3 + : _alu_T_4 + ? 5'h4 + : _alu_T_5 + ? 5'h5 + : _alu_T_6 + ? 5'h6 + : _alu_T_7 + ? 5'h7 + : _alu_T_8 + ? 5'h8 + : _alu_T_9 + ? 5'h9 + : d_lui + ? 5'hA + : d_andn + ? 5'hB + : d_orn + ? 5'hC + : d_xnor + ? 5'hD + : d_clz + ? 5'hE + : d_ctz + ? 5'hF + : d_cpop + ? 5'h10 + : d_max + ? 5'h11 + : d_maxu + ? 5'h12 + : d_min + ? 5'h13 + : d_minu + ? 5'h14 + : d_sextb + ? 5'h15 + : d_sexth + ? 5'h16 + : d_rol + ? 5'h17 + : d_ror + ? 5'h18 + : d_orcb + ? 5'h19 + : d_rev8 + ? 5'h1A + : d_zexth + ? 5'h1B + : d_rori + ? 5'h18 + : 5'h0; + assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_25 | bxx_fault); + assign io_bru_bits_fwd = io_inst_bits_brchFwd; + assign io_bru_bits_op = bru_bits; + assign io_bru_bits_pc = io_inst_bits_addr; + assign io_bru_bits_target = _bru_target_T_2; + assign io_bru_bits_link = io_inst_bits_inst[11:7]; + assign io_csr_valid = io_csr_valid_0; + assign io_csr_bits_addr = io_inst_bits_inst[11:7]; + assign io_csr_bits_index = io_inst_bits_inst[31:20]; + assign io_csr_bits_op = d_csrrw ? 2'h0 : d_csrrs ? 2'h1 : {d_csrrc, 1'h0}; + assign io_csrFault = csrEn & _GEN_5; + assign io_lsu_valid = decodeEn & lsu_valid; + assign io_lsu_bits_store = io_inst_bits_inst[5]; + assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; + assign io_lsu_bits_op = + d_lb + ? 5'h0 + : d_lh + ? 5'h1 + : d_lw + ? 5'h2 + : d_lbu + ? 5'h3 + : d_lhu + ? 5'h4 + : d_sb + ? 5'h5 + : d_sh + ? 5'h6 + : d_sw + ? 5'h7 + : d_wfi | d_fencei + ? 5'h8 + : d_flushat + ? 5'h9 + : d_flushall + ? 5'hA + : _lsu_T_7_valid ? 5'hC : 5'h0; + assign io_lsu_bits_pc = io_inst_bits_addr; + assign io_mlu_valid = decodeEn & mlu_valid; + assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; + assign io_mlu_bits_op = + d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; + assign io_dvu_valid = decodeEn & dvu_valid; + assign io_dvu_bits_addr = io_inst_bits_inst[11:7]; + assign io_dvu_bits_op = d_div ? 2'h0 : d_divu ? 2'h1 : d_rem ? 2'h2 : {2{d_remu}}; + assign io_float_valid = decodeEn & d_d_float_y & ~(d_d_float_y & _io_float_valid_T_5); + assign io_float_bits_opcode = d_d_float_opcode_bits; + assign io_float_bits_funct5 = io_inst_bits_inst[31:27]; + assign io_float_bits_rs3 = io_inst_bits_inst[31:27]; + assign io_float_bits_rs2 = io_inst_bits_inst[24:20]; + assign io_float_bits_rs1 = io_inst_bits_inst[19:15]; + assign io_float_bits_rm = io_inst_bits_inst[14:12]; + assign io_float_bits_inst = io_inst_bits_inst; + assign io_float_bits_pc = io_inst_bits_addr; + assign io_float_bits_scalar_rd = d_d_float_scalar_rd; + assign io_float_bits_scalar_rs1 = d_d_float_scalar_rs1; + assign io_float_bits_rd = io_inst_bits_inst[11:7]; + assign io_float_bits_uses_rs3 = + |{d_d_float_opcode_bits == 3'h6, + d_d_float_opcode_bits == 3'h5, + d_d_float_opcode_bits == 3'h4, + d_d_float_opcode_bits == 3'h3}; + assign io_float_bits_uses_rs2 = + _d_d_float_T_1 | _d_d_float_uses_rs2_T_2 + & ~(io_inst_bits_inst[31:27] == 5'hB | _d_d_float_uses_rs2_T_11 + | _d_d_float_uses_rs2_T_9 | _d_d_float_uses_rs2_T_7 | _d_d_float_uses_rs2_T_5) + & io_inst_bits_inst[31:27] != 5'h1C; + assign io_serializeOut_mul = mlu_valid; + assign io_serializeOut_jump = d_jal | d_jalr | d_ebreak | d_ecall | d_mpause | d_mret; + assign io_serializeOut_brcond = d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + assign io_serializeOut_wfi = d_wfi; + assign io_serializeOut_fence = + _io_serializeOut_fence_T | d_wfi | d_mpause | d_flushat | d_flushall; + assign io_serializeOut_csr = d_csrrw | d_csrrs | d_csrrc; + assign io_serializeOut_undef = d_undef; + assign io_slog = decodeEn & d_slog; +endmodule + +module Decode_1( + input io_halted, + output io_inst_ready, + input io_inst_valid, + input [31:0] io_inst_bits_addr, + io_inst_bits_inst, + input io_inst_bits_brchFwd, + input [31:0] io_scoreboard_regd, + io_scoreboard_comb, + output [31:0] io_scoreboard_spec, + output io_rs1Read_valid, + output [4:0] io_rs1Read_addr, + output io_rs1Set_valid, + output [31:0] io_rs1Set_value, + output io_rs2Read_valid, + output [4:0] io_rs2Read_addr, + output io_rs2Set_valid, + output [31:0] io_rs2Set_value, + output io_rdMark_valid, + output [4:0] io_rdMark_addr, + output io_busRead_bypass, + output [31:0] io_busRead_immed, + output io_jalFault, + io_jalrFault, + io_bxxFault, + output [31:0] io_bruTarget, + input [31:0] io_jalrTarget_data, + output io_alu_valid, + output [4:0] io_alu_bits_addr, + io_alu_bits_op, + output io_bru_valid, + io_bru_bits_fwd, + output [3:0] io_bru_bits_op, + output [31:0] io_bru_bits_pc, + io_bru_bits_target, + output [4:0] io_bru_bits_link, + input io_lsu_ready, + output io_lsu_valid, + io_lsu_bits_store, + output [4:0] io_lsu_bits_addr, + io_lsu_bits_op, + output [31:0] io_lsu_bits_pc, + output io_mlu_valid, + output [4:0] io_mlu_bits_addr, + output [2:0] io_mlu_bits_op, + input io_branchTaken, + io_interlock, + io_serializeIn_mul, + io_serializeIn_jump, + io_serializeIn_brcond, + io_serializeIn_wfi, + io_serializeIn_fence, + io_serializeIn_csr, + io_serializeIn_undef, + output io_serializeOut_mul, + io_serializeOut_jump, + io_serializeOut_brcond, + io_serializeOut_wfi, + io_serializeOut_fence, + io_serializeOut_csr, + io_serializeOut_undef +); + + wire io_inst_ready_0; + wire io_busRead_bypass_0; + wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; + wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; + wire d_lui = io_inst_bits_inst[6:0] == 7'h37; + wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; + wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; + wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_jalr = _GEN == 10'h67; + wire d_beq = _GEN == 10'h63; + wire d_bne = _GEN == 10'hE3; + wire d_blt = _GEN == 10'h263; + wire d_bge = _GEN == 10'h2E3; + wire d_bltu = _GEN == 10'h363; + wire d_bgeu = _GEN == 10'h3E3; + wire d_lb = _GEN == 10'h3; + wire d_lh = _GEN == 10'h83; + wire d_lw = _GEN == 10'h103; + wire d_lbu = _GEN == 10'h203; + wire d_lhu = _GEN == 10'h283; + wire d_sb = _GEN == 10'h23; + wire d_sh = _GEN == 10'hA3; + wire d_sw = _GEN == 10'h123; + wire d_addi = _GEN == 10'h13; + wire d_slti = _GEN == 10'h113; + wire d_sltiu = _GEN == 10'h193; + wire d_xori = _GEN == 10'h213; + wire d_ori = _GEN == 10'h313; + wire d_andi = _GEN == 10'h393; + wire [16:0] _GEN_0 = + {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_slli = _GEN_0 == 17'h93; + wire d_srli = _GEN_0 == 17'h293; + wire d_srai = _GEN_0 == 17'h8293; + wire d_add = _GEN_0 == 17'h33; + wire d_sub = _GEN_0 == 17'h8033; + wire d_slt = _GEN_0 == 17'h133; + wire d_sltu = _GEN_0 == 17'h1B3; + wire d_xor = _GEN_0 == 17'h233; + wire d_or = _GEN_0 == 17'h333; + wire d_and = _GEN_0 == 17'h3B3; + wire d_sll = _GEN_0 == 17'hB3; + wire d_srl = _GEN_0 == 17'h2B3; + wire d_sra = _GEN_0 == 17'h82B3; + wire d_mul = _GEN_0 == 17'h433; + wire d_mulh = _GEN_0 == 17'h4B3; + wire d_mulhsu = _GEN_0 == 17'h533; + wire d_mulhu = _GEN_0 == 17'h5B3; + wire d_andn = _GEN_0 == 17'h83B3; + wire d_orn = _GEN_0 == 17'h8333; + wire d_xnor = _GEN_0 == 17'h8233; + wire [21:0] _GEN_1 = + {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_clz = _GEN_1 == 22'h180093; + wire d_ctz = _GEN_1 == 22'h180493; + wire d_cpop = _GEN_1 == 22'h180893; + wire d_max = _GEN_0 == 17'h1733; + wire d_maxu = _GEN_0 == 17'h17B3; + wire d_min = _GEN_0 == 17'h1633; + wire d_minu = _GEN_0 == 17'h16B3; + wire d_sextb = _GEN_1 == 22'h181093; + wire d_sexth = _GEN_1 == 22'h181493; + wire d_rol = _GEN_0 == 17'hC0B3; + wire d_ror = _GEN_0 == 17'hC2B3; + wire d_orcb = _GEN_1 == 22'hA1E93; + wire d_rev8 = _GEN_1 == 22'h1A6293; + wire d_zexth = _GEN_1 == 22'h20233; + wire d_rori = _GEN_0 == 17'hC293; + wire d_undef = + {d_lui, + d_auipc, + d_jal, + d_jalr, + d_beq, + d_bne, + d_blt, + d_bge, + d_bltu, + d_bgeu, + d_lb, + d_lh, + d_lw, + d_lbu, + d_lhu, + d_sb, + d_sh, + d_sw, + d_addi, + d_slti, + d_sltiu, + d_xori, + d_ori, + d_andi, + d_add, + d_sub, + d_slt, + d_sltu, + d_xor, + d_or, + d_and, + d_xnor, + d_orn, + d_andn, + d_slli, + d_srli, + d_srai, + d_sll, + d_srl, + d_sra, + d_mul, + d_mulh, + d_mulhsu, + d_mulhu, + d_clz, + d_ctz, + d_cpop, + d_min, + d_minu, + d_max, + d_maxu, + d_sextb, + d_sexth, + d_zexth, + d_rol, + d_ror, + d_orcb, + d_rev8, + d_rori} == 59'h0; + wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[11:7]}; + wire [31:0] _aluRdEn_T = io_scoreboard_comb >> _GEN_2; + wire _io_rs2Read_valid_T_24 = d_sb | d_sh; + wire _io_rs2Read_valid_T = d_beq | d_bne; + wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[19:15]}; + wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_3; + wire _rdMark_valid_T_5 = d_lb | d_lh; + wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; + wire _io_rs2Set_valid_T_5 = d_addi | d_slti; + wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; + wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_3; + wire bruEn = + ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 + & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; + wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; + wire _alu_T_1 = d_auipc | d_addi | d_add; + wire _alu_T_2 = d_slti | d_slt; + wire _alu_T_3 = d_sltiu | d_sltu; + wire _alu_T_4 = d_xori | d_xor; + wire _alu_T_5 = d_ori | d_or; + wire _alu_T_6 = d_andi | d_and; + wire _alu_T_7 = d_slli | d_sll; + wire _alu_T_8 = d_srli | d_srl; + wire _alu_T_9 = d_srai | d_sra; + wire alu_valid = + _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 + | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop + | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb + | d_rev8 | d_zexth | d_rori; + wire bru_valid = + d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + wire [3:0] bru_bits = + d_jal + ? 4'h0 + : d_jalr + ? 4'h1 + : d_beq + ? 4'h2 + : d_bne + ? 4'h3 + : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; + wire [31:0] _bru_target_T_2 = + io_inst_bits_addr + + {{12{io_inst_bits_inst[31]}}, + io_inst_bits_inst[2] + ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} + : {{8{io_inst_bits_inst[31]}}, + io_inst_bits_inst[7], + io_inst_bits_inst[30:25], + io_inst_bits_inst[11:8]}, + 1'h0}; + wire _bxx_fault_T = bruEn & bru_valid; + wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; + wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); + wire bxx_fault = + _bxx_fault_T + & (|{bru_bits == 4'h7, + bru_bits == 4'h6, + bru_bits == 4'h5, + bru_bits == 4'h4, + bru_bits == 4'h3, + bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); + wire _io_inst_ready_T_26 = jalr_fault | jal_fault; + wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; + wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; + wire _io_rs2Read_valid_T_5 = d_add | d_sub; + wire _io_rs2Read_valid_T_18 = d_min | d_minu; + wire rdMark_valid = + alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) + | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); + wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_2; + assign io_busRead_bypass_0 = + io_inst_bits_inst[31:25] == 7'h0 + & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] + ? io_inst_bits_inst[24:20] == 5'h0 + : ~(|(io_inst_bits_inst[11:7]))); + assign io_inst_ready_0 = + (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt + | d_bge | d_bltu | d_bgeu) + & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) + & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu + | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori + | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) + & bruEn + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | io_lsu_ready + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | ~io_serializeIn_brcond) + & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] + & (_io_rs2Read_valid_T_24 | d_sw))) + & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) + & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump + & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted + & ~io_interlock & ~d_undef & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_inst_ready = io_inst_ready_0; + assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; + assign io_rs1Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol + | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); + assign io_rs1Read_addr = + io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; + assign io_rs1Set_valid = decodeEn & d_auipc; + assign io_rs1Set_value = io_inst_bits_addr; + assign io_rs2Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror + | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); + assign io_rs2Read_addr = io_inst_bits_inst[24:20]; + assign io_rs2Set_valid = + decodeEn + & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | d_lui); + assign io_rs2Set_value = + d_auipc | d_lui + ? {io_inst_bits_inst[31:12], 12'h0} + : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; + assign io_rdMark_valid = decodeEn & rdMark_valid; + assign io_rdMark_addr = io_inst_bits_inst[11:7]; + assign io_busRead_bypass = io_busRead_bypass_0; + assign io_busRead_immed = + {_d_d_imm12_T_1, + io_inst_bits_inst[31:25], + io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) + ? io_inst_bits_inst[11:7] + : io_inst_bits_inst[24:20]}; + assign io_jalFault = jal_fault; + assign io_jalrFault = jalr_fault; + assign io_bxxFault = bxx_fault; + assign io_bruTarget = _bru_target_T_2; + assign io_alu_valid = decodeEn & alu_valid; + assign io_alu_bits_addr = io_inst_bits_inst[11:7]; + assign io_alu_bits_op = + _alu_T_1 + ? 5'h0 + : d_sub + ? 5'h1 + : _alu_T_2 + ? 5'h2 + : _alu_T_3 + ? 5'h3 + : _alu_T_4 + ? 5'h4 + : _alu_T_5 + ? 5'h5 + : _alu_T_6 + ? 5'h6 + : _alu_T_7 + ? 5'h7 + : _alu_T_8 + ? 5'h8 + : _alu_T_9 + ? 5'h9 + : d_lui + ? 5'hA + : d_andn + ? 5'hB + : d_orn + ? 5'hC + : d_xnor + ? 5'hD + : d_clz + ? 5'hE + : d_ctz + ? 5'hF + : d_cpop + ? 5'h10 + : d_max + ? 5'h11 + : d_maxu + ? 5'h12 + : d_min + ? 5'h13 + : d_minu + ? 5'h14 + : d_sextb + ? 5'h15 + : d_sexth + ? 5'h16 + : d_rol + ? 5'h17 + : d_ror + ? 5'h18 + : d_orcb + ? 5'h19 + : d_rev8 + ? 5'h1A + : d_zexth + ? 5'h1B + : d_rori + ? 5'h18 + : 5'h0; + assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_bru_bits_fwd = io_inst_bits_brchFwd; + assign io_bru_bits_op = bru_bits; + assign io_bru_bits_pc = io_inst_bits_addr; + assign io_bru_bits_target = _bru_target_T_2; + assign io_bru_bits_link = io_inst_bits_inst[11:7]; + assign io_lsu_valid = decodeEn & lsu_valid; + assign io_lsu_bits_store = io_inst_bits_inst[5]; + assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; + assign io_lsu_bits_op = + d_lb + ? 5'h0 + : d_lh + ? 5'h1 + : d_lw + ? 5'h2 + : d_lbu + ? 5'h3 + : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; + assign io_lsu_bits_pc = io_inst_bits_addr; + assign io_mlu_valid = decodeEn & mlu_valid; + assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; + assign io_mlu_bits_op = + d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; + assign io_serializeOut_mul = io_serializeIn_mul | mlu_valid; + assign io_serializeOut_jump = io_serializeIn_jump | d_jal | d_jalr; + assign io_serializeOut_brcond = + io_serializeIn_brcond | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + assign io_serializeOut_wfi = io_serializeIn_wfi; + assign io_serializeOut_fence = io_serializeIn_fence; + assign io_serializeOut_csr = io_serializeIn_csr; + assign io_serializeOut_undef = io_serializeIn_undef | d_undef; +endmodule + +module Decode_2( + input io_halted, + output io_inst_ready, + input io_inst_valid, + input [31:0] io_inst_bits_addr, + io_inst_bits_inst, + input io_inst_bits_brchFwd, + input [31:0] io_scoreboard_regd, + io_scoreboard_comb, + output [31:0] io_scoreboard_spec, + output io_rs1Read_valid, + output [4:0] io_rs1Read_addr, + output io_rs1Set_valid, + output [31:0] io_rs1Set_value, + output io_rs2Read_valid, + output [4:0] io_rs2Read_addr, + output io_rs2Set_valid, + output [31:0] io_rs2Set_value, + output io_rdMark_valid, + output [4:0] io_rdMark_addr, + output io_busRead_bypass, + output [31:0] io_busRead_immed, + output io_jalFault, + io_jalrFault, + io_bxxFault, + output [31:0] io_bruTarget, + input [31:0] io_jalrTarget_data, + output io_alu_valid, + output [4:0] io_alu_bits_addr, + io_alu_bits_op, + output io_bru_valid, + io_bru_bits_fwd, + output [3:0] io_bru_bits_op, + output [31:0] io_bru_bits_pc, + io_bru_bits_target, + output [4:0] io_bru_bits_link, + input io_lsu_ready, + output io_lsu_valid, + io_lsu_bits_store, + output [4:0] io_lsu_bits_addr, + io_lsu_bits_op, + output [31:0] io_lsu_bits_pc, + output io_mlu_valid, + output [4:0] io_mlu_bits_addr, + output [2:0] io_mlu_bits_op, + input io_branchTaken, + io_interlock, + io_serializeIn_mul, + io_serializeIn_jump, + io_serializeIn_brcond, + io_serializeIn_wfi, + io_serializeIn_fence, + io_serializeIn_csr, + io_serializeIn_undef, + output io_serializeOut_mul, + io_serializeOut_jump, + io_serializeOut_brcond, + io_serializeOut_wfi, + io_serializeOut_fence, + io_serializeOut_csr, + io_serializeOut_undef +); + + wire io_inst_ready_0; + wire io_busRead_bypass_0; + wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; + wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; + wire d_lui = io_inst_bits_inst[6:0] == 7'h37; + wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; + wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; + wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_jalr = _GEN == 10'h67; + wire d_beq = _GEN == 10'h63; + wire d_bne = _GEN == 10'hE3; + wire d_blt = _GEN == 10'h263; + wire d_bge = _GEN == 10'h2E3; + wire d_bltu = _GEN == 10'h363; + wire d_bgeu = _GEN == 10'h3E3; + wire d_lb = _GEN == 10'h3; + wire d_lh = _GEN == 10'h83; + wire d_lw = _GEN == 10'h103; + wire d_lbu = _GEN == 10'h203; + wire d_lhu = _GEN == 10'h283; + wire d_sb = _GEN == 10'h23; + wire d_sh = _GEN == 10'hA3; + wire d_sw = _GEN == 10'h123; + wire d_addi = _GEN == 10'h13; + wire d_slti = _GEN == 10'h113; + wire d_sltiu = _GEN == 10'h193; + wire d_xori = _GEN == 10'h213; + wire d_ori = _GEN == 10'h313; + wire d_andi = _GEN == 10'h393; + wire [16:0] _GEN_0 = + {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_slli = _GEN_0 == 17'h93; + wire d_srli = _GEN_0 == 17'h293; + wire d_srai = _GEN_0 == 17'h8293; + wire d_add = _GEN_0 == 17'h33; + wire d_sub = _GEN_0 == 17'h8033; + wire d_slt = _GEN_0 == 17'h133; + wire d_sltu = _GEN_0 == 17'h1B3; + wire d_xor = _GEN_0 == 17'h233; + wire d_or = _GEN_0 == 17'h333; + wire d_and = _GEN_0 == 17'h3B3; + wire d_sll = _GEN_0 == 17'hB3; + wire d_srl = _GEN_0 == 17'h2B3; + wire d_sra = _GEN_0 == 17'h82B3; + wire d_mul = _GEN_0 == 17'h433; + wire d_mulh = _GEN_0 == 17'h4B3; + wire d_mulhsu = _GEN_0 == 17'h533; + wire d_mulhu = _GEN_0 == 17'h5B3; + wire d_andn = _GEN_0 == 17'h83B3; + wire d_orn = _GEN_0 == 17'h8333; + wire d_xnor = _GEN_0 == 17'h8233; + wire [21:0] _GEN_1 = + {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_clz = _GEN_1 == 22'h180093; + wire d_ctz = _GEN_1 == 22'h180493; + wire d_cpop = _GEN_1 == 22'h180893; + wire d_max = _GEN_0 == 17'h1733; + wire d_maxu = _GEN_0 == 17'h17B3; + wire d_min = _GEN_0 == 17'h1633; + wire d_minu = _GEN_0 == 17'h16B3; + wire d_sextb = _GEN_1 == 22'h181093; + wire d_sexth = _GEN_1 == 22'h181493; + wire d_rol = _GEN_0 == 17'hC0B3; + wire d_ror = _GEN_0 == 17'hC2B3; + wire d_orcb = _GEN_1 == 22'hA1E93; + wire d_rev8 = _GEN_1 == 22'h1A6293; + wire d_zexth = _GEN_1 == 22'h20233; + wire d_rori = _GEN_0 == 17'hC293; + wire d_undef = + {d_lui, + d_auipc, + d_jal, + d_jalr, + d_beq, + d_bne, + d_blt, + d_bge, + d_bltu, + d_bgeu, + d_lb, + d_lh, + d_lw, + d_lbu, + d_lhu, + d_sb, + d_sh, + d_sw, + d_addi, + d_slti, + d_sltiu, + d_xori, + d_ori, + d_andi, + d_add, + d_sub, + d_slt, + d_sltu, + d_xor, + d_or, + d_and, + d_xnor, + d_orn, + d_andn, + d_slli, + d_srli, + d_srai, + d_sll, + d_srl, + d_sra, + d_mul, + d_mulh, + d_mulhsu, + d_mulhu, + d_clz, + d_ctz, + d_cpop, + d_min, + d_minu, + d_max, + d_maxu, + d_sextb, + d_sexth, + d_zexth, + d_rol, + d_ror, + d_orcb, + d_rev8, + d_rori} == 59'h0; + wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[11:7]}; + wire [31:0] _aluRdEn_T = io_scoreboard_comb >> _GEN_2; + wire _io_rs2Read_valid_T_24 = d_sb | d_sh; + wire _io_rs2Read_valid_T = d_beq | d_bne; + wire [31:0] _GEN_3 = {27'h0, io_inst_bits_inst[19:15]}; + wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_3; + wire _rdMark_valid_T_5 = d_lb | d_lh; + wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; + wire _io_rs2Set_valid_T_5 = d_addi | d_slti; + wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; + wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_3; + wire bruEn = + ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 + & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; + wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; + wire _alu_T_1 = d_auipc | d_addi | d_add; + wire _alu_T_2 = d_slti | d_slt; + wire _alu_T_3 = d_sltiu | d_sltu; + wire _alu_T_4 = d_xori | d_xor; + wire _alu_T_5 = d_ori | d_or; + wire _alu_T_6 = d_andi | d_and; + wire _alu_T_7 = d_slli | d_sll; + wire _alu_T_8 = d_srli | d_srl; + wire _alu_T_9 = d_srai | d_sra; + wire alu_valid = + _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 + | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop + | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb + | d_rev8 | d_zexth | d_rori; + wire bru_valid = + d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + wire [3:0] bru_bits = + d_jal + ? 4'h0 + : d_jalr + ? 4'h1 + : d_beq + ? 4'h2 + : d_bne + ? 4'h3 + : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; + wire [31:0] _bru_target_T_2 = + io_inst_bits_addr + + {{12{io_inst_bits_inst[31]}}, + io_inst_bits_inst[2] + ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} + : {{8{io_inst_bits_inst[31]}}, + io_inst_bits_inst[7], + io_inst_bits_inst[30:25], + io_inst_bits_inst[11:8]}, + 1'h0}; + wire _bxx_fault_T = bruEn & bru_valid; + wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; + wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); + wire bxx_fault = + _bxx_fault_T + & (|{bru_bits == 4'h7, + bru_bits == 4'h6, + bru_bits == 4'h5, + bru_bits == 4'h4, + bru_bits == 4'h3, + bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); + wire _io_inst_ready_T_26 = jalr_fault | jal_fault; + wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; + wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; + wire _io_rs2Read_valid_T_5 = d_add | d_sub; + wire _io_rs2Read_valid_T_18 = d_min | d_minu; + wire rdMark_valid = + alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) + | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) & (|(io_inst_bits_inst[11:7])); + wire [31:0] _scoreboard_spec_T_1 = 32'h1 << _GEN_2; + assign io_busRead_bypass_0 = + io_inst_bits_inst[31:25] == 7'h0 + & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] + ? io_inst_bits_inst[24:20] == 5'h0 + : ~(|(io_inst_bits_inst[11:7]))); + assign io_inst_ready_0 = + (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt + | d_bge | d_bltu | d_bgeu) + & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) + & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu + | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori + | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) + & bruEn + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | io_lsu_ready + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | ~io_serializeIn_brcond) + & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] + & (_io_rs2Read_valid_T_24 | d_sw))) + & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) + & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump + & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted + & ~io_interlock & ~d_undef & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_inst_ready = io_inst_ready_0; + assign io_scoreboard_spec = {rdMark_valid ? _scoreboard_spec_T_1[31:1] : 31'h0, 1'h0}; + assign io_rs1Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol + | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); + assign io_rs1Read_addr = + io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; + assign io_rs1Set_valid = decodeEn & d_auipc; + assign io_rs1Set_value = io_inst_bits_addr; + assign io_rs2Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror + | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); + assign io_rs2Read_addr = io_inst_bits_inst[24:20]; + assign io_rs2Set_valid = + decodeEn + & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | d_lui); + assign io_rs2Set_value = + d_auipc | d_lui + ? {io_inst_bits_inst[31:12], 12'h0} + : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; + assign io_rdMark_valid = decodeEn & rdMark_valid; + assign io_rdMark_addr = io_inst_bits_inst[11:7]; + assign io_busRead_bypass = io_busRead_bypass_0; + assign io_busRead_immed = + {_d_d_imm12_T_1, + io_inst_bits_inst[31:25], + io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) + ? io_inst_bits_inst[11:7] + : io_inst_bits_inst[24:20]}; + assign io_jalFault = jal_fault; + assign io_jalrFault = jalr_fault; + assign io_bxxFault = bxx_fault; + assign io_bruTarget = _bru_target_T_2; + assign io_alu_valid = decodeEn & alu_valid; + assign io_alu_bits_addr = io_inst_bits_inst[11:7]; + assign io_alu_bits_op = + _alu_T_1 + ? 5'h0 + : d_sub + ? 5'h1 + : _alu_T_2 + ? 5'h2 + : _alu_T_3 + ? 5'h3 + : _alu_T_4 + ? 5'h4 + : _alu_T_5 + ? 5'h5 + : _alu_T_6 + ? 5'h6 + : _alu_T_7 + ? 5'h7 + : _alu_T_8 + ? 5'h8 + : _alu_T_9 + ? 5'h9 + : d_lui + ? 5'hA + : d_andn + ? 5'hB + : d_orn + ? 5'hC + : d_xnor + ? 5'hD + : d_clz + ? 5'hE + : d_ctz + ? 5'hF + : d_cpop + ? 5'h10 + : d_max + ? 5'h11 + : d_maxu + ? 5'h12 + : d_min + ? 5'h13 + : d_minu + ? 5'h14 + : d_sextb + ? 5'h15 + : d_sexth + ? 5'h16 + : d_rol + ? 5'h17 + : d_ror + ? 5'h18 + : d_orcb + ? 5'h19 + : d_rev8 + ? 5'h1A + : d_zexth + ? 5'h1B + : d_rori + ? 5'h18 + : 5'h0; + assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_bru_bits_fwd = io_inst_bits_brchFwd; + assign io_bru_bits_op = bru_bits; + assign io_bru_bits_pc = io_inst_bits_addr; + assign io_bru_bits_target = _bru_target_T_2; + assign io_bru_bits_link = io_inst_bits_inst[11:7]; + assign io_lsu_valid = decodeEn & lsu_valid; + assign io_lsu_bits_store = io_inst_bits_inst[5]; + assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; + assign io_lsu_bits_op = + d_lb + ? 5'h0 + : d_lh + ? 5'h1 + : d_lw + ? 5'h2 + : d_lbu + ? 5'h3 + : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; + assign io_lsu_bits_pc = io_inst_bits_addr; + assign io_mlu_valid = decodeEn & mlu_valid; + assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; + assign io_mlu_bits_op = + d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; + assign io_serializeOut_mul = io_serializeIn_mul | mlu_valid; + assign io_serializeOut_jump = io_serializeIn_jump | d_jal | d_jalr; + assign io_serializeOut_brcond = + io_serializeIn_brcond | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + assign io_serializeOut_wfi = io_serializeIn_wfi; + assign io_serializeOut_fence = io_serializeIn_fence; + assign io_serializeOut_csr = io_serializeIn_csr; + assign io_serializeOut_undef = io_serializeIn_undef | d_undef; +endmodule + +module Decode_3( + input io_halted, + output io_inst_ready, + input io_inst_valid, + input [31:0] io_inst_bits_addr, + io_inst_bits_inst, + input io_inst_bits_brchFwd, + input [31:0] io_scoreboard_regd, + io_scoreboard_comb, + output io_rs1Read_valid, + output [4:0] io_rs1Read_addr, + output io_rs1Set_valid, + output [31:0] io_rs1Set_value, + output io_rs2Read_valid, + output [4:0] io_rs2Read_addr, + output io_rs2Set_valid, + output [31:0] io_rs2Set_value, + output io_rdMark_valid, + output [4:0] io_rdMark_addr, + output io_busRead_bypass, + output [31:0] io_busRead_immed, + output io_jalFault, + io_jalrFault, + io_bxxFault, + output [31:0] io_bruTarget, + input [31:0] io_jalrTarget_data, + output io_alu_valid, + output [4:0] io_alu_bits_addr, + io_alu_bits_op, + output io_bru_valid, + io_bru_bits_fwd, + output [3:0] io_bru_bits_op, + output [31:0] io_bru_bits_pc, + io_bru_bits_target, + output [4:0] io_bru_bits_link, + input io_lsu_ready, + output io_lsu_valid, + io_lsu_bits_store, + output [4:0] io_lsu_bits_addr, + io_lsu_bits_op, + output [31:0] io_lsu_bits_pc, + output io_mlu_valid, + output [4:0] io_mlu_bits_addr, + output [2:0] io_mlu_bits_op, + input io_branchTaken, + io_interlock, + io_serializeIn_mul, + io_serializeIn_jump, + io_serializeIn_brcond, + io_serializeIn_wfi, + io_serializeIn_fence, + io_serializeIn_csr, + io_serializeIn_undef +); + + wire io_inst_ready_0; + wire io_busRead_bypass_0; + wire decodeEn = io_inst_valid & io_inst_ready_0 & ~io_branchTaken; + wire [19:0] _d_d_imm12_T_1 = {20{io_inst_bits_inst[31]}}; + wire d_lui = io_inst_bits_inst[6:0] == 7'h37; + wire d_auipc = io_inst_bits_inst[6:0] == 7'h17; + wire d_jal = io_inst_bits_inst[6:0] == 7'h6F; + wire [9:0] _GEN = {io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_jalr = _GEN == 10'h67; + wire d_beq = _GEN == 10'h63; + wire d_bne = _GEN == 10'hE3; + wire d_blt = _GEN == 10'h263; + wire d_bge = _GEN == 10'h2E3; + wire d_bltu = _GEN == 10'h363; + wire d_bgeu = _GEN == 10'h3E3; + wire d_lb = _GEN == 10'h3; + wire d_lh = _GEN == 10'h83; + wire d_lw = _GEN == 10'h103; + wire d_lbu = _GEN == 10'h203; + wire d_lhu = _GEN == 10'h283; + wire d_sb = _GEN == 10'h23; + wire d_sh = _GEN == 10'hA3; + wire d_sw = _GEN == 10'h123; + wire d_addi = _GEN == 10'h13; + wire d_slti = _GEN == 10'h113; + wire d_sltiu = _GEN == 10'h193; + wire d_xori = _GEN == 10'h213; + wire d_ori = _GEN == 10'h313; + wire d_andi = _GEN == 10'h393; + wire [16:0] _GEN_0 = + {io_inst_bits_inst[31:25], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_slli = _GEN_0 == 17'h93; + wire d_srli = _GEN_0 == 17'h293; + wire d_srai = _GEN_0 == 17'h8293; + wire d_add = _GEN_0 == 17'h33; + wire d_sub = _GEN_0 == 17'h8033; + wire d_slt = _GEN_0 == 17'h133; + wire d_sltu = _GEN_0 == 17'h1B3; + wire d_xor = _GEN_0 == 17'h233; + wire d_or = _GEN_0 == 17'h333; + wire d_and = _GEN_0 == 17'h3B3; + wire d_sll = _GEN_0 == 17'hB3; + wire d_srl = _GEN_0 == 17'h2B3; + wire d_sra = _GEN_0 == 17'h82B3; + wire d_mul = _GEN_0 == 17'h433; + wire d_mulh = _GEN_0 == 17'h4B3; + wire d_mulhsu = _GEN_0 == 17'h533; + wire d_mulhu = _GEN_0 == 17'h5B3; + wire d_andn = _GEN_0 == 17'h83B3; + wire d_orn = _GEN_0 == 17'h8333; + wire d_xnor = _GEN_0 == 17'h8233; + wire [21:0] _GEN_1 = + {io_inst_bits_inst[31:20], io_inst_bits_inst[14:12], io_inst_bits_inst[6:0]}; + wire d_clz = _GEN_1 == 22'h180093; + wire d_ctz = _GEN_1 == 22'h180493; + wire d_cpop = _GEN_1 == 22'h180893; + wire d_max = _GEN_0 == 17'h1733; + wire d_maxu = _GEN_0 == 17'h17B3; + wire d_min = _GEN_0 == 17'h1633; + wire d_minu = _GEN_0 == 17'h16B3; + wire d_sextb = _GEN_1 == 22'h181093; + wire d_sexth = _GEN_1 == 22'h181493; + wire d_rol = _GEN_0 == 17'hC0B3; + wire d_ror = _GEN_0 == 17'hC2B3; + wire d_orcb = _GEN_1 == 22'hA1E93; + wire d_rev8 = _GEN_1 == 22'h1A6293; + wire d_zexth = _GEN_1 == 22'h20233; + wire d_rori = _GEN_0 == 17'hC293; + wire [31:0] _aluRdEn_T = io_scoreboard_comb >> io_inst_bits_inst[11:7]; + wire _io_rs2Read_valid_T_24 = d_sb | d_sh; + wire _io_rs2Read_valid_T = d_beq | d_bne; + wire [31:0] _GEN_2 = {27'h0, io_inst_bits_inst[19:15]}; + wire [31:0] _lsuEn_T_43 = io_scoreboard_comb >> _GEN_2; + wire _rdMark_valid_T_5 = d_lb | d_lh; + wire [31:0] _lsuEn_T_48 = io_scoreboard_comb >> io_inst_bits_inst[24:20]; + wire _io_rs2Set_valid_T_5 = d_addi | d_slti; + wire _io_rs2Set_valid_T_15 = d_clz | d_ctz; + wire [31:0] _lsuEn_T_45 = io_scoreboard_regd >> _GEN_2; + wire bruEn = + ~d_jalr | ~(_lsuEn_T_45[0]) | io_inst_bits_inst[31:20] == 12'h0 + & ~(|(io_inst_bits_inst[11:7])) & io_inst_bits_inst[19:15] == 5'h1; + wire _io_rs2Read_valid_T_33 = d_mul | d_mulh; + wire _alu_T_1 = d_auipc | d_addi | d_add; + wire _alu_T_2 = d_slti | d_slt; + wire _alu_T_3 = d_sltiu | d_sltu; + wire _alu_T_4 = d_xori | d_xor; + wire _alu_T_5 = d_ori | d_or; + wire _alu_T_6 = d_andi | d_and; + wire _alu_T_7 = d_slli | d_sll; + wire _alu_T_8 = d_srli | d_srl; + wire _alu_T_9 = d_srai | d_sra; + wire alu_valid = + _alu_T_1 | d_sub | _alu_T_2 | _alu_T_3 | _alu_T_4 | _alu_T_5 | _alu_T_6 | _alu_T_7 + | _alu_T_8 | _alu_T_9 | d_lui | d_andn | d_orn | d_xnor | d_clz | d_ctz | d_cpop + | d_max | d_maxu | d_min | d_minu | d_sextb | d_sexth | d_rol | d_ror | d_orcb + | d_rev8 | d_zexth | d_rori; + wire bru_valid = + d_jal | d_jalr | d_beq | d_bne | d_blt | d_bge | d_bltu | d_bgeu; + wire [3:0] bru_bits = + d_jal + ? 4'h0 + : d_jalr + ? 4'h1 + : d_beq + ? 4'h2 + : d_bne + ? 4'h3 + : d_blt ? 4'h4 : d_bge ? 4'h5 : d_bltu ? 4'h6 : d_bgeu ? 4'h7 : 4'h0; + wire [31:0] _bru_target_T_2 = + io_inst_bits_addr + + {{12{io_inst_bits_inst[31]}}, + io_inst_bits_inst[2] + ? {io_inst_bits_inst[19:12], io_inst_bits_inst[20], io_inst_bits_inst[30:21]} + : {{8{io_inst_bits_inst[31]}}, + io_inst_bits_inst[7], + io_inst_bits_inst[30:25], + io_inst_bits_inst[11:8]}, + 1'h0}; + wire _bxx_fault_T = bruEn & bru_valid; + wire jalr_fault = _bxx_fault_T & bru_bits == 4'h1 & io_jalrTarget_data[1]; + wire jal_fault = _bxx_fault_T & bru_bits == 4'h0 & (|(_bru_target_T_2[1:0])); + wire bxx_fault = + _bxx_fault_T + & (|{bru_bits == 4'h7, + bru_bits == 4'h6, + bru_bits == 4'h5, + bru_bits == 4'h4, + bru_bits == 4'h3, + bru_bits == 4'h2}) & (|(_bru_target_T_2[1:0])); + wire _io_inst_ready_T_26 = jalr_fault | jal_fault; + wire lsu_valid = d_lb | d_lh | d_lw | d_lbu | d_lhu | d_sb | d_sh | d_sw; + wire mlu_valid = d_mul | d_mulh | d_mulhsu | d_mulhu; + wire _io_rs2Read_valid_T_5 = d_add | d_sub; + wire _io_rs2Read_valid_T_18 = d_min | d_minu; + assign io_busRead_bypass_0 = + io_inst_bits_inst[31:25] == 7'h0 + & (~(io_inst_bits_inst[5]) | io_inst_bits_inst[6] + ? io_inst_bits_inst[24:20] == 5'h0 + : ~(|(io_inst_bits_inst[11:7]))); + assign io_inst_ready_0 = + (~(_aluRdEn_T[0]) | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T | d_blt + | d_bge | d_bltu | d_bgeu) + & (~(_lsuEn_T_43[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui) + & (~(_lsuEn_T_48[0]) | _rdMark_valid_T_5 | d_lw | d_lbu | d_lhu + | _io_rs2Read_valid_T_24 | d_sw | d_auipc | d_lui | _io_rs2Set_valid_T_5 | d_sltiu + | d_xori | d_ori | d_andi | d_slli | d_srli | d_srai | d_rori + | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth | d_zexth | d_orcb | d_rev8) + & bruEn + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | io_lsu_ready + & (~(_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu | _io_rs2Read_valid_T_24 | d_sw) + | ~io_serializeIn_brcond) + & ~((io_busRead_bypass_0 ? _lsuEn_T_43[0] : _lsuEn_T_45[0]) | _lsuEn_T_48[0] + & (_io_rs2Read_valid_T_24 | d_sw))) + & (~(_io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu) | ~io_serializeIn_mul) + & ~io_serializeIn_brcond & ~io_serializeIn_fence & ~io_serializeIn_jump + & ~io_serializeIn_wfi & ~io_serializeIn_undef & ~io_serializeIn_csr & ~io_halted + & ~io_interlock + & (|{d_lui, + d_auipc, + d_jal, + d_jalr, + d_beq, + d_bne, + d_blt, + d_bge, + d_bltu, + d_bgeu, + d_lb, + d_lh, + d_lw, + d_lbu, + d_lhu, + d_sb, + d_sh, + d_sw, + d_addi, + d_slti, + d_sltiu, + d_xori, + d_ori, + d_andi, + d_add, + d_sub, + d_slt, + d_sltu, + d_xor, + d_or, + d_and, + d_xnor, + d_orn, + d_andn, + d_slli, + d_srli, + d_srai, + d_sll, + d_srl, + d_sra, + d_mul, + d_mulh, + d_mulhsu, + d_mulhu, + d_clz, + d_ctz, + d_cpop, + d_min, + d_minu, + d_max, + d_maxu, + d_sextb, + d_sexth, + d_zexth, + d_rol, + d_ror, + d_orcb, + d_rev8, + d_rori}) & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_inst_ready = io_inst_ready_0; + assign io_rs1Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol + | d_ror | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu | d_jalr); + assign io_rs1Read_addr = + io_inst_bits_inst[0] ? io_inst_bits_inst[19:15] : io_inst_bits_inst[31:27]; + assign io_rs1Set_valid = decodeEn & d_auipc; + assign io_rs1Set_value = io_inst_bits_addr; + assign io_rs2Read_valid = + decodeEn + & (_io_rs2Read_valid_T | d_blt | d_bge | d_bltu | d_bgeu | _io_rs2Read_valid_T_5 + | d_slt | d_sltu | d_xor | d_or | d_and | d_xnor | d_orn | d_andn | d_sll | d_srl + | d_sra | _io_rs2Read_valid_T_18 | d_max | d_maxu | d_rol | d_ror + | _io_rs2Read_valid_T_24 | d_sw | _io_rs2Read_valid_T_33 | d_mulhsu | d_mulhu); + assign io_rs2Read_addr = io_inst_bits_inst[24:20]; + assign io_rs2Set_valid = + decodeEn + & (d_auipc | _io_rs2Set_valid_T_5 | d_sltiu | d_xori | d_ori | d_andi | d_slli + | d_srli | d_srai | d_rori | _io_rs2Set_valid_T_15 | d_cpop | d_sextb | d_sexth + | d_zexth | d_orcb | d_rev8 | d_lui); + assign io_rs2Set_value = + d_auipc | d_lui + ? {io_inst_bits_inst[31:12], 12'h0} + : {_d_d_imm12_T_1, io_inst_bits_inst[31:20]}; + assign io_rdMark_valid = + decodeEn + & (alu_valid | mlu_valid | lsu_valid & (_rdMark_valid_T_5 | d_lw | d_lbu | d_lhu) + | bru_valid & (|{bru_bits == 4'h1, bru_bits == 4'h0}) + & (|(io_inst_bits_inst[11:7]))); + assign io_rdMark_addr = io_inst_bits_inst[11:7]; + assign io_busRead_bypass = io_busRead_bypass_0; + assign io_busRead_immed = + {_d_d_imm12_T_1, + io_inst_bits_inst[31:25], + io_inst_bits_inst[6:3] == 4'h4 & (&(io_inst_bits_inst[1:0])) + ? io_inst_bits_inst[11:7] + : io_inst_bits_inst[24:20]}; + assign io_jalFault = jal_fault; + assign io_jalrFault = jalr_fault; + assign io_bxxFault = bxx_fault; + assign io_bruTarget = _bru_target_T_2; + assign io_alu_valid = decodeEn & alu_valid; + assign io_alu_bits_addr = io_inst_bits_inst[11:7]; + assign io_alu_bits_op = + _alu_T_1 + ? 5'h0 + : d_sub + ? 5'h1 + : _alu_T_2 + ? 5'h2 + : _alu_T_3 + ? 5'h3 + : _alu_T_4 + ? 5'h4 + : _alu_T_5 + ? 5'h5 + : _alu_T_6 + ? 5'h6 + : _alu_T_7 + ? 5'h7 + : _alu_T_8 + ? 5'h8 + : _alu_T_9 + ? 5'h9 + : d_lui + ? 5'hA + : d_andn + ? 5'hB + : d_orn + ? 5'hC + : d_xnor + ? 5'hD + : d_clz + ? 5'hE + : d_ctz + ? 5'hF + : d_cpop + ? 5'h10 + : d_max + ? 5'h11 + : d_maxu + ? 5'h12 + : d_min + ? 5'h13 + : d_minu + ? 5'h14 + : d_sextb + ? 5'h15 + : d_sexth + ? 5'h16 + : d_rol + ? 5'h17 + : d_ror + ? 5'h18 + : d_orcb + ? 5'h19 + : d_rev8 + ? 5'h1A + : d_zexth + ? 5'h1B + : d_rori + ? 5'h18 + : 5'h0; + assign io_bru_valid = decodeEn & bru_valid & ~(_io_inst_ready_T_26 | bxx_fault); + assign io_bru_bits_fwd = io_inst_bits_brchFwd; + assign io_bru_bits_op = bru_bits; + assign io_bru_bits_pc = io_inst_bits_addr; + assign io_bru_bits_target = _bru_target_T_2; + assign io_bru_bits_link = io_inst_bits_inst[11:7]; + assign io_lsu_valid = decodeEn & lsu_valid; + assign io_lsu_bits_store = io_inst_bits_inst[5]; + assign io_lsu_bits_addr = io_inst_bits_inst[11:7]; + assign io_lsu_bits_op = + d_lb + ? 5'h0 + : d_lh + ? 5'h1 + : d_lw + ? 5'h2 + : d_lbu + ? 5'h3 + : d_lhu ? 5'h4 : d_sb ? 5'h5 : d_sh ? 5'h6 : d_sw ? 5'h7 : 5'h0; + assign io_lsu_bits_pc = io_inst_bits_addr; + assign io_mlu_valid = decodeEn & mlu_valid; + assign io_mlu_bits_addr = io_inst_bits_inst[11:7]; + assign io_mlu_bits_op = + d_mul ? 3'h0 : d_mulh ? 3'h1 : d_mulhsu ? 3'h2 : d_mulhu ? 3'h3 : 3'h0; +endmodule + +module DispatchV1( + input io_halted, + io_lsuActive, + input [31:0] io_scoreboard_regd, + io_scoreboard_comb, + io_fscoreboard, + input io_branchTaken, + output io_csrFault_0, + io_jalFault_0, + io_jalFault_1, + io_jalFault_2, + io_jalFault_3, + io_jalrFault_0, + io_jalrFault_1, + io_jalrFault_2, + io_jalrFault_3, + io_bxxFault_0, + io_bxxFault_1, + io_bxxFault_2, + io_bxxFault_3, + io_undefFault_0, + output [31:0] io_bruTarget_0, + io_bruTarget_1, + io_bruTarget_2, + io_bruTarget_3, + input [31:0] io_jalrTarget_0_data, + io_jalrTarget_1_data, + io_jalrTarget_2_data, + io_jalrTarget_3_data, + input io_interlock, + output io_inst_0_ready, + input io_inst_0_valid, + input [31:0] io_inst_0_bits_addr, + io_inst_0_bits_inst, + input io_inst_0_bits_brchFwd, + output io_inst_1_ready, + input io_inst_1_valid, + input [31:0] io_inst_1_bits_addr, + io_inst_1_bits_inst, + input io_inst_1_bits_brchFwd, + output io_inst_2_ready, + input io_inst_2_valid, + input [31:0] io_inst_2_bits_addr, + io_inst_2_bits_inst, + input io_inst_2_bits_brchFwd, + output io_inst_3_ready, + input io_inst_3_valid, + input [31:0] io_inst_3_bits_addr, + io_inst_3_bits_inst, + input io_inst_3_bits_brchFwd, + output io_rs1Read_0_valid, + output [4:0] io_rs1Read_0_addr, + output io_rs1Read_1_valid, + output [4:0] io_rs1Read_1_addr, + output io_rs1Read_2_valid, + output [4:0] io_rs1Read_2_addr, + output io_rs1Read_3_valid, + output [4:0] io_rs1Read_3_addr, + output io_rs1Set_0_valid, + output [31:0] io_rs1Set_0_value, + output io_rs1Set_1_valid, + output [31:0] io_rs1Set_1_value, + output io_rs1Set_2_valid, + output [31:0] io_rs1Set_2_value, + output io_rs1Set_3_valid, + output [31:0] io_rs1Set_3_value, + output io_rs2Read_0_valid, + output [4:0] io_rs2Read_0_addr, + output io_rs2Read_1_valid, + output [4:0] io_rs2Read_1_addr, + output io_rs2Read_2_valid, + output [4:0] io_rs2Read_2_addr, + output io_rs2Read_3_valid, + output [4:0] io_rs2Read_3_addr, + output io_rs2Set_0_valid, + output [31:0] io_rs2Set_0_value, + output io_rs2Set_1_valid, + output [31:0] io_rs2Set_1_value, + output io_rs2Set_2_valid, + output [31:0] io_rs2Set_2_value, + output io_rs2Set_3_valid, + output [31:0] io_rs2Set_3_value, + output io_rdMark_0_valid, + output [4:0] io_rdMark_0_addr, + output io_rdMark_1_valid, + output [4:0] io_rdMark_1_addr, + output io_rdMark_2_valid, + output [4:0] io_rdMark_2_addr, + output io_rdMark_3_valid, + output [4:0] io_rdMark_3_addr, + output io_busRead_0_bypass, + io_busRead_0_immen, + output [31:0] io_busRead_0_immed, + output io_busRead_1_bypass, + output [31:0] io_busRead_1_immed, + output io_busRead_2_bypass, + output [31:0] io_busRead_2_immed, + output io_busRead_3_bypass, + output [31:0] io_busRead_3_immed, + output io_rdMark_flt_valid, + output [4:0] io_rdMark_flt_addr, + output io_alu_0_valid, + output [4:0] io_alu_0_bits_addr, + io_alu_0_bits_op, + output io_alu_1_valid, + output [4:0] io_alu_1_bits_addr, + io_alu_1_bits_op, + output io_alu_2_valid, + output [4:0] io_alu_2_bits_addr, + io_alu_2_bits_op, + output io_alu_3_valid, + output [4:0] io_alu_3_bits_addr, + io_alu_3_bits_op, + output io_bru_0_valid, + io_bru_0_bits_fwd, + output [3:0] io_bru_0_bits_op, + output [31:0] io_bru_0_bits_pc, + io_bru_0_bits_target, + output [4:0] io_bru_0_bits_link, + output io_bru_1_valid, + io_bru_1_bits_fwd, + output [3:0] io_bru_1_bits_op, + output [31:0] io_bru_1_bits_pc, + io_bru_1_bits_target, + output [4:0] io_bru_1_bits_link, + output io_bru_2_valid, + io_bru_2_bits_fwd, + output [3:0] io_bru_2_bits_op, + output [31:0] io_bru_2_bits_pc, + io_bru_2_bits_target, + output [4:0] io_bru_2_bits_link, + output io_bru_3_valid, + io_bru_3_bits_fwd, + output [3:0] io_bru_3_bits_op, + output [31:0] io_bru_3_bits_pc, + io_bru_3_bits_target, + output [4:0] io_bru_3_bits_link, + output io_csr_valid, + output [4:0] io_csr_bits_addr, + output [11:0] io_csr_bits_index, + output [1:0] io_csr_bits_op, + input io_lsu_0_ready, + output io_lsu_0_valid, + io_lsu_0_bits_store, + output [4:0] io_lsu_0_bits_addr, + io_lsu_0_bits_op, + output [31:0] io_lsu_0_bits_pc, + input io_lsu_1_ready, + output io_lsu_1_valid, + io_lsu_1_bits_store, + output [4:0] io_lsu_1_bits_addr, + io_lsu_1_bits_op, + output [31:0] io_lsu_1_bits_pc, + input io_lsu_2_ready, + output io_lsu_2_valid, + io_lsu_2_bits_store, + output [4:0] io_lsu_2_bits_addr, + io_lsu_2_bits_op, + output [31:0] io_lsu_2_bits_pc, + input io_lsu_3_ready, + output io_lsu_3_valid, + io_lsu_3_bits_store, + output [4:0] io_lsu_3_bits_addr, + io_lsu_3_bits_op, + output [31:0] io_lsu_3_bits_pc, + output io_mlu_0_valid, + output [4:0] io_mlu_0_bits_addr, + output [2:0] io_mlu_0_bits_op, + output io_mlu_1_valid, + output [4:0] io_mlu_1_bits_addr, + output [2:0] io_mlu_1_bits_op, + output io_mlu_2_valid, + output [4:0] io_mlu_2_bits_addr, + output [2:0] io_mlu_2_bits_op, + output io_mlu_3_valid, + output [4:0] io_mlu_3_bits_addr, + output [2:0] io_mlu_3_bits_op, + input io_dvu_0_ready, + output io_dvu_0_valid, + output [4:0] io_dvu_0_bits_addr, + output [1:0] io_dvu_0_bits_op, + input io_float_ready, + output io_float_valid, + output [2:0] io_float_bits_opcode, + output [4:0] io_float_bits_funct5, + io_float_bits_rs3, + io_float_bits_rs2, + io_float_bits_rs1, + output [2:0] io_float_bits_rm, + output [31:0] io_float_bits_inst, + io_float_bits_pc, + output io_float_bits_scalar_rd, + io_float_bits_scalar_rs1, + output [4:0] io_float_bits_rd, + output io_float_bits_uses_rs3, + io_float_bits_uses_rs2, + output [4:0] io_fbusPortAddr, + output io_slog +); + + wire _decode_3_io_inst_ready; + wire _decode_3_io_jalFault; + wire _decode_3_io_jalrFault; + wire _decode_3_io_bxxFault; + wire _decode_2_io_inst_ready; + wire [31:0] _decode_2_io_scoreboard_spec; + wire _decode_2_io_jalFault; + wire _decode_2_io_jalrFault; + wire _decode_2_io_bxxFault; + wire _decode_2_io_serializeOut_mul; + wire _decode_2_io_serializeOut_jump; + wire _decode_2_io_serializeOut_brcond; + wire _decode_2_io_serializeOut_wfi; + wire _decode_2_io_serializeOut_fence; + wire _decode_2_io_serializeOut_csr; + wire _decode_2_io_serializeOut_undef; + wire _decode_1_io_inst_ready; + wire [31:0] _decode_1_io_scoreboard_spec; + wire _decode_1_io_jalFault; + wire _decode_1_io_jalrFault; + wire _decode_1_io_bxxFault; + wire _decode_1_io_serializeOut_mul; + wire _decode_1_io_serializeOut_jump; + wire _decode_1_io_serializeOut_brcond; + wire _decode_1_io_serializeOut_wfi; + wire _decode_1_io_serializeOut_fence; + wire _decode_1_io_serializeOut_csr; + wire _decode_1_io_serializeOut_undef; + wire _decode_0_io_inst_ready; + wire [31:0] _decode_0_io_scoreboard_spec; + wire _decode_0_io_jalFault; + wire _decode_0_io_jalrFault; + wire _decode_0_io_bxxFault; + wire _decode_0_io_undefFault; + wire _decode_0_io_csrFault; + wire _decode_0_io_serializeOut_mul; + wire _decode_0_io_serializeOut_jump; + wire _decode_0_io_serializeOut_brcond; + wire _decode_0_io_serializeOut_wfi; + wire _decode_0_io_serializeOut_fence; + wire _decode_0_io_serializeOut_csr; + wire _decode_0_io_serializeOut_undef; + wire mask_2 = _decode_0_io_inst_ready & _decode_1_io_inst_ready; + wire mask_3 = mask_2 & _decode_2_io_inst_ready; + wire decode_1_io_inst_valid = io_inst_1_valid & _decode_0_io_inst_ready; + wire decode_2_io_inst_valid = io_inst_2_valid & mask_2; + wire decode_3_io_inst_valid = io_inst_3_valid & mask_3; + wire [31:0] scoreboard_spec_2 = + _decode_0_io_scoreboard_spec | _decode_1_io_scoreboard_spec; + wire [31:0] scoreboard_spec_3 = scoreboard_spec_2 | _decode_2_io_scoreboard_spec; + Decode decode_0 ( + .io_halted (io_halted), + .io_inst_ready (_decode_0_io_inst_ready), + .io_inst_valid (io_inst_0_valid), + .io_inst_bits_addr (io_inst_0_bits_addr), + .io_inst_bits_inst (io_inst_0_bits_inst), + .io_inst_bits_brchFwd (io_inst_0_bits_brchFwd), + .io_scoreboard_regd (io_scoreboard_regd), + .io_scoreboard_comb (io_scoreboard_comb), + .io_scoreboard_spec (_decode_0_io_scoreboard_spec), + .io_fscoreboard (io_fscoreboard), + .io_lsuActive (io_lsuActive), + .io_rs1Read_valid (io_rs1Read_0_valid), + .io_rs1Read_addr (io_rs1Read_0_addr), + .io_rs1Set_valid (io_rs1Set_0_valid), + .io_rs1Set_value (io_rs1Set_0_value), + .io_rs2Read_valid (io_rs2Read_0_valid), + .io_rs2Read_addr (io_rs2Read_0_addr), + .io_rs2Set_valid (io_rs2Set_0_valid), + .io_rs2Set_value (io_rs2Set_0_value), + .io_rdMark_valid (io_rdMark_0_valid), + .io_rdMark_addr (io_rdMark_0_addr), + .io_rdMark_flt_valid (io_rdMark_flt_valid), + .io_rdMark_flt_addr (io_rdMark_flt_addr), + .io_busRead_bypass (io_busRead_0_bypass), + .io_busRead_immen (io_busRead_0_immen), + .io_busRead_immed (io_busRead_0_immed), + .io_jalFault (_decode_0_io_jalFault), + .io_jalrFault (_decode_0_io_jalrFault), + .io_bxxFault (_decode_0_io_bxxFault), + .io_undefFault (_decode_0_io_undefFault), + .io_bruTarget (io_bruTarget_0), + .io_jalrTarget_data (io_jalrTarget_0_data), + .io_alu_valid (io_alu_0_valid), + .io_alu_bits_addr (io_alu_0_bits_addr), + .io_alu_bits_op (io_alu_0_bits_op), + .io_bru_valid (io_bru_0_valid), + .io_bru_bits_fwd (io_bru_0_bits_fwd), + .io_bru_bits_op (io_bru_0_bits_op), + .io_bru_bits_pc (io_bru_0_bits_pc), + .io_bru_bits_target (io_bru_0_bits_target), + .io_bru_bits_link (io_bru_0_bits_link), + .io_csr_valid (io_csr_valid), + .io_csr_bits_addr (io_csr_bits_addr), + .io_csr_bits_index (io_csr_bits_index), + .io_csr_bits_op (io_csr_bits_op), + .io_csrFault (_decode_0_io_csrFault), + .io_lsu_ready (io_lsu_0_ready), + .io_lsu_valid (io_lsu_0_valid), + .io_lsu_bits_store (io_lsu_0_bits_store), + .io_lsu_bits_addr (io_lsu_0_bits_addr), + .io_lsu_bits_op (io_lsu_0_bits_op), + .io_lsu_bits_pc (io_lsu_0_bits_pc), + .io_mlu_valid (io_mlu_0_valid), + .io_mlu_bits_addr (io_mlu_0_bits_addr), + .io_mlu_bits_op (io_mlu_0_bits_op), + .io_dvu_ready (io_dvu_0_ready), + .io_dvu_valid (io_dvu_0_valid), + .io_dvu_bits_addr (io_dvu_0_bits_addr), + .io_dvu_bits_op (io_dvu_0_bits_op), + .io_float_ready (io_float_ready), + .io_float_valid (io_float_valid), + .io_float_bits_opcode (io_float_bits_opcode), + .io_float_bits_funct5 (io_float_bits_funct5), + .io_float_bits_rs3 (io_float_bits_rs3), + .io_float_bits_rs2 (io_float_bits_rs2), + .io_float_bits_rs1 (io_float_bits_rs1), + .io_float_bits_rm (io_float_bits_rm), + .io_float_bits_inst (io_float_bits_inst), + .io_float_bits_pc (io_float_bits_pc), + .io_float_bits_scalar_rd (io_float_bits_scalar_rd), + .io_float_bits_scalar_rs1 (io_float_bits_scalar_rs1), + .io_float_bits_rd (io_float_bits_rd), + .io_float_bits_uses_rs3 (io_float_bits_uses_rs3), + .io_float_bits_uses_rs2 (io_float_bits_uses_rs2), + .io_branchTaken (io_branchTaken), + .io_interlock (io_interlock), + .io_serializeOut_mul (_decode_0_io_serializeOut_mul), + .io_serializeOut_jump (_decode_0_io_serializeOut_jump), + .io_serializeOut_brcond (_decode_0_io_serializeOut_brcond), + .io_serializeOut_wfi (_decode_0_io_serializeOut_wfi), + .io_serializeOut_fence (_decode_0_io_serializeOut_fence), + .io_serializeOut_csr (_decode_0_io_serializeOut_csr), + .io_serializeOut_undef (_decode_0_io_serializeOut_undef), + .io_slog (io_slog) + ); + Decode_1 decode_1 ( + .io_halted (io_halted), + .io_inst_ready (_decode_1_io_inst_ready), + .io_inst_valid (decode_1_io_inst_valid), + .io_inst_bits_addr (io_inst_1_bits_addr), + .io_inst_bits_inst (io_inst_1_bits_inst), + .io_inst_bits_brchFwd (io_inst_1_bits_brchFwd), + .io_scoreboard_regd (io_scoreboard_regd | _decode_0_io_scoreboard_spec), + .io_scoreboard_comb (io_scoreboard_comb | _decode_0_io_scoreboard_spec), + .io_scoreboard_spec (_decode_1_io_scoreboard_spec), + .io_rs1Read_valid (io_rs1Read_1_valid), + .io_rs1Read_addr (io_rs1Read_1_addr), + .io_rs1Set_valid (io_rs1Set_1_valid), + .io_rs1Set_value (io_rs1Set_1_value), + .io_rs2Read_valid (io_rs2Read_1_valid), + .io_rs2Read_addr (io_rs2Read_1_addr), + .io_rs2Set_valid (io_rs2Set_1_valid), + .io_rs2Set_value (io_rs2Set_1_value), + .io_rdMark_valid (io_rdMark_1_valid), + .io_rdMark_addr (io_rdMark_1_addr), + .io_busRead_bypass (io_busRead_1_bypass), + .io_busRead_immed (io_busRead_1_immed), + .io_jalFault (_decode_1_io_jalFault), + .io_jalrFault (_decode_1_io_jalrFault), + .io_bxxFault (_decode_1_io_bxxFault), + .io_bruTarget (io_bruTarget_1), + .io_jalrTarget_data (io_jalrTarget_1_data), + .io_alu_valid (io_alu_1_valid), + .io_alu_bits_addr (io_alu_1_bits_addr), + .io_alu_bits_op (io_alu_1_bits_op), + .io_bru_valid (io_bru_1_valid), + .io_bru_bits_fwd (io_bru_1_bits_fwd), + .io_bru_bits_op (io_bru_1_bits_op), + .io_bru_bits_pc (io_bru_1_bits_pc), + .io_bru_bits_target (io_bru_1_bits_target), + .io_bru_bits_link (io_bru_1_bits_link), + .io_lsu_ready (io_lsu_1_ready), + .io_lsu_valid (io_lsu_1_valid), + .io_lsu_bits_store (io_lsu_1_bits_store), + .io_lsu_bits_addr (io_lsu_1_bits_addr), + .io_lsu_bits_op (io_lsu_1_bits_op), + .io_lsu_bits_pc (io_lsu_1_bits_pc), + .io_mlu_valid (io_mlu_1_valid), + .io_mlu_bits_addr (io_mlu_1_bits_addr), + .io_mlu_bits_op (io_mlu_1_bits_op), + .io_branchTaken (io_branchTaken), + .io_interlock (io_interlock), + .io_serializeIn_mul (_decode_0_io_serializeOut_mul), + .io_serializeIn_jump (_decode_0_io_serializeOut_jump), + .io_serializeIn_brcond (_decode_0_io_serializeOut_brcond), + .io_serializeIn_wfi (_decode_0_io_serializeOut_wfi), + .io_serializeIn_fence (_decode_0_io_serializeOut_fence), + .io_serializeIn_csr (_decode_0_io_serializeOut_csr), + .io_serializeIn_undef (_decode_0_io_serializeOut_undef), + .io_serializeOut_mul (_decode_1_io_serializeOut_mul), + .io_serializeOut_jump (_decode_1_io_serializeOut_jump), + .io_serializeOut_brcond (_decode_1_io_serializeOut_brcond), + .io_serializeOut_wfi (_decode_1_io_serializeOut_wfi), + .io_serializeOut_fence (_decode_1_io_serializeOut_fence), + .io_serializeOut_csr (_decode_1_io_serializeOut_csr), + .io_serializeOut_undef (_decode_1_io_serializeOut_undef) + ); + Decode_2 decode_2 ( + .io_halted (io_halted), + .io_inst_ready (_decode_2_io_inst_ready), + .io_inst_valid (decode_2_io_inst_valid), + .io_inst_bits_addr (io_inst_2_bits_addr), + .io_inst_bits_inst (io_inst_2_bits_inst), + .io_inst_bits_brchFwd (io_inst_2_bits_brchFwd), + .io_scoreboard_regd (io_scoreboard_regd | scoreboard_spec_2), + .io_scoreboard_comb (io_scoreboard_comb | scoreboard_spec_2), + .io_scoreboard_spec (_decode_2_io_scoreboard_spec), + .io_rs1Read_valid (io_rs1Read_2_valid), + .io_rs1Read_addr (io_rs1Read_2_addr), + .io_rs1Set_valid (io_rs1Set_2_valid), + .io_rs1Set_value (io_rs1Set_2_value), + .io_rs2Read_valid (io_rs2Read_2_valid), + .io_rs2Read_addr (io_rs2Read_2_addr), + .io_rs2Set_valid (io_rs2Set_2_valid), + .io_rs2Set_value (io_rs2Set_2_value), + .io_rdMark_valid (io_rdMark_2_valid), + .io_rdMark_addr (io_rdMark_2_addr), + .io_busRead_bypass (io_busRead_2_bypass), + .io_busRead_immed (io_busRead_2_immed), + .io_jalFault (_decode_2_io_jalFault), + .io_jalrFault (_decode_2_io_jalrFault), + .io_bxxFault (_decode_2_io_bxxFault), + .io_bruTarget (io_bruTarget_2), + .io_jalrTarget_data (io_jalrTarget_2_data), + .io_alu_valid (io_alu_2_valid), + .io_alu_bits_addr (io_alu_2_bits_addr), + .io_alu_bits_op (io_alu_2_bits_op), + .io_bru_valid (io_bru_2_valid), + .io_bru_bits_fwd (io_bru_2_bits_fwd), + .io_bru_bits_op (io_bru_2_bits_op), + .io_bru_bits_pc (io_bru_2_bits_pc), + .io_bru_bits_target (io_bru_2_bits_target), + .io_bru_bits_link (io_bru_2_bits_link), + .io_lsu_ready (io_lsu_2_ready), + .io_lsu_valid (io_lsu_2_valid), + .io_lsu_bits_store (io_lsu_2_bits_store), + .io_lsu_bits_addr (io_lsu_2_bits_addr), + .io_lsu_bits_op (io_lsu_2_bits_op), + .io_lsu_bits_pc (io_lsu_2_bits_pc), + .io_mlu_valid (io_mlu_2_valid), + .io_mlu_bits_addr (io_mlu_2_bits_addr), + .io_mlu_bits_op (io_mlu_2_bits_op), + .io_branchTaken (io_branchTaken), + .io_interlock (io_interlock), + .io_serializeIn_mul (_decode_1_io_serializeOut_mul), + .io_serializeIn_jump (_decode_1_io_serializeOut_jump), + .io_serializeIn_brcond (_decode_1_io_serializeOut_brcond), + .io_serializeIn_wfi (_decode_1_io_serializeOut_wfi), + .io_serializeIn_fence (_decode_1_io_serializeOut_fence), + .io_serializeIn_csr (_decode_1_io_serializeOut_csr), + .io_serializeIn_undef (_decode_1_io_serializeOut_undef), + .io_serializeOut_mul (_decode_2_io_serializeOut_mul), + .io_serializeOut_jump (_decode_2_io_serializeOut_jump), + .io_serializeOut_brcond (_decode_2_io_serializeOut_brcond), + .io_serializeOut_wfi (_decode_2_io_serializeOut_wfi), + .io_serializeOut_fence (_decode_2_io_serializeOut_fence), + .io_serializeOut_csr (_decode_2_io_serializeOut_csr), + .io_serializeOut_undef (_decode_2_io_serializeOut_undef) + ); + Decode_3 decode_3 ( + .io_halted (io_halted), + .io_inst_ready (_decode_3_io_inst_ready), + .io_inst_valid (decode_3_io_inst_valid), + .io_inst_bits_addr (io_inst_3_bits_addr), + .io_inst_bits_inst (io_inst_3_bits_inst), + .io_inst_bits_brchFwd (io_inst_3_bits_brchFwd), + .io_scoreboard_regd (io_scoreboard_regd | scoreboard_spec_3), + .io_scoreboard_comb (io_scoreboard_comb | scoreboard_spec_3), + .io_rs1Read_valid (io_rs1Read_3_valid), + .io_rs1Read_addr (io_rs1Read_3_addr), + .io_rs1Set_valid (io_rs1Set_3_valid), + .io_rs1Set_value (io_rs1Set_3_value), + .io_rs2Read_valid (io_rs2Read_3_valid), + .io_rs2Read_addr (io_rs2Read_3_addr), + .io_rs2Set_valid (io_rs2Set_3_valid), + .io_rs2Set_value (io_rs2Set_3_value), + .io_rdMark_valid (io_rdMark_3_valid), + .io_rdMark_addr (io_rdMark_3_addr), + .io_busRead_bypass (io_busRead_3_bypass), + .io_busRead_immed (io_busRead_3_immed), + .io_jalFault (_decode_3_io_jalFault), + .io_jalrFault (_decode_3_io_jalrFault), + .io_bxxFault (_decode_3_io_bxxFault), + .io_bruTarget (io_bruTarget_3), + .io_jalrTarget_data (io_jalrTarget_3_data), + .io_alu_valid (io_alu_3_valid), + .io_alu_bits_addr (io_alu_3_bits_addr), + .io_alu_bits_op (io_alu_3_bits_op), + .io_bru_valid (io_bru_3_valid), + .io_bru_bits_fwd (io_bru_3_bits_fwd), + .io_bru_bits_op (io_bru_3_bits_op), + .io_bru_bits_pc (io_bru_3_bits_pc), + .io_bru_bits_target (io_bru_3_bits_target), + .io_bru_bits_link (io_bru_3_bits_link), + .io_lsu_ready (io_lsu_3_ready), + .io_lsu_valid (io_lsu_3_valid), + .io_lsu_bits_store (io_lsu_3_bits_store), + .io_lsu_bits_addr (io_lsu_3_bits_addr), + .io_lsu_bits_op (io_lsu_3_bits_op), + .io_lsu_bits_pc (io_lsu_3_bits_pc), + .io_mlu_valid (io_mlu_3_valid), + .io_mlu_bits_addr (io_mlu_3_bits_addr), + .io_mlu_bits_op (io_mlu_3_bits_op), + .io_branchTaken (io_branchTaken), + .io_interlock (io_interlock), + .io_serializeIn_mul (_decode_2_io_serializeOut_mul), + .io_serializeIn_jump (_decode_2_io_serializeOut_jump), + .io_serializeIn_brcond (_decode_2_io_serializeOut_brcond), + .io_serializeIn_wfi (_decode_2_io_serializeOut_wfi), + .io_serializeIn_fence (_decode_2_io_serializeOut_fence), + .io_serializeIn_csr (_decode_2_io_serializeOut_csr), + .io_serializeIn_undef (_decode_2_io_serializeOut_undef) + ); + assign io_csrFault_0 = _decode_0_io_csrFault & ~io_branchTaken & io_inst_0_valid; + assign io_jalFault_0 = _decode_0_io_jalFault & ~io_branchTaken & io_inst_0_valid; + assign io_jalFault_1 = _decode_1_io_jalFault & ~io_branchTaken & decode_1_io_inst_valid; + assign io_jalFault_2 = _decode_2_io_jalFault & ~io_branchTaken & decode_2_io_inst_valid; + assign io_jalFault_3 = _decode_3_io_jalFault & ~io_branchTaken & decode_3_io_inst_valid; + assign io_jalrFault_0 = _decode_0_io_jalrFault & ~io_branchTaken & io_inst_0_valid; + assign io_jalrFault_1 = + _decode_1_io_jalrFault & ~io_branchTaken & decode_1_io_inst_valid; + assign io_jalrFault_2 = + _decode_2_io_jalrFault & ~io_branchTaken & decode_2_io_inst_valid; + assign io_jalrFault_3 = + _decode_3_io_jalrFault & ~io_branchTaken & decode_3_io_inst_valid; + assign io_bxxFault_0 = _decode_0_io_bxxFault & ~io_branchTaken & io_inst_0_valid; + assign io_bxxFault_1 = _decode_1_io_bxxFault & ~io_branchTaken & decode_1_io_inst_valid; + assign io_bxxFault_2 = _decode_2_io_bxxFault & ~io_branchTaken & decode_2_io_inst_valid; + assign io_bxxFault_3 = _decode_3_io_bxxFault & ~io_branchTaken & decode_3_io_inst_valid; + assign io_undefFault_0 = _decode_0_io_undefFault & ~io_branchTaken & io_inst_0_valid; + assign io_inst_0_ready = _decode_0_io_inst_ready; + assign io_inst_1_ready = _decode_1_io_inst_ready & _decode_0_io_inst_ready; + assign io_inst_2_ready = _decode_2_io_inst_ready & mask_2; + assign io_inst_3_ready = _decode_3_io_inst_ready & mask_3; + assign io_fbusPortAddr = io_inst_0_bits_inst[24:20]; +endmodule + +module Alu( + input clock, + reset, + io_req_valid, + input [4:0] io_req_bits_addr, + io_req_bits_op, + input io_rs1_valid, + input [31:0] io_rs1_data, + input io_rs2_valid, + input [31:0] io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data +); + + reg valid; + reg [4:0] addr; + reg [4:0] op; + wire r2IsGreater = $signed(io_rs1_data) < $signed(io_rs2_data); + wire r2IsGreaterU = io_rs1_data < io_rs2_data; + wire [31:0] _io_rd_bits_data_T_19 = io_rs1_data ^ io_rs2_data; + wire [62:0] _io_rd_bits_data_T_7 = {31'h0, io_rs1_data} << io_rs2_data[4:0]; + wire [31:0] _GEN = {27'h0, io_rs2_data[4:0]}; + wire [31:0] _io_rd_bits_data_T_29 = + {16'h0, io_rs1_data[31:16]} | {io_rs1_data[15:0], 16'h0}; + wire [31:0] _io_rd_bits_data_T_39 = + {8'h0, _io_rd_bits_data_T_29[31:8] & 24'hFF00FF} + | {_io_rd_bits_data_T_29[23:0] & 24'hFF00FF, 8'h0}; + wire [31:0] _io_rd_bits_data_T_49 = + {4'h0, _io_rd_bits_data_T_39[31:4] & 28'hF0F0F0F} + | {_io_rd_bits_data_T_39[27:0] & 28'hF0F0F0F, 4'h0}; + wire [31:0] _io_rd_bits_data_T_59 = + {2'h0, _io_rd_bits_data_T_49[31:2] & 30'h33333333} + | {_io_rd_bits_data_T_49[29:0] & 30'h33333333, 2'h0}; + wire [31:0] _io_rd_bits_data_T_69 = + {1'h0, _io_rd_bits_data_T_59[31:1] & 31'h55555555} + | {_io_rd_bits_data_T_59[30:0] & 31'h55555555, 1'h0}; + wire [31:0] _io_rd_bits_data_T_312 = + io_rs2_data[0] ? {io_rs1_data[30:0], io_rs1_data[31]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_316 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_312[29:0], _io_rd_bits_data_T_312[31:30]} + : _io_rd_bits_data_T_312; + wire [31:0] _io_rd_bits_data_T_320 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_316[27:0], _io_rd_bits_data_T_316[31:28]} + : _io_rd_bits_data_T_316; + wire [31:0] _io_rd_bits_data_T_324 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_320[23:0], _io_rd_bits_data_T_320[31:24]} + : _io_rd_bits_data_T_320; + wire [31:0] _io_rd_bits_data_T_337 = + io_rs2_data[0] ? {io_rs1_data[0], io_rs1_data[31:1]} : io_rs1_data; + wire [31:0] _io_rd_bits_data_T_341 = + io_rs2_data[1] + ? {_io_rd_bits_data_T_337[1:0], _io_rd_bits_data_T_337[31:2]} + : _io_rd_bits_data_T_337; + wire [31:0] _io_rd_bits_data_T_345 = + io_rs2_data[2] + ? {_io_rd_bits_data_T_341[3:0], _io_rd_bits_data_T_341[31:4]} + : _io_rd_bits_data_T_341; + wire [31:0] _io_rd_bits_data_T_349 = + io_rs2_data[3] + ? {_io_rd_bits_data_T_345[7:0], _io_rd_bits_data_T_345[31:8]} + : _io_rd_bits_data_T_345; + wire [31:0][31:0] _GEN_0 = + {{32'h0}, + {32'h0}, + {32'h0}, + {32'h0}, + {{16'h0, io_rs1_data[15:0]}}, + {{io_rs1_data[7:0], io_rs1_data[15:8], io_rs1_data[23:16], io_rs1_data[31:24]}}, + {{io_rs1_data[31:24] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[23:16] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[15:8] == 8'h0 ? 8'h0 : 8'hFF, + io_rs1_data[7:0] == 8'h0 ? 8'h0 : 8'hFF}}, + {io_rs2_data[4] + ? {_io_rd_bits_data_T_349[15:0], _io_rd_bits_data_T_349[31:16]} + : _io_rd_bits_data_T_349}, + {io_rs2_data[4] + ? {_io_rd_bits_data_T_324[15:0], _io_rd_bits_data_T_324[31:16]} + : _io_rd_bits_data_T_324}, + {{{16{io_rs1_data[15]}}, io_rs1_data[15:0]}}, + {{{24{io_rs1_data[7]}}, io_rs1_data[7:0]}}, + {r2IsGreaterU ? io_rs1_data : io_rs2_data}, + {r2IsGreater ? io_rs1_data : io_rs2_data}, + {r2IsGreaterU ? io_rs2_data : io_rs1_data}, + {r2IsGreater ? io_rs2_data : io_rs1_data}, + {{26'h0, + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[0]} + {1'h0, io_rs1_data[1]}} + + {1'h0, {1'h0, io_rs1_data[2]} + {1'h0, io_rs1_data[3]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[4]} + {1'h0, io_rs1_data[5]}} + + {1'h0, {1'h0, io_rs1_data[6]} + {1'h0, io_rs1_data[7]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[8]} + {1'h0, io_rs1_data[9]}} + + {1'h0, {1'h0, io_rs1_data[10]} + {1'h0, io_rs1_data[11]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[12]} + {1'h0, io_rs1_data[13]}} + + {1'h0, {1'h0, io_rs1_data[14]} + {1'h0, io_rs1_data[15]}}}}} + + {1'h0, + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[16]} + {1'h0, io_rs1_data[17]}} + + {1'h0, {1'h0, io_rs1_data[18]} + {1'h0, io_rs1_data[19]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[20]} + {1'h0, io_rs1_data[21]}} + + {1'h0, {1'h0, io_rs1_data[22]} + {1'h0, io_rs1_data[23]}}}} + + {1'h0, + {1'h0, + {1'h0, {1'h0, io_rs1_data[24]} + {1'h0, io_rs1_data[25]}} + + {1'h0, {1'h0, io_rs1_data[26]} + {1'h0, io_rs1_data[27]}}} + + {1'h0, + {1'h0, {1'h0, io_rs1_data[28]} + {1'h0, io_rs1_data[29]}} + + {1'h0, {1'h0, io_rs1_data[30]} + {1'h0, io_rs1_data[31]}}}}}}}, + {{26'h0, + io_rs1_data[0] + ? 6'h0 + : io_rs1_data[1] + ? 6'h1 + : io_rs1_data[2] + ? 6'h2 + : io_rs1_data[3] + ? 6'h3 + : io_rs1_data[4] + ? 6'h4 + : io_rs1_data[5] + ? 6'h5 + : io_rs1_data[6] + ? 6'h6 + : io_rs1_data[7] + ? 6'h7 + : io_rs1_data[8] + ? 6'h8 + : io_rs1_data[9] + ? 6'h9 + : io_rs1_data[10] + ? 6'hA + : io_rs1_data[11] + ? 6'hB + : io_rs1_data[12] + ? 6'hC + : io_rs1_data[13] + ? 6'hD + : io_rs1_data[14] + ? 6'hE + : io_rs1_data[15] + ? 6'hF + : io_rs1_data[16] + ? 6'h10 + : io_rs1_data[17] + ? 6'h11 + : io_rs1_data[18] + ? 6'h12 + : io_rs1_data[19] + ? 6'h13 + : io_rs1_data[20] + ? 6'h14 + : io_rs1_data[21] + ? 6'h15 + : io_rs1_data[22] + ? 6'h16 + : io_rs1_data[23] + ? 6'h17 + : io_rs1_data[24] + ? 6'h18 + : io_rs1_data[25] + ? 6'h19 + : io_rs1_data[26] + ? 6'h1A + : io_rs1_data[27] + ? 6'h1B + : io_rs1_data[28] + ? 6'h1C + : io_rs1_data[29] + ? 6'h1D + : io_rs1_data[30] + ? 6'h1E + : io_rs1_data[31] + ? 6'h1F + : 6'h20}}, + {{26'h0, + _io_rd_bits_data_T_69[0] + ? 6'h0 + : _io_rd_bits_data_T_69[1] + ? 6'h1 + : _io_rd_bits_data_T_69[2] + ? 6'h2 + : _io_rd_bits_data_T_69[3] + ? 6'h3 + : _io_rd_bits_data_T_69[4] + ? 6'h4 + : _io_rd_bits_data_T_69[5] + ? 6'h5 + : _io_rd_bits_data_T_69[6] + ? 6'h6 + : _io_rd_bits_data_T_69[7] + ? 6'h7 + : _io_rd_bits_data_T_69[8] + ? 6'h8 + : _io_rd_bits_data_T_69[9] + ? 6'h9 + : _io_rd_bits_data_T_69[10] + ? 6'hA + : _io_rd_bits_data_T_69[11] + ? 6'hB + : _io_rd_bits_data_T_69[12] + ? 6'hC + : _io_rd_bits_data_T_69[13] + ? 6'hD + : _io_rd_bits_data_T_69[14] + ? 6'hE + : _io_rd_bits_data_T_69[15] + ? 6'hF + : _io_rd_bits_data_T_69[16] + ? 6'h10 + : _io_rd_bits_data_T_69[17] + ? 6'h11 + : _io_rd_bits_data_T_69[18] + ? 6'h12 + : _io_rd_bits_data_T_69[19] + ? 6'h13 + : _io_rd_bits_data_T_69[20] + ? 6'h14 + : _io_rd_bits_data_T_69[21] + ? 6'h15 + : _io_rd_bits_data_T_69[22] + ? 6'h16 + : _io_rd_bits_data_T_69[23] + ? 6'h17 + : _io_rd_bits_data_T_69[24] + ? 6'h18 + : _io_rd_bits_data_T_69[25] + ? 6'h19 + : _io_rd_bits_data_T_69[26] + ? 6'h1A + : _io_rd_bits_data_T_69[27] + ? 6'h1B + : _io_rd_bits_data_T_69[28] + ? 6'h1C + : _io_rd_bits_data_T_69[29] + ? 6'h1D + : _io_rd_bits_data_T_69[30] + ? 6'h1E + : _io_rd_bits_data_T_69[31] + ? 6'h1F + : 6'h20}}, + {~_io_rd_bits_data_T_19}, + {io_rs1_data | ~io_rs2_data}, + {io_rs1_data & ~io_rs2_data}, + {io_rs2_data}, + {$signed($signed(io_rs1_data) >>> _GEN)}, + {io_rs1_data >> _GEN}, + {_io_rd_bits_data_T_7[31:0]}, + {io_rs1_data & io_rs2_data}, + {io_rs1_data | io_rs2_data}, + {_io_rd_bits_data_T_19}, + {{31'h0, r2IsGreaterU}}, + {{31'h0, r2IsGreater}}, + {io_rs1_data - io_rs2_data}, + {io_rs1_data + io_rs2_data}}; + always @(posedge clock or posedge reset) begin + if (reset) begin + valid <= 1'h0; + addr <= 5'h0; + op <= 5'h0; + end + else begin + valid <= io_req_valid; + if (io_req_valid) begin + addr <= io_req_bits_addr; + op <= io_req_bits_op; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + valid = _RANDOM[/*Zero width*/ 1'b0][0]; + addr = _RANDOM[/*Zero width*/ 1'b0][5:1]; + op = _RANDOM[/*Zero width*/ 1'b0][10:6]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + valid = 1'h0; + addr = 5'h0; + op = 5'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_rd_valid = valid; + assign io_rd_bits_addr = addr; + assign io_rd_bits_data = _GEN_0[op]; +endmodule + +module Bru( + input clock, + reset, + io_req_valid, + io_req_bits_fwd, + input [3:0] io_req_bits_op, + input [31:0] io_req_bits_pc, + io_req_bits_target, + input [4:0] io_req_bits_link, + output io_csr_in_mode_valid, + output [1:0] io_csr_in_mode_bits, + output io_csr_in_mcause_valid, + output [31:0] io_csr_in_mcause_bits, + output io_csr_in_mepc_valid, + output [31:0] io_csr_in_mepc_bits, + output io_csr_in_mtval_valid, + output [31:0] io_csr_in_mtval_bits, + output io_csr_in_halt, + io_csr_in_fault, + io_csr_in_wfi, + input [1:0] io_csr_out_mode, + input [31:0] io_csr_out_mepc, + io_csr_out_mtvec, + input io_rs1_valid, + input [31:0] io_rs1_data, + input io_rs2_valid, + input [31:0] io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_taken_valid, + output [31:0] io_taken_value, + input [31:0] io_target_data, + output io_interlock, + input io_fault_manager_valid, + input [31:0] io_fault_manager_bits_mepc, + io_fault_manager_bits_mtval, + io_fault_manager_bits_mcause +); + + wire io_csr_in_fault_0; + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + reg [31:0] stateReg_bits_pcEx; + wire _io_csr_in_fault_T = io_csr_out_mode == 2'h0; + wire _io_csr_in_mcause_bits_T_4 = io_csr_out_mode == 2'h1; + wire _ignore_T_2 = stateReg_bits_op == 4'h8; + wire _ignore_T_3 = stateReg_bits_op == 4'h9; + wire _ignore_T_4 = stateReg_bits_op == 4'hA; + wire _ignore_T_5 = stateReg_bits_op == 4'hB; + wire _ignore_T_7 = stateReg_bits_op == 4'hD; + wire usageFault = + stateReg_valid + & (_io_csr_in_mcause_bits_T_4 ? (|{_ignore_T_5, _ignore_T_4}) : _ignore_T_2); + assign io_csr_in_fault_0 = usageFault & _io_csr_in_fault_T; + wire _ignore_T_6 = stateReg_bits_op == 4'hC; + wire [31:0] nextState_linkData = io_req_bits_pc + 32'h4; + wire _nextState_target_T = io_req_bits_op == 4'h1; + wire [31:0] mtvec = {io_csr_out_mtvec[31:2], 2'h0}; + wire _pipeline0Target_call_T = io_req_bits_op == 4'hB; + wire stateRegValid = io_req_valid | io_fault_manager_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h0; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h0; + stateReg_bits_linkData <= 32'h0; + stateReg_bits_pcEx <= 32'h0; + end + else begin + stateReg_valid <= stateRegValid; + if (stateRegValid) begin + stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; + stateReg_bits_op <= io_fault_manager_valid ? 4'hD : io_req_bits_op; + stateReg_bits_target <= + io_fault_manager_valid + ? mtvec + : io_req_bits_fwd + ? nextState_linkData + : _nextState_target_T + ? io_target_data & 32'hFFFFFFFE + : io_req_bits_op == 4'h9 + ? mtvec + : (|{_pipeline0Target_call_T & _io_csr_in_fault_T, + _pipeline0Target_call_T & _io_csr_in_mcause_bits_T_4, + io_req_bits_op == 4'hA, + io_req_bits_op == 4'h8}) + ? io_csr_out_mepc + : io_req_bits_op == 4'hC + ? nextState_linkData + : io_req_bits_target; + stateReg_bits_linkValid <= + io_req_valid & (|io_req_bits_link) + & (|{_nextState_target_T, io_req_bits_op == 4'h0}); + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= nextState_linkData; + stateReg_bits_pcEx <= io_req_bits_pc; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + stateReg_valid = _RANDOM[2'h0][0]; + stateReg_bits_fwd = _RANDOM[2'h0][1]; + stateReg_bits_op = _RANDOM[2'h0][5:2]; + stateReg_bits_target = {_RANDOM[2'h0][31:6], _RANDOM[2'h1][5:0]}; + stateReg_bits_linkValid = _RANDOM[2'h1][6]; + stateReg_bits_linkAddr = _RANDOM[2'h1][11:7]; + stateReg_bits_linkData = {_RANDOM[2'h1][31:12], _RANDOM[2'h2][11:0]}; + stateReg_bits_pcEx = {_RANDOM[2'h2][31:12], _RANDOM[2'h3][11:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + stateReg_valid = 1'h0; + stateReg_bits_fwd = 1'h0; + stateReg_bits_op = 4'h0; + stateReg_bits_target = 32'h0; + stateReg_bits_linkValid = 1'h0; + stateReg_bits_linkAddr = 5'h0; + stateReg_bits_linkData = 32'h0; + stateReg_bits_pcEx = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_csr_in_mode_valid = + stateReg_valid + & (_io_csr_in_mcause_bits_T_4 + ? (|{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2}) + : _ignore_T_5); + assign io_csr_in_mode_bits = {1'h0, ~(_ignore_T_5 & _io_csr_in_fault_T)}; + assign io_csr_in_mcause_valid = + stateReg_valid & (usageFault | _ignore_T_3 | _io_csr_in_mcause_bits_T_4 & _ignore_T_2) + | io_fault_manager_valid; + assign io_csr_in_mcause_bits = + io_fault_manager_valid + ? io_fault_manager_bits_mcause + : {27'h0, + _ignore_T_3 & _io_csr_in_fault_T + ? 5'hB + : _ignore_T_3 & _io_csr_in_mcause_bits_T_4 + ? 5'h8 + : _ignore_T_2 ? 5'h3 : usageFault ? 5'h19 : 5'h0}; + assign io_csr_in_mepc_valid = stateReg_valid & _ignore_T_3 | io_fault_manager_valid; + assign io_csr_in_mepc_bits = + io_fault_manager_valid ? io_fault_manager_bits_mepc : stateReg_bits_pcEx; + assign io_csr_in_mtval_valid = usageFault | io_fault_manager_valid; + assign io_csr_in_mtval_bits = + io_fault_manager_valid ? io_fault_manager_bits_mtval : stateReg_bits_pcEx; + assign io_csr_in_halt = + stateReg_valid & _ignore_T_4 & _io_csr_in_fault_T | io_csr_in_fault_0; + assign io_csr_in_fault = io_csr_in_fault_0; + assign io_csr_in_wfi = stateReg_valid & _ignore_T_6; + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = + stateReg_valid + & (stateReg_bits_op == 4'hD + | (stateReg_bits_op == 4'h7 + ? io_rs1_data >= io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h6 + ? io_rs1_data < io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h5 + ? $signed(io_rs1_data) >= $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h4 + ? $signed(io_rs1_data) < $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h3 + ? io_rs1_data != io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h2 + ? io_rs1_data == io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op) + ? ~stateReg_bits_fwd + : stateReg_bits_op == 4'hC + | (stateReg_bits_op == 4'hB + ? _io_csr_in_fault_T + : stateReg_bits_op == 4'hA + ? _io_csr_in_mcause_bits_T_4 + : stateReg_bits_op == 4'h9 + | stateReg_bits_op == 4'h8 + & _io_csr_in_mcause_bits_T_4))); + assign io_taken_value = stateReg_bits_target; + assign io_interlock = + stateReg_valid & (|{_ignore_T_7, _ignore_T_5, _ignore_T_4, _ignore_T_3, _ignore_T_2}); +endmodule + +module Bru_1( + input clock, + reset, + io_req_valid, + io_req_bits_fwd, + input [3:0] io_req_bits_op, + input [31:0] io_req_bits_pc, + io_req_bits_target, + input [4:0] io_req_bits_link, + input io_rs1_valid, + input [31:0] io_rs1_data, + input io_rs2_valid, + input [31:0] io_rs2_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_taken_valid, + output [31:0] io_taken_value, + input [31:0] io_target_data +); + + reg stateReg_valid; + reg stateReg_bits_fwd; + reg [3:0] stateReg_bits_op; + reg [31:0] stateReg_bits_target; + reg stateReg_bits_linkValid; + reg [4:0] stateReg_bits_linkAddr; + reg [31:0] stateReg_bits_linkData; + wire _ignore_T_2 = stateReg_bits_op == 4'h8; + wire _ignore_T_3 = stateReg_bits_op == 4'h9; + wire _ignore_T_4 = stateReg_bits_op == 4'hA; + wire _ignore_T_5 = stateReg_bits_op == 4'hB; + wire _ignore_T_6 = stateReg_bits_op == 4'hC; + wire [31:0] nextState_linkData = io_req_bits_pc + 32'h4; + wire _nextState_target_T = io_req_bits_op == 4'h1; + always @(posedge clock or posedge reset) begin + if (reset) begin + stateReg_valid <= 1'h0; + stateReg_bits_fwd <= 1'h0; + stateReg_bits_op <= 4'h0; + stateReg_bits_target <= 32'h0; + stateReg_bits_linkValid <= 1'h0; + stateReg_bits_linkAddr <= 5'h0; + stateReg_bits_linkData <= 32'h0; + end + else begin + stateReg_valid <= io_req_valid; + if (io_req_valid) begin + stateReg_bits_fwd <= io_req_valid & io_req_bits_fwd; + stateReg_bits_op <= io_req_bits_op; + stateReg_bits_target <= + io_req_bits_fwd + ? nextState_linkData + : _nextState_target_T ? io_target_data & 32'hFFFFFFFE : io_req_bits_target; + stateReg_bits_linkValid <= + io_req_valid & (|io_req_bits_link) + & (|{_nextState_target_T, io_req_bits_op == 4'h0}); + stateReg_bits_linkAddr <= io_req_bits_link; + stateReg_bits_linkData <= nextState_linkData; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + stateReg_valid = _RANDOM[2'h0][0]; + stateReg_bits_fwd = _RANDOM[2'h0][1]; + stateReg_bits_op = _RANDOM[2'h0][5:2]; + stateReg_bits_target = {_RANDOM[2'h0][31:6], _RANDOM[2'h1][5:0]}; + stateReg_bits_linkValid = _RANDOM[2'h1][6]; + stateReg_bits_linkAddr = _RANDOM[2'h1][11:7]; + stateReg_bits_linkData = {_RANDOM[2'h1][31:12], _RANDOM[2'h2][11:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + stateReg_valid = 1'h0; + stateReg_bits_fwd = 1'h0; + stateReg_bits_op = 4'h0; + stateReg_bits_target = 32'h0; + stateReg_bits_linkValid = 1'h0; + stateReg_bits_linkAddr = 5'h0; + stateReg_bits_linkData = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_rd_valid = stateReg_valid & stateReg_bits_linkValid; + assign io_rd_bits_addr = stateReg_bits_linkAddr; + assign io_rd_bits_data = stateReg_bits_linkData; + assign io_taken_valid = + stateReg_valid + & (stateReg_bits_op == 4'hD + | (stateReg_bits_op == 4'h7 + ? io_rs1_data >= io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h6 + ? io_rs1_data < io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h5 + ? $signed(io_rs1_data) >= $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h4 + ? $signed(io_rs1_data) < $signed(io_rs2_data) != stateReg_bits_fwd + : stateReg_bits_op == 4'h3 + ? io_rs1_data != io_rs2_data != stateReg_bits_fwd + : stateReg_bits_op == 4'h2 + ? io_rs1_data == io_rs2_data != stateReg_bits_fwd + : (stateReg_bits_op == 4'h1 | ~(|stateReg_bits_op)) + & ~stateReg_bits_fwd)); + assign io_taken_value = stateReg_bits_target; +endmodule + +module Slice( + input clock, + reset, + output io_in_ready, + input io_in_valid, + input [31:0] io_in_bits_pc, + io_in_bits_addr, + io_in_bits_adrx, + io_in_bits_data, + input [4:0] io_in_bits_index, + io_in_bits_size, + io_in_bits_fullsize, + input io_in_bits_write, + io_in_bits_sext, + io_in_bits_iload, + io_in_bits_fencei, + io_in_bits_flushat, + io_in_bits_flushall, + io_in_bits_sldst, + io_in_bits_vldst, + io_in_bits_fldst, + input [1:0] io_in_bits_regionType, + input [15:0] io_in_bits_mask, + input io_in_bits_last, + io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_pc, + io_out_bits_addr, + io_out_bits_adrx, + io_out_bits_data, + output [4:0] io_out_bits_index, + io_out_bits_size, + io_out_bits_fullsize, + output io_out_bits_write, + io_out_bits_sext, + io_out_bits_iload, + io_out_bits_fencei, + io_out_bits_flushat, + io_out_bits_flushall, + io_out_bits_sldst, + io_out_bits_vldst, + io_out_bits_fldst, + output [1:0] io_out_bits_regionType, + output [15:0] io_out_bits_mask, + output io_out_bits_last +); + + reg ipos; + reg opos; + reg [31:0] mem_0_pc; + reg [31:0] mem_0_addr; + reg [31:0] mem_0_adrx; + reg [31:0] mem_0_data; + reg [4:0] mem_0_index; + reg [4:0] mem_0_size; + reg [4:0] mem_0_fullsize; + reg mem_0_write; + reg mem_0_sext; + reg mem_0_iload; + reg mem_0_fencei; + reg mem_0_flushat; + reg mem_0_flushall; + reg mem_0_sldst; + reg mem_0_vldst; + reg mem_0_fldst; + reg [1:0] mem_0_regionType; + reg [15:0] mem_0_mask; + reg mem_0_last; + wire io_in_ready_0 = ipos == opos | io_out_ready; + wire io_out_valid_0 = ipos != opos; + always @(posedge clock or posedge reset) begin + if (reset) begin + ipos <= 1'h0; + opos <= 1'h0; + mem_0_pc <= 32'h0; + mem_0_addr <= 32'h0; + mem_0_adrx <= 32'h0; + mem_0_data <= 32'h0; + mem_0_index <= 5'h0; + mem_0_size <= 5'h0; + mem_0_fullsize <= 5'h0; + mem_0_write <= 1'h0; + mem_0_sext <= 1'h0; + mem_0_iload <= 1'h0; + mem_0_fencei <= 1'h0; + mem_0_flushat <= 1'h0; + mem_0_flushall <= 1'h0; + mem_0_sldst <= 1'h0; + mem_0_vldst <= 1'h0; + mem_0_fldst <= 1'h0; + mem_0_regionType <= 2'h0; + mem_0_mask <= 16'h0; + mem_0_last <= 1'h0; + end + else begin + if (io_in_valid & io_in_ready_0) begin + ipos <= ipos - 1'h1; + mem_0_pc <= io_in_bits_pc; + mem_0_addr <= io_in_bits_addr; + mem_0_adrx <= io_in_bits_adrx; + mem_0_data <= io_in_bits_data; + mem_0_index <= io_in_bits_index; + mem_0_size <= io_in_bits_size; + mem_0_fullsize <= io_in_bits_fullsize; + mem_0_write <= io_in_bits_write; + mem_0_sext <= io_in_bits_sext; + mem_0_iload <= io_in_bits_iload; + mem_0_fencei <= io_in_bits_fencei; + mem_0_flushat <= io_in_bits_flushat; + mem_0_flushall <= io_in_bits_flushall; + mem_0_sldst <= io_in_bits_sldst; + mem_0_vldst <= io_in_bits_vldst; + mem_0_fldst <= io_in_bits_fldst; + mem_0_regionType <= io_in_bits_regionType; + mem_0_mask <= io_in_bits_mask; + mem_0_last <= io_in_bits_last; + end + if (io_out_valid_0 & io_out_ready) + opos <= opos - 1'h1; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:5]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h6; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + ipos = _RANDOM[3'h0][0]; + opos = _RANDOM[3'h0][1]; + mem_0_pc = {_RANDOM[3'h0][31:3], _RANDOM[3'h1][2:0]}; + mem_0_addr = {_RANDOM[3'h1][31:3], _RANDOM[3'h2][2:0]}; + mem_0_adrx = {_RANDOM[3'h2][31:3], _RANDOM[3'h3][2:0]}; + mem_0_data = {_RANDOM[3'h3][31:3], _RANDOM[3'h4][2:0]}; + mem_0_index = _RANDOM[3'h4][7:3]; + mem_0_size = _RANDOM[3'h4][12:8]; + mem_0_fullsize = _RANDOM[3'h4][17:13]; + mem_0_write = _RANDOM[3'h4][18]; + mem_0_sext = _RANDOM[3'h4][19]; + mem_0_iload = _RANDOM[3'h4][20]; + mem_0_fencei = _RANDOM[3'h4][21]; + mem_0_flushat = _RANDOM[3'h4][22]; + mem_0_flushall = _RANDOM[3'h4][23]; + mem_0_sldst = _RANDOM[3'h4][24]; + mem_0_vldst = _RANDOM[3'h4][25]; + mem_0_fldst = _RANDOM[3'h4][26]; + mem_0_regionType = _RANDOM[3'h4][28:27]; + mem_0_mask = {_RANDOM[3'h4][31:29], _RANDOM[3'h5][12:0]}; + mem_0_last = _RANDOM[3'h5][13]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ipos = 1'h0; + opos = 1'h0; + mem_0_pc = 32'h0; + mem_0_addr = 32'h0; + mem_0_adrx = 32'h0; + mem_0_data = 32'h0; + mem_0_index = 5'h0; + mem_0_size = 5'h0; + mem_0_fullsize = 5'h0; + mem_0_write = 1'h0; + mem_0_sext = 1'h0; + mem_0_iload = 1'h0; + mem_0_fencei = 1'h0; + mem_0_flushat = 1'h0; + mem_0_flushall = 1'h0; + mem_0_sldst = 1'h0; + mem_0_vldst = 1'h0; + mem_0_fldst = 1'h0; + mem_0_regionType = 2'h0; + mem_0_mask = 16'h0; + mem_0_last = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_in_ready = io_in_ready_0; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_pc = mem_0_pc; + assign io_out_bits_addr = mem_0_addr; + assign io_out_bits_adrx = mem_0_adrx; + assign io_out_bits_data = mem_0_data; + assign io_out_bits_index = mem_0_index; + assign io_out_bits_size = mem_0_size; + assign io_out_bits_fullsize = mem_0_fullsize; + assign io_out_bits_write = mem_0_write; + assign io_out_bits_sext = mem_0_sext; + assign io_out_bits_iload = mem_0_iload; + assign io_out_bits_fencei = mem_0_fencei; + assign io_out_bits_flushat = mem_0_flushat; + assign io_out_bits_flushall = mem_0_flushall; + assign io_out_bits_sldst = mem_0_sldst; + assign io_out_bits_vldst = mem_0_vldst; + assign io_out_bits_fldst = mem_0_fldst; + assign io_out_bits_regionType = mem_0_regionType; + assign io_out_bits_mask = mem_0_mask; + assign io_out_bits_last = mem_0_last; +endmodule + +module FifoX( + input clock, + reset, + io_in_valid, + io_in_bits_0_valid, + input [31:0] io_in_bits_0_bits_pc, + io_in_bits_0_bits_addr, + io_in_bits_0_bits_adrx, + io_in_bits_0_bits_data, + input [4:0] io_in_bits_0_bits_index, + io_in_bits_0_bits_size, + io_in_bits_0_bits_fullsize, + input io_in_bits_0_bits_write, + io_in_bits_0_bits_sext, + io_in_bits_0_bits_iload, + io_in_bits_0_bits_fencei, + io_in_bits_0_bits_flushat, + io_in_bits_0_bits_flushall, + io_in_bits_0_bits_sldst, + io_in_bits_0_bits_vldst, + io_in_bits_0_bits_fldst, + input [1:0] io_in_bits_0_bits_regionType, + input [15:0] io_in_bits_0_bits_mask, + input io_in_bits_1_valid, + input [31:0] io_in_bits_1_bits_pc, + io_in_bits_1_bits_addr, + io_in_bits_1_bits_adrx, + io_in_bits_1_bits_data, + input [4:0] io_in_bits_1_bits_index, + io_in_bits_1_bits_size, + io_in_bits_1_bits_fullsize, + input io_in_bits_1_bits_write, + io_in_bits_1_bits_sext, + io_in_bits_1_bits_iload, + io_in_bits_1_bits_fencei, + io_in_bits_1_bits_flushat, + io_in_bits_1_bits_flushall, + io_in_bits_1_bits_sldst, + io_in_bits_1_bits_vldst, + io_in_bits_1_bits_fldst, + input [1:0] io_in_bits_1_bits_regionType, + input [15:0] io_in_bits_1_bits_mask, + input io_in_bits_2_valid, + input [31:0] io_in_bits_2_bits_pc, + io_in_bits_2_bits_addr, + io_in_bits_2_bits_adrx, + io_in_bits_2_bits_data, + input [4:0] io_in_bits_2_bits_index, + io_in_bits_2_bits_size, + io_in_bits_2_bits_fullsize, + input io_in_bits_2_bits_write, + io_in_bits_2_bits_sext, + io_in_bits_2_bits_iload, + io_in_bits_2_bits_fencei, + io_in_bits_2_bits_flushat, + io_in_bits_2_bits_flushall, + io_in_bits_2_bits_sldst, + io_in_bits_2_bits_vldst, + io_in_bits_2_bits_fldst, + input [1:0] io_in_bits_2_bits_regionType, + input [15:0] io_in_bits_2_bits_mask, + input io_in_bits_3_valid, + input [31:0] io_in_bits_3_bits_pc, + io_in_bits_3_bits_addr, + io_in_bits_3_bits_adrx, + io_in_bits_3_bits_data, + input [4:0] io_in_bits_3_bits_index, + io_in_bits_3_bits_size, + io_in_bits_3_bits_fullsize, + input io_in_bits_3_bits_write, + io_in_bits_3_bits_sext, + io_in_bits_3_bits_iload, + io_in_bits_3_bits_fencei, + io_in_bits_3_bits_flushat, + io_in_bits_3_bits_flushall, + io_in_bits_3_bits_sldst, + io_in_bits_3_bits_vldst, + io_in_bits_3_bits_fldst, + input [1:0] io_in_bits_3_bits_regionType, + input [15:0] io_in_bits_3_bits_mask, + input io_in_bits_4_valid, + input [31:0] io_in_bits_4_bits_pc, + io_in_bits_4_bits_addr, + io_in_bits_4_bits_adrx, + io_in_bits_4_bits_data, + input [4:0] io_in_bits_4_bits_index, + io_in_bits_4_bits_size, + io_in_bits_4_bits_fullsize, + input io_in_bits_4_bits_write, + io_in_bits_4_bits_sext, + io_in_bits_4_bits_iload, + io_in_bits_4_bits_fencei, + io_in_bits_4_bits_flushat, + io_in_bits_4_bits_flushall, + io_in_bits_4_bits_sldst, + io_in_bits_4_bits_vldst, + io_in_bits_4_bits_fldst, + input [1:0] io_in_bits_4_bits_regionType, + input [15:0] io_in_bits_4_bits_mask, + input io_in_bits_5_valid, + input [31:0] io_in_bits_5_bits_pc, + io_in_bits_5_bits_addr, + io_in_bits_5_bits_adrx, + io_in_bits_5_bits_data, + input [4:0] io_in_bits_5_bits_index, + io_in_bits_5_bits_size, + io_in_bits_5_bits_fullsize, + input io_in_bits_5_bits_write, + io_in_bits_5_bits_sext, + io_in_bits_5_bits_iload, + io_in_bits_5_bits_fencei, + io_in_bits_5_bits_flushat, + io_in_bits_5_bits_flushall, + io_in_bits_5_bits_sldst, + io_in_bits_5_bits_vldst, + io_in_bits_5_bits_fldst, + input [1:0] io_in_bits_5_bits_regionType, + input [15:0] io_in_bits_5_bits_mask, + input io_in_bits_6_valid, + input [31:0] io_in_bits_6_bits_pc, + io_in_bits_6_bits_addr, + io_in_bits_6_bits_adrx, + io_in_bits_6_bits_data, + input [4:0] io_in_bits_6_bits_index, + io_in_bits_6_bits_size, + io_in_bits_6_bits_fullsize, + input io_in_bits_6_bits_write, + io_in_bits_6_bits_sext, + io_in_bits_6_bits_iload, + io_in_bits_6_bits_fencei, + io_in_bits_6_bits_flushat, + io_in_bits_6_bits_flushall, + io_in_bits_6_bits_sldst, + io_in_bits_6_bits_vldst, + io_in_bits_6_bits_fldst, + input [1:0] io_in_bits_6_bits_regionType, + input [15:0] io_in_bits_6_bits_mask, + input io_in_bits_7_valid, + input [31:0] io_in_bits_7_bits_pc, + io_in_bits_7_bits_addr, + io_in_bits_7_bits_adrx, + io_in_bits_7_bits_data, + input [4:0] io_in_bits_7_bits_index, + io_in_bits_7_bits_size, + io_in_bits_7_bits_fullsize, + input io_in_bits_7_bits_write, + io_in_bits_7_bits_sext, + io_in_bits_7_bits_iload, + io_in_bits_7_bits_fencei, + io_in_bits_7_bits_flushat, + io_in_bits_7_bits_flushall, + io_in_bits_7_bits_sldst, + io_in_bits_7_bits_vldst, + io_in_bits_7_bits_fldst, + input [1:0] io_in_bits_7_bits_regionType, + input [15:0] io_in_bits_7_bits_mask, + input io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_pc, + io_out_bits_addr, + io_out_bits_adrx, + io_out_bits_data, + output [4:0] io_out_bits_index, + io_out_bits_size, + io_out_bits_fullsize, + output io_out_bits_write, + io_out_bits_sext, + io_out_bits_iload, + io_out_bits_fencei, + io_out_bits_flushat, + io_out_bits_flushall, + io_out_bits_sldst, + io_out_bits_vldst, + io_out_bits_fldst, + output [1:0] io_out_bits_regionType, + output [15:0] io_out_bits_mask, + output io_out_bits_last, + output [3:0] io_count +); + + wire io_in_ready; + wire _mslice_io_in_ready; + wire _mslice_io_out_valid; + wire [7:0] _GEN = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + reg [31:0] mem_0_pc; + reg [31:0] mem_0_addr; + reg [31:0] mem_0_adrx; + reg [31:0] mem_0_data; + reg [4:0] mem_0_index; + reg [4:0] mem_0_size; + reg [4:0] mem_0_fullsize; + reg mem_0_write; + reg mem_0_sext; + reg mem_0_iload; + reg mem_0_fencei; + reg mem_0_flushat; + reg mem_0_flushall; + reg mem_0_sldst; + reg mem_0_vldst; + reg mem_0_fldst; + reg [1:0] mem_0_regionType; + reg [15:0] mem_0_mask; + reg mem_0_last; + reg [31:0] mem_1_pc; + reg [31:0] mem_1_addr; + reg [31:0] mem_1_adrx; + reg [31:0] mem_1_data; + reg [4:0] mem_1_index; + reg [4:0] mem_1_size; + reg [4:0] mem_1_fullsize; + reg mem_1_write; + reg mem_1_sext; + reg mem_1_iload; + reg mem_1_fencei; + reg mem_1_flushat; + reg mem_1_flushall; + reg mem_1_sldst; + reg mem_1_vldst; + reg mem_1_fldst; + reg [1:0] mem_1_regionType; + reg [15:0] mem_1_mask; + reg mem_1_last; + reg [31:0] mem_2_pc; + reg [31:0] mem_2_addr; + reg [31:0] mem_2_adrx; + reg [31:0] mem_2_data; + reg [4:0] mem_2_index; + reg [4:0] mem_2_size; + reg [4:0] mem_2_fullsize; + reg mem_2_write; + reg mem_2_sext; + reg mem_2_iload; + reg mem_2_fencei; + reg mem_2_flushat; + reg mem_2_flushall; + reg mem_2_sldst; + reg mem_2_vldst; + reg mem_2_fldst; + reg [1:0] mem_2_regionType; + reg [15:0] mem_2_mask; + reg mem_2_last; + reg [31:0] mem_3_pc; + reg [31:0] mem_3_addr; + reg [31:0] mem_3_adrx; + reg [31:0] mem_3_data; + reg [4:0] mem_3_index; + reg [4:0] mem_3_size; + reg [4:0] mem_3_fullsize; + reg mem_3_write; + reg mem_3_sext; + reg mem_3_iload; + reg mem_3_fencei; + reg mem_3_flushat; + reg mem_3_flushall; + reg mem_3_sldst; + reg mem_3_vldst; + reg mem_3_fldst; + reg [1:0] mem_3_regionType; + reg [15:0] mem_3_mask; + reg mem_3_last; + reg [31:0] mem_4_pc; + reg [31:0] mem_4_addr; + reg [31:0] mem_4_adrx; + reg [31:0] mem_4_data; + reg [4:0] mem_4_index; + reg [4:0] mem_4_size; + reg [4:0] mem_4_fullsize; + reg mem_4_write; + reg mem_4_sext; + reg mem_4_iload; + reg mem_4_fencei; + reg mem_4_flushat; + reg mem_4_flushall; + reg mem_4_sldst; + reg mem_4_vldst; + reg mem_4_fldst; + reg [1:0] mem_4_regionType; + reg [15:0] mem_4_mask; + reg mem_4_last; + reg [31:0] mem_5_pc; + reg [31:0] mem_5_addr; + reg [31:0] mem_5_adrx; + reg [31:0] mem_5_data; + reg [4:0] mem_5_index; + reg [4:0] mem_5_size; + reg [4:0] mem_5_fullsize; + reg mem_5_write; + reg mem_5_sext; + reg mem_5_iload; + reg mem_5_fencei; + reg mem_5_flushat; + reg mem_5_flushall; + reg mem_5_sldst; + reg mem_5_vldst; + reg mem_5_fldst; + reg [1:0] mem_5_regionType; + reg [15:0] mem_5_mask; + reg mem_5_last; + reg [31:0] mem_6_pc; + reg [31:0] mem_6_addr; + reg [31:0] mem_6_adrx; + reg [31:0] mem_6_data; + reg [4:0] mem_6_index; + reg [4:0] mem_6_size; + reg [4:0] mem_6_fullsize; + reg mem_6_write; + reg mem_6_sext; + reg mem_6_iload; + reg mem_6_fencei; + reg mem_6_flushat; + reg mem_6_flushall; + reg mem_6_sldst; + reg mem_6_vldst; + reg mem_6_fldst; + reg [1:0] mem_6_regionType; + reg [15:0] mem_6_mask; + reg mem_6_last; + reg [31:0] mem_7_pc; + reg [31:0] mem_7_addr; + reg [31:0] mem_7_adrx; + reg [31:0] mem_7_data; + reg [4:0] mem_7_index; + reg [4:0] mem_7_size; + reg [4:0] mem_7_fullsize; + reg mem_7_write; + reg mem_7_sext; + reg mem_7_iload; + reg mem_7_fencei; + reg mem_7_flushat; + reg mem_7_flushall; + reg mem_7_sldst; + reg mem_7_vldst; + reg mem_7_fldst; + reg [1:0] mem_7_regionType; + reg [15:0] mem_7_mask; + reg mem_7_last; + reg [2:0] inxpos_0; + reg [2:0] inxpos_1; + reg [2:0] inxpos_2; + reg [2:0] inxpos_3; + reg [2:0] inxpos_4; + reg [2:0] inxpos_5; + reg [2:0] inxpos_6; + reg [2:0] inxpos_7; + reg [3:0] outpos; + reg [3:0] mcount; + wire ivalid = io_in_valid & io_in_ready; + wire [1:0] _GEN_0 = {1'h0, io_in_bits_0_valid}; + wire [1:0] _GEN_1 = {1'h0, io_in_bits_1_valid}; + wire [1:0] _GEN_2 = {1'h0, io_in_bits_2_valid}; + wire [1:0] _GEN_3 = {1'h0, io_in_bits_3_valid}; + wire [1:0] _GEN_4 = {1'h0, io_in_bits_4_valid}; + wire [1:0] _GEN_5 = {1'h0, io_in_bits_5_valid}; + wire [1:0] _GEN_6 = {1'h0, io_in_bits_6_valid}; + wire [1:0] _GEN_7 = {1'h0, io_in_bits_7_valid}; + wire [3:0] icount = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}}; + wire [7:0][31:0] _GEN_8 = + {{io_in_bits_7_bits_pc}, + {io_in_bits_6_bits_pc}, + {io_in_bits_5_bits_pc}, + {io_in_bits_4_bits_pc}, + {io_in_bits_3_bits_pc}, + {io_in_bits_2_bits_pc}, + {io_in_bits_1_bits_pc}, + {io_in_bits_0_bits_pc}}; + wire [7:0][31:0] _GEN_9 = + {{io_in_bits_7_bits_addr}, + {io_in_bits_6_bits_addr}, + {io_in_bits_5_bits_addr}, + {io_in_bits_4_bits_addr}, + {io_in_bits_3_bits_addr}, + {io_in_bits_2_bits_addr}, + {io_in_bits_1_bits_addr}, + {io_in_bits_0_bits_addr}}; + wire [7:0][31:0] _GEN_10 = + {{io_in_bits_7_bits_adrx}, + {io_in_bits_6_bits_adrx}, + {io_in_bits_5_bits_adrx}, + {io_in_bits_4_bits_adrx}, + {io_in_bits_3_bits_adrx}, + {io_in_bits_2_bits_adrx}, + {io_in_bits_1_bits_adrx}, + {io_in_bits_0_bits_adrx}}; + wire [7:0][31:0] _GEN_11 = + {{io_in_bits_7_bits_data}, + {io_in_bits_6_bits_data}, + {io_in_bits_5_bits_data}, + {io_in_bits_4_bits_data}, + {io_in_bits_3_bits_data}, + {io_in_bits_2_bits_data}, + {io_in_bits_1_bits_data}, + {io_in_bits_0_bits_data}}; + wire [7:0][4:0] _GEN_12 = + {{io_in_bits_7_bits_index}, + {io_in_bits_6_bits_index}, + {io_in_bits_5_bits_index}, + {io_in_bits_4_bits_index}, + {io_in_bits_3_bits_index}, + {io_in_bits_2_bits_index}, + {io_in_bits_1_bits_index}, + {io_in_bits_0_bits_index}}; + wire [7:0][4:0] _GEN_13 = + {{io_in_bits_7_bits_size}, + {io_in_bits_6_bits_size}, + {io_in_bits_5_bits_size}, + {io_in_bits_4_bits_size}, + {io_in_bits_3_bits_size}, + {io_in_bits_2_bits_size}, + {io_in_bits_1_bits_size}, + {io_in_bits_0_bits_size}}; + wire [7:0][4:0] _GEN_14 = + {{io_in_bits_7_bits_fullsize}, + {io_in_bits_6_bits_fullsize}, + {io_in_bits_5_bits_fullsize}, + {io_in_bits_4_bits_fullsize}, + {io_in_bits_3_bits_fullsize}, + {io_in_bits_2_bits_fullsize}, + {io_in_bits_1_bits_fullsize}, + {io_in_bits_0_bits_fullsize}}; + wire [7:0] _GEN_15 = + {{io_in_bits_7_bits_write}, + {io_in_bits_6_bits_write}, + {io_in_bits_5_bits_write}, + {io_in_bits_4_bits_write}, + {io_in_bits_3_bits_write}, + {io_in_bits_2_bits_write}, + {io_in_bits_1_bits_write}, + {io_in_bits_0_bits_write}}; + wire [7:0] _GEN_16 = + {{io_in_bits_7_bits_sext}, + {io_in_bits_6_bits_sext}, + {io_in_bits_5_bits_sext}, + {io_in_bits_4_bits_sext}, + {io_in_bits_3_bits_sext}, + {io_in_bits_2_bits_sext}, + {io_in_bits_1_bits_sext}, + {io_in_bits_0_bits_sext}}; + wire [7:0] _GEN_17 = + {{io_in_bits_7_bits_iload}, + {io_in_bits_6_bits_iload}, + {io_in_bits_5_bits_iload}, + {io_in_bits_4_bits_iload}, + {io_in_bits_3_bits_iload}, + {io_in_bits_2_bits_iload}, + {io_in_bits_1_bits_iload}, + {io_in_bits_0_bits_iload}}; + wire [7:0] _GEN_18 = + {{io_in_bits_7_bits_fencei}, + {io_in_bits_6_bits_fencei}, + {io_in_bits_5_bits_fencei}, + {io_in_bits_4_bits_fencei}, + {io_in_bits_3_bits_fencei}, + {io_in_bits_2_bits_fencei}, + {io_in_bits_1_bits_fencei}, + {io_in_bits_0_bits_fencei}}; + wire [7:0] _GEN_19 = + {{io_in_bits_7_bits_flushat}, + {io_in_bits_6_bits_flushat}, + {io_in_bits_5_bits_flushat}, + {io_in_bits_4_bits_flushat}, + {io_in_bits_3_bits_flushat}, + {io_in_bits_2_bits_flushat}, + {io_in_bits_1_bits_flushat}, + {io_in_bits_0_bits_flushat}}; + wire [7:0] _GEN_20 = + {{io_in_bits_7_bits_flushall}, + {io_in_bits_6_bits_flushall}, + {io_in_bits_5_bits_flushall}, + {io_in_bits_4_bits_flushall}, + {io_in_bits_3_bits_flushall}, + {io_in_bits_2_bits_flushall}, + {io_in_bits_1_bits_flushall}, + {io_in_bits_0_bits_flushall}}; + wire [7:0] _GEN_21 = + {{io_in_bits_7_bits_sldst}, + {io_in_bits_6_bits_sldst}, + {io_in_bits_5_bits_sldst}, + {io_in_bits_4_bits_sldst}, + {io_in_bits_3_bits_sldst}, + {io_in_bits_2_bits_sldst}, + {io_in_bits_1_bits_sldst}, + {io_in_bits_0_bits_sldst}}; + wire [7:0] _GEN_22 = + {{io_in_bits_7_bits_vldst}, + {io_in_bits_6_bits_vldst}, + {io_in_bits_5_bits_vldst}, + {io_in_bits_4_bits_vldst}, + {io_in_bits_3_bits_vldst}, + {io_in_bits_2_bits_vldst}, + {io_in_bits_1_bits_vldst}, + {io_in_bits_0_bits_vldst}}; + wire [7:0] _GEN_23 = + {{io_in_bits_7_bits_fldst}, + {io_in_bits_6_bits_fldst}, + {io_in_bits_5_bits_fldst}, + {io_in_bits_4_bits_fldst}, + {io_in_bits_3_bits_fldst}, + {io_in_bits_2_bits_fldst}, + {io_in_bits_1_bits_fldst}, + {io_in_bits_0_bits_fldst}}; + wire [7:0][1:0] _GEN_24 = + {{io_in_bits_7_bits_regionType}, + {io_in_bits_6_bits_regionType}, + {io_in_bits_5_bits_regionType}, + {io_in_bits_4_bits_regionType}, + {io_in_bits_3_bits_regionType}, + {io_in_bits_2_bits_regionType}, + {io_in_bits_1_bits_regionType}, + {io_in_bits_0_bits_regionType}}; + wire [7:0][15:0] _GEN_25 = + {{io_in_bits_7_bits_mask}, + {io_in_bits_6_bits_mask}, + {io_in_bits_5_bits_mask}, + {io_in_bits_4_bits_mask}, + {io_in_bits_3_bits_mask}, + {io_in_bits_2_bits_mask}, + {io_in_bits_1_bits_mask}, + {io_in_bits_0_bits_mask}}; + wire _GEN_26 = + ivalid + & (|{io_in_bits_7_valid, + io_in_bits_6_valid, + io_in_bits_5_valid, + io_in_bits_4_valid, + io_in_bits_3_valid, + io_in_bits_2_valid, + io_in_bits_1_valid, + io_in_bits_0_valid}); + wire mslice_io_in_valid = (|mcount) ? io_out_ready : _GEN_26; + wire [15:0][31:0] _GEN_27 = + {{mem_0_pc}, + {mem_0_pc}, + {mem_0_pc}, + {mem_0_pc}, + {mem_0_pc}, + {mem_0_pc}, + {mem_0_pc}, + {32'h0}, + {mem_7_pc}, + {mem_6_pc}, + {mem_5_pc}, + {mem_4_pc}, + {mem_3_pc}, + {mem_2_pc}, + {mem_1_pc}, + {mem_0_pc}}; + wire [15:0][31:0] _GEN_28 = + {{mem_0_addr}, + {mem_0_addr}, + {mem_0_addr}, + {mem_0_addr}, + {mem_0_addr}, + {mem_0_addr}, + {mem_0_addr}, + {32'h0}, + {mem_7_addr}, + {mem_6_addr}, + {mem_5_addr}, + {mem_4_addr}, + {mem_3_addr}, + {mem_2_addr}, + {mem_1_addr}, + {mem_0_addr}}; + wire [15:0][31:0] _GEN_29 = + {{mem_0_adrx}, + {mem_0_adrx}, + {mem_0_adrx}, + {mem_0_adrx}, + {mem_0_adrx}, + {mem_0_adrx}, + {mem_0_adrx}, + {32'h0}, + {mem_7_adrx}, + {mem_6_adrx}, + {mem_5_adrx}, + {mem_4_adrx}, + {mem_3_adrx}, + {mem_2_adrx}, + {mem_1_adrx}, + {mem_0_adrx}}; + wire [15:0][31:0] _GEN_30 = + {{mem_0_data}, + {mem_0_data}, + {mem_0_data}, + {mem_0_data}, + {mem_0_data}, + {mem_0_data}, + {mem_0_data}, + {32'h0}, + {mem_7_data}, + {mem_6_data}, + {mem_5_data}, + {mem_4_data}, + {mem_3_data}, + {mem_2_data}, + {mem_1_data}, + {mem_0_data}}; + wire [15:0][4:0] _GEN_31 = + {{mem_0_index}, + {mem_0_index}, + {mem_0_index}, + {mem_0_index}, + {mem_0_index}, + {mem_0_index}, + {mem_0_index}, + {5'h0}, + {mem_7_index}, + {mem_6_index}, + {mem_5_index}, + {mem_4_index}, + {mem_3_index}, + {mem_2_index}, + {mem_1_index}, + {mem_0_index}}; + wire [15:0][4:0] _GEN_32 = + {{mem_0_size}, + {mem_0_size}, + {mem_0_size}, + {mem_0_size}, + {mem_0_size}, + {mem_0_size}, + {mem_0_size}, + {5'h0}, + {mem_7_size}, + {mem_6_size}, + {mem_5_size}, + {mem_4_size}, + {mem_3_size}, + {mem_2_size}, + {mem_1_size}, + {mem_0_size}}; + wire [15:0][4:0] _GEN_33 = + {{mem_0_fullsize}, + {mem_0_fullsize}, + {mem_0_fullsize}, + {mem_0_fullsize}, + {mem_0_fullsize}, + {mem_0_fullsize}, + {mem_0_fullsize}, + {5'h0}, + {mem_7_fullsize}, + {mem_6_fullsize}, + {mem_5_fullsize}, + {mem_4_fullsize}, + {mem_3_fullsize}, + {mem_2_fullsize}, + {mem_1_fullsize}, + {mem_0_fullsize}}; + wire [15:0] _GEN_34 = + {{mem_0_write}, + {mem_0_write}, + {mem_0_write}, + {mem_0_write}, + {mem_0_write}, + {mem_0_write}, + {mem_0_write}, + {1'h0}, + {mem_7_write}, + {mem_6_write}, + {mem_5_write}, + {mem_4_write}, + {mem_3_write}, + {mem_2_write}, + {mem_1_write}, + {mem_0_write}}; + wire [15:0] _GEN_35 = + {{mem_0_sext}, + {mem_0_sext}, + {mem_0_sext}, + {mem_0_sext}, + {mem_0_sext}, + {mem_0_sext}, + {mem_0_sext}, + {1'h0}, + {mem_7_sext}, + {mem_6_sext}, + {mem_5_sext}, + {mem_4_sext}, + {mem_3_sext}, + {mem_2_sext}, + {mem_1_sext}, + {mem_0_sext}}; + wire [15:0] _GEN_36 = + {{mem_0_iload}, + {mem_0_iload}, + {mem_0_iload}, + {mem_0_iload}, + {mem_0_iload}, + {mem_0_iload}, + {mem_0_iload}, + {1'h0}, + {mem_7_iload}, + {mem_6_iload}, + {mem_5_iload}, + {mem_4_iload}, + {mem_3_iload}, + {mem_2_iload}, + {mem_1_iload}, + {mem_0_iload}}; + wire [15:0] _GEN_37 = + {{mem_0_fencei}, + {mem_0_fencei}, + {mem_0_fencei}, + {mem_0_fencei}, + {mem_0_fencei}, + {mem_0_fencei}, + {mem_0_fencei}, + {1'h0}, + {mem_7_fencei}, + {mem_6_fencei}, + {mem_5_fencei}, + {mem_4_fencei}, + {mem_3_fencei}, + {mem_2_fencei}, + {mem_1_fencei}, + {mem_0_fencei}}; + wire [15:0] _GEN_38 = + {{mem_0_flushat}, + {mem_0_flushat}, + {mem_0_flushat}, + {mem_0_flushat}, + {mem_0_flushat}, + {mem_0_flushat}, + {mem_0_flushat}, + {1'h0}, + {mem_7_flushat}, + {mem_6_flushat}, + {mem_5_flushat}, + {mem_4_flushat}, + {mem_3_flushat}, + {mem_2_flushat}, + {mem_1_flushat}, + {mem_0_flushat}}; + wire [15:0] _GEN_39 = + {{mem_0_flushall}, + {mem_0_flushall}, + {mem_0_flushall}, + {mem_0_flushall}, + {mem_0_flushall}, + {mem_0_flushall}, + {mem_0_flushall}, + {1'h0}, + {mem_7_flushall}, + {mem_6_flushall}, + {mem_5_flushall}, + {mem_4_flushall}, + {mem_3_flushall}, + {mem_2_flushall}, + {mem_1_flushall}, + {mem_0_flushall}}; + wire [15:0] _GEN_40 = + {{mem_0_sldst}, + {mem_0_sldst}, + {mem_0_sldst}, + {mem_0_sldst}, + {mem_0_sldst}, + {mem_0_sldst}, + {mem_0_sldst}, + {1'h0}, + {mem_7_sldst}, + {mem_6_sldst}, + {mem_5_sldst}, + {mem_4_sldst}, + {mem_3_sldst}, + {mem_2_sldst}, + {mem_1_sldst}, + {mem_0_sldst}}; + wire [15:0] _GEN_41 = + {{mem_0_vldst}, + {mem_0_vldst}, + {mem_0_vldst}, + {mem_0_vldst}, + {mem_0_vldst}, + {mem_0_vldst}, + {mem_0_vldst}, + {1'h0}, + {mem_7_vldst}, + {mem_6_vldst}, + {mem_5_vldst}, + {mem_4_vldst}, + {mem_3_vldst}, + {mem_2_vldst}, + {mem_1_vldst}, + {mem_0_vldst}}; + wire [15:0] _GEN_42 = + {{mem_0_fldst}, + {mem_0_fldst}, + {mem_0_fldst}, + {mem_0_fldst}, + {mem_0_fldst}, + {mem_0_fldst}, + {mem_0_fldst}, + {1'h0}, + {mem_7_fldst}, + {mem_6_fldst}, + {mem_5_fldst}, + {mem_4_fldst}, + {mem_3_fldst}, + {mem_2_fldst}, + {mem_1_fldst}, + {mem_0_fldst}}; + wire [15:0][1:0] _GEN_43 = + {{mem_0_regionType}, + {mem_0_regionType}, + {mem_0_regionType}, + {mem_0_regionType}, + {mem_0_regionType}, + {mem_0_regionType}, + {mem_0_regionType}, + {2'h0}, + {mem_7_regionType}, + {mem_6_regionType}, + {mem_5_regionType}, + {mem_4_regionType}, + {mem_3_regionType}, + {mem_2_regionType}, + {mem_1_regionType}, + {mem_0_regionType}}; + wire [15:0][15:0] _GEN_44 = + {{mem_0_mask}, + {mem_0_mask}, + {mem_0_mask}, + {mem_0_mask}, + {mem_0_mask}, + {mem_0_mask}, + {mem_0_mask}, + {16'h0}, + {mem_7_mask}, + {mem_6_mask}, + {mem_5_mask}, + {mem_4_mask}, + {mem_3_mask}, + {mem_2_mask}, + {mem_1_mask}, + {mem_0_mask}}; + wire [15:0] _GEN_45 = + {{mem_0_last}, + {mem_0_last}, + {mem_0_last}, + {mem_0_last}, + {mem_0_last}, + {mem_0_last}, + {mem_0_last}, + {1'h0}, + {mem_7_last}, + {mem_6_last}, + {mem_5_last}, + {mem_4_last}, + {mem_3_last}, + {mem_2_last}, + {mem_1_last}, + {mem_0_last}}; + wire [2:0] idx_8 = + io_in_bits_0_valid + ? 3'h0 + : io_in_bits_1_valid + ? 3'h1 + : io_in_bits_2_valid + ? 3'h2 + : io_in_bits_3_valid + ? 3'h3 + : io_in_bits_4_valid + ? 3'h4 + : io_in_bits_5_valid ? 3'h5 : {2'h3, ~io_in_bits_6_valid}; + assign io_in_ready = mcount <= 4'h8 - icount; + wire [7:0] _GEN_46 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_47 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_48 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_49 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_50 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_51 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_52 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [7:0] _GEN_53 = '{1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0, 1'h1, 1'h0}; + wire [4:0] outpos_c = {1'h0, outpos} + 5'h1; + wire dec = mslice_io_in_valid & _mslice_io_in_ready; + wire _inxvalid_T_25 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h1 + & io_in_bits_7_valid; + wire _inxvalid_T_48 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h1 & io_in_bits_6_valid; + wire _inxvalid_T_68 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h1 + & io_in_bits_5_valid; + wire _inxvalid_T_85 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h1 + & io_in_bits_4_valid; + wire _inxvalid_T_99 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h1 & io_in_bits_3_valid; + wire _inxvalid_T_110 = + _GEN_0 + _GEN_1 + _GEN_2 == 2'h1 & io_in_bits_2_valid; + wire _inxvalid_T_118 = _GEN_0 + _GEN_1 == 2'h1 & io_in_bits_1_valid; + wire _inxvalid_T_149 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h2 + & io_in_bits_7_valid; + wire _inxvalid_T_172 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h2 & io_in_bits_6_valid; + wire _inxvalid_T_192 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h2 + & io_in_bits_5_valid; + wire _inxvalid_T_209 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h2 + & io_in_bits_4_valid; + wire _inxvalid_T_223 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h2 & io_in_bits_3_valid; + wire _inxvalid_T_234 = + _GEN_0 + _GEN_1 + _GEN_2 == 2'h2 & io_in_bits_2_valid; + wire _inxvalid_T_242 = _GEN_0 + _GEN_1 == 2'h2 & io_in_bits_1_valid; + wire _inxvalid_T_268 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h3 + & io_in_bits_7_valid; + wire _inxvalid_T_291 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h3 & io_in_bits_6_valid; + wire _inxvalid_T_311 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h3 + & io_in_bits_5_valid; + wire _inxvalid_T_328 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h3 + & io_in_bits_4_valid; + wire _inxvalid_T_342 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h3 & io_in_bits_3_valid; + wire _inxvalid_T_353 = (&(_GEN_0 + _GEN_1 + _GEN_2)) & io_in_bits_2_valid; + wire _inxvalid_T_379 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h4 + & io_in_bits_7_valid; + wire _inxvalid_T_402 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h4 & io_in_bits_6_valid; + wire _inxvalid_T_422 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h4 + & io_in_bits_5_valid; + wire _inxvalid_T_439 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h4 + & io_in_bits_4_valid; + wire _inxvalid_T_453 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3} == 3'h4 & io_in_bits_3_valid; + wire _inxvalid_T_479 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h5 + & io_in_bits_7_valid; + wire _inxvalid_T_502 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h5 & io_in_bits_6_valid; + wire _inxvalid_T_522 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h5 + & io_in_bits_5_valid; + wire _inxvalid_T_539 = + {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3 + _GEN_4} == 3'h5 + & io_in_bits_4_valid; + wire _inxvalid_T_565 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h6 + & io_in_bits_7_valid; + wire _inxvalid_T_588 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6} == 3'h6 & io_in_bits_6_valid; + wire _inxvalid_T_608 = + {1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4 + _GEN_5} == 3'h6 + & io_in_bits_5_valid; + wire _inxvalid_T_634 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h7 + & io_in_bits_7_valid; + wire _inxvalid_T_657 = + (&({1'h0, _GEN_0 + _GEN_1 + _GEN_2} + {1'h0, _GEN_3 + _GEN_4} + + {1'h0, _GEN_5 + _GEN_6})) & io_in_bits_6_valid; + wire _inxvalid_T_683 = + {1'h0, {1'h0, _GEN_0 + _GEN_1} + {1'h0, _GEN_2 + _GEN_3}} + + {1'h0, {1'h0, _GEN_4 + _GEN_5} + {1'h0, _GEN_6 + _GEN_7}} == 4'h8 + & io_in_bits_7_valid; + wire _valid_T_133 = inxpos_0 == 3'h0; + wire _valid_T_129 = inxpos_1 == 3'h0; + wire _valid_T_121 = inxpos_2 == 3'h0; + wire _valid_T_109 = inxpos_3 == 3'h0; + wire _valid_T_93 = inxpos_4 == 3'h0; + wire _valid_T_73 = inxpos_5 == 3'h0; + wire _valid_T_49 = inxpos_6 == 3'h0; + wire _valid_T_57 = + _valid_T_133 & _inxvalid_T_48 | _valid_T_129 & _inxvalid_T_172 | _valid_T_121 + & _inxvalid_T_291 | _valid_T_109 & _inxvalid_T_402 | _valid_T_93 & _inxvalid_T_502 + | _valid_T_73 & _inxvalid_T_588 | _valid_T_49 & _inxvalid_T_657; + wire _valid_T_80 = + _valid_T_133 & _inxvalid_T_68 | _valid_T_129 & _inxvalid_T_192 | _valid_T_121 + & _inxvalid_T_311 | _valid_T_109 & _inxvalid_T_422 | _valid_T_93 & _inxvalid_T_522 + | _valid_T_73 & _inxvalid_T_608; + wire _valid_T_99 = + _valid_T_133 & _inxvalid_T_85 | _valid_T_129 & _inxvalid_T_209 | _valid_T_121 + & _inxvalid_T_328 | _valid_T_109 & _inxvalid_T_439 | _valid_T_93 & _inxvalid_T_539; + wire _valid_T_114 = + _valid_T_133 & _inxvalid_T_99 | _valid_T_129 & _inxvalid_T_223 | _valid_T_121 + & _inxvalid_T_342 | _valid_T_109 & _inxvalid_T_453; + wire _valid_T_125 = + _valid_T_133 & _inxvalid_T_110 | _valid_T_129 & _inxvalid_T_234 | _valid_T_121 + & _inxvalid_T_353; + wire _valid_T_132 = + _valid_T_133 & _inxvalid_T_118 | _valid_T_129 & _inxvalid_T_242; + wire _valid_T_135 = _valid_T_133 & io_in_bits_0_valid; + wire _valid_T_269 = inxpos_0 == 3'h1; + wire _valid_T_265 = inxpos_1 == 3'h1; + wire _valid_T_257 = inxpos_2 == 3'h1; + wire _valid_T_245 = inxpos_3 == 3'h1; + wire _valid_T_229 = inxpos_4 == 3'h1; + wire _valid_T_209 = inxpos_5 == 3'h1; + wire _valid_T_185 = inxpos_6 == 3'h1; + wire _valid_T_193 = + _valid_T_269 & _inxvalid_T_48 | _valid_T_265 & _inxvalid_T_172 | _valid_T_257 + & _inxvalid_T_291 | _valid_T_245 & _inxvalid_T_402 | _valid_T_229 & _inxvalid_T_502 + | _valid_T_209 & _inxvalid_T_588 | _valid_T_185 & _inxvalid_T_657; + wire _valid_T_216 = + _valid_T_269 & _inxvalid_T_68 | _valid_T_265 & _inxvalid_T_192 | _valid_T_257 + & _inxvalid_T_311 | _valid_T_245 & _inxvalid_T_422 | _valid_T_229 & _inxvalid_T_522 + | _valid_T_209 & _inxvalid_T_608; + wire _valid_T_235 = + _valid_T_269 & _inxvalid_T_85 | _valid_T_265 & _inxvalid_T_209 | _valid_T_257 + & _inxvalid_T_328 | _valid_T_245 & _inxvalid_T_439 | _valid_T_229 & _inxvalid_T_539; + wire _valid_T_250 = + _valid_T_269 & _inxvalid_T_99 | _valid_T_265 & _inxvalid_T_223 | _valid_T_257 + & _inxvalid_T_342 | _valid_T_245 & _inxvalid_T_453; + wire _valid_T_261 = + _valid_T_269 & _inxvalid_T_110 | _valid_T_265 & _inxvalid_T_234 | _valid_T_257 + & _inxvalid_T_353; + wire _valid_T_268 = + _valid_T_269 & _inxvalid_T_118 | _valid_T_265 & _inxvalid_T_242; + wire _valid_T_271 = _valid_T_269 & io_in_bits_0_valid; + wire _valid_T_405 = inxpos_0 == 3'h2; + wire _valid_T_401 = inxpos_1 == 3'h2; + wire _valid_T_393 = inxpos_2 == 3'h2; + wire _valid_T_381 = inxpos_3 == 3'h2; + wire _valid_T_365 = inxpos_4 == 3'h2; + wire _valid_T_345 = inxpos_5 == 3'h2; + wire _valid_T_321 = inxpos_6 == 3'h2; + wire _valid_T_329 = + _valid_T_405 & _inxvalid_T_48 | _valid_T_401 & _inxvalid_T_172 | _valid_T_393 + & _inxvalid_T_291 | _valid_T_381 & _inxvalid_T_402 | _valid_T_365 & _inxvalid_T_502 + | _valid_T_345 & _inxvalid_T_588 | _valid_T_321 & _inxvalid_T_657; + wire _valid_T_352 = + _valid_T_405 & _inxvalid_T_68 | _valid_T_401 & _inxvalid_T_192 | _valid_T_393 + & _inxvalid_T_311 | _valid_T_381 & _inxvalid_T_422 | _valid_T_365 & _inxvalid_T_522 + | _valid_T_345 & _inxvalid_T_608; + wire _valid_T_371 = + _valid_T_405 & _inxvalid_T_85 | _valid_T_401 & _inxvalid_T_209 | _valid_T_393 + & _inxvalid_T_328 | _valid_T_381 & _inxvalid_T_439 | _valid_T_365 & _inxvalid_T_539; + wire _valid_T_386 = + _valid_T_405 & _inxvalid_T_99 | _valid_T_401 & _inxvalid_T_223 | _valid_T_393 + & _inxvalid_T_342 | _valid_T_381 & _inxvalid_T_453; + wire _valid_T_397 = + _valid_T_405 & _inxvalid_T_110 | _valid_T_401 & _inxvalid_T_234 | _valid_T_393 + & _inxvalid_T_353; + wire _valid_T_404 = + _valid_T_405 & _inxvalid_T_118 | _valid_T_401 & _inxvalid_T_242; + wire _valid_T_407 = _valid_T_405 & io_in_bits_0_valid; + wire _valid_T_541 = inxpos_0 == 3'h3; + wire _valid_T_537 = inxpos_1 == 3'h3; + wire _valid_T_529 = inxpos_2 == 3'h3; + wire _valid_T_517 = inxpos_3 == 3'h3; + wire _valid_T_501 = inxpos_4 == 3'h3; + wire _valid_T_481 = inxpos_5 == 3'h3; + wire _valid_T_457 = inxpos_6 == 3'h3; + wire _valid_T_465 = + _valid_T_541 & _inxvalid_T_48 | _valid_T_537 & _inxvalid_T_172 | _valid_T_529 + & _inxvalid_T_291 | _valid_T_517 & _inxvalid_T_402 | _valid_T_501 & _inxvalid_T_502 + | _valid_T_481 & _inxvalid_T_588 | _valid_T_457 & _inxvalid_T_657; + wire _valid_T_488 = + _valid_T_541 & _inxvalid_T_68 | _valid_T_537 & _inxvalid_T_192 | _valid_T_529 + & _inxvalid_T_311 | _valid_T_517 & _inxvalid_T_422 | _valid_T_501 & _inxvalid_T_522 + | _valid_T_481 & _inxvalid_T_608; + wire _valid_T_507 = + _valid_T_541 & _inxvalid_T_85 | _valid_T_537 & _inxvalid_T_209 | _valid_T_529 + & _inxvalid_T_328 | _valid_T_517 & _inxvalid_T_439 | _valid_T_501 & _inxvalid_T_539; + wire _valid_T_522 = + _valid_T_541 & _inxvalid_T_99 | _valid_T_537 & _inxvalid_T_223 | _valid_T_529 + & _inxvalid_T_342 | _valid_T_517 & _inxvalid_T_453; + wire _valid_T_533 = + _valid_T_541 & _inxvalid_T_110 | _valid_T_537 & _inxvalid_T_234 | _valid_T_529 + & _inxvalid_T_353; + wire _valid_T_540 = + _valid_T_541 & _inxvalid_T_118 | _valid_T_537 & _inxvalid_T_242; + wire _valid_T_543 = _valid_T_541 & io_in_bits_0_valid; + wire _valid_T_677 = inxpos_0 == 3'h4; + wire _valid_T_673 = inxpos_1 == 3'h4; + wire _valid_T_665 = inxpos_2 == 3'h4; + wire _valid_T_653 = inxpos_3 == 3'h4; + wire _valid_T_637 = inxpos_4 == 3'h4; + wire _valid_T_617 = inxpos_5 == 3'h4; + wire _valid_T_593 = inxpos_6 == 3'h4; + wire _valid_T_601 = + _valid_T_677 & _inxvalid_T_48 | _valid_T_673 & _inxvalid_T_172 | _valid_T_665 + & _inxvalid_T_291 | _valid_T_653 & _inxvalid_T_402 | _valid_T_637 & _inxvalid_T_502 + | _valid_T_617 & _inxvalid_T_588 | _valid_T_593 & _inxvalid_T_657; + wire _valid_T_624 = + _valid_T_677 & _inxvalid_T_68 | _valid_T_673 & _inxvalid_T_192 | _valid_T_665 + & _inxvalid_T_311 | _valid_T_653 & _inxvalid_T_422 | _valid_T_637 & _inxvalid_T_522 + | _valid_T_617 & _inxvalid_T_608; + wire _valid_T_643 = + _valid_T_677 & _inxvalid_T_85 | _valid_T_673 & _inxvalid_T_209 | _valid_T_665 + & _inxvalid_T_328 | _valid_T_653 & _inxvalid_T_439 | _valid_T_637 & _inxvalid_T_539; + wire _valid_T_658 = + _valid_T_677 & _inxvalid_T_99 | _valid_T_673 & _inxvalid_T_223 | _valid_T_665 + & _inxvalid_T_342 | _valid_T_653 & _inxvalid_T_453; + wire _valid_T_669 = + _valid_T_677 & _inxvalid_T_110 | _valid_T_673 & _inxvalid_T_234 | _valid_T_665 + & _inxvalid_T_353; + wire _valid_T_676 = + _valid_T_677 & _inxvalid_T_118 | _valid_T_673 & _inxvalid_T_242; + wire _valid_T_679 = _valid_T_677 & io_in_bits_0_valid; + wire _valid_T_813 = inxpos_0 == 3'h5; + wire _valid_T_809 = inxpos_1 == 3'h5; + wire _valid_T_801 = inxpos_2 == 3'h5; + wire _valid_T_789 = inxpos_3 == 3'h5; + wire _valid_T_773 = inxpos_4 == 3'h5; + wire _valid_T_753 = inxpos_5 == 3'h5; + wire _valid_T_729 = inxpos_6 == 3'h5; + wire _valid_T_737 = + _valid_T_813 & _inxvalid_T_48 | _valid_T_809 & _inxvalid_T_172 | _valid_T_801 + & _inxvalid_T_291 | _valid_T_789 & _inxvalid_T_402 | _valid_T_773 & _inxvalid_T_502 + | _valid_T_753 & _inxvalid_T_588 | _valid_T_729 & _inxvalid_T_657; + wire _valid_T_760 = + _valid_T_813 & _inxvalid_T_68 | _valid_T_809 & _inxvalid_T_192 | _valid_T_801 + & _inxvalid_T_311 | _valid_T_789 & _inxvalid_T_422 | _valid_T_773 & _inxvalid_T_522 + | _valid_T_753 & _inxvalid_T_608; + wire _valid_T_779 = + _valid_T_813 & _inxvalid_T_85 | _valid_T_809 & _inxvalid_T_209 | _valid_T_801 + & _inxvalid_T_328 | _valid_T_789 & _inxvalid_T_439 | _valid_T_773 & _inxvalid_T_539; + wire _valid_T_794 = + _valid_T_813 & _inxvalid_T_99 | _valid_T_809 & _inxvalid_T_223 | _valid_T_801 + & _inxvalid_T_342 | _valid_T_789 & _inxvalid_T_453; + wire _valid_T_805 = + _valid_T_813 & _inxvalid_T_110 | _valid_T_809 & _inxvalid_T_234 | _valid_T_801 + & _inxvalid_T_353; + wire _valid_T_812 = + _valid_T_813 & _inxvalid_T_118 | _valid_T_809 & _inxvalid_T_242; + wire _valid_T_815 = _valid_T_813 & io_in_bits_0_valid; + wire _valid_T_949 = inxpos_0 == 3'h6; + wire _valid_T_945 = inxpos_1 == 3'h6; + wire _valid_T_937 = inxpos_2 == 3'h6; + wire _valid_T_925 = inxpos_3 == 3'h6; + wire _valid_T_909 = inxpos_4 == 3'h6; + wire _valid_T_889 = inxpos_5 == 3'h6; + wire _valid_T_865 = inxpos_6 == 3'h6; + wire _valid_T_873 = + _valid_T_949 & _inxvalid_T_48 | _valid_T_945 & _inxvalid_T_172 | _valid_T_937 + & _inxvalid_T_291 | _valid_T_925 & _inxvalid_T_402 | _valid_T_909 & _inxvalid_T_502 + | _valid_T_889 & _inxvalid_T_588 | _valid_T_865 & _inxvalid_T_657; + wire _valid_T_896 = + _valid_T_949 & _inxvalid_T_68 | _valid_T_945 & _inxvalid_T_192 | _valid_T_937 + & _inxvalid_T_311 | _valid_T_925 & _inxvalid_T_422 | _valid_T_909 & _inxvalid_T_522 + | _valid_T_889 & _inxvalid_T_608; + wire _valid_T_915 = + _valid_T_949 & _inxvalid_T_85 | _valid_T_945 & _inxvalid_T_209 | _valid_T_937 + & _inxvalid_T_328 | _valid_T_925 & _inxvalid_T_439 | _valid_T_909 & _inxvalid_T_539; + wire _valid_T_930 = + _valid_T_949 & _inxvalid_T_99 | _valid_T_945 & _inxvalid_T_223 | _valid_T_937 + & _inxvalid_T_342 | _valid_T_925 & _inxvalid_T_453; + wire _valid_T_941 = + _valid_T_949 & _inxvalid_T_110 | _valid_T_945 & _inxvalid_T_234 | _valid_T_937 + & _inxvalid_T_353; + wire _valid_T_948 = + _valid_T_949 & _inxvalid_T_118 | _valid_T_945 & _inxvalid_T_242; + wire _valid_T_951 = _valid_T_949 & io_in_bits_0_valid; + wire _valid_T_1009 = + (&inxpos_0) & _inxvalid_T_48 | (&inxpos_1) & _inxvalid_T_172 | (&inxpos_2) + & _inxvalid_T_291 | (&inxpos_3) & _inxvalid_T_402 | (&inxpos_4) & _inxvalid_T_502 + | (&inxpos_5) & _inxvalid_T_588 | (&inxpos_6) & _inxvalid_T_657; + wire _valid_T_1032 = + (&inxpos_0) & _inxvalid_T_68 | (&inxpos_1) & _inxvalid_T_192 | (&inxpos_2) + & _inxvalid_T_311 | (&inxpos_3) & _inxvalid_T_422 | (&inxpos_4) & _inxvalid_T_522 + | (&inxpos_5) & _inxvalid_T_608; + wire _valid_T_1051 = + (&inxpos_0) & _inxvalid_T_85 | (&inxpos_1) & _inxvalid_T_209 | (&inxpos_2) + & _inxvalid_T_328 | (&inxpos_3) & _inxvalid_T_439 | (&inxpos_4) & _inxvalid_T_539; + wire _valid_T_1066 = + (&inxpos_0) & _inxvalid_T_99 | (&inxpos_1) & _inxvalid_T_223 | (&inxpos_2) + & _inxvalid_T_342 | (&inxpos_3) & _inxvalid_T_453; + wire _valid_T_1077 = + (&inxpos_0) & _inxvalid_T_110 | (&inxpos_1) & _inxvalid_T_234 | (&inxpos_2) + & _inxvalid_T_353; + wire _valid_T_1084 = + (&inxpos_0) & _inxvalid_T_118 | (&inxpos_1) & _inxvalid_T_242; + wire _valid_T_1087 = (&inxpos_0) & io_in_bits_0_valid; + wire [2:0] idx = + _valid_T_135 + ? 3'h0 + : _valid_T_132 + ? 3'h1 + : _valid_T_125 + ? 3'h2 + : _valid_T_114 + ? 3'h3 + : _valid_T_99 ? 3'h4 : _valid_T_80 ? 3'h5 : {2'h3, ~_valid_T_57}; + wire [2:0] idx_1 = + _valid_T_271 + ? 3'h0 + : _valid_T_268 + ? 3'h1 + : _valid_T_261 + ? 3'h2 + : _valid_T_250 + ? 3'h3 + : _valid_T_235 ? 3'h4 : _valid_T_216 ? 3'h5 : {2'h3, ~_valid_T_193}; + wire [2:0] idx_2 = + _valid_T_407 + ? 3'h0 + : _valid_T_404 + ? 3'h1 + : _valid_T_397 + ? 3'h2 + : _valid_T_386 + ? 3'h3 + : _valid_T_371 ? 3'h4 : _valid_T_352 ? 3'h5 : {2'h3, ~_valid_T_329}; + wire [2:0] idx_3 = + _valid_T_543 + ? 3'h0 + : _valid_T_540 + ? 3'h1 + : _valid_T_533 + ? 3'h2 + : _valid_T_522 + ? 3'h3 + : _valid_T_507 ? 3'h4 : _valid_T_488 ? 3'h5 : {2'h3, ~_valid_T_465}; + wire [2:0] idx_4 = + _valid_T_679 + ? 3'h0 + : _valid_T_676 + ? 3'h1 + : _valid_T_669 + ? 3'h2 + : _valid_T_658 + ? 3'h3 + : _valid_T_643 ? 3'h4 : _valid_T_624 ? 3'h5 : {2'h3, ~_valid_T_601}; + wire [2:0] idx_5 = + _valid_T_815 + ? 3'h0 + : _valid_T_812 + ? 3'h1 + : _valid_T_805 + ? 3'h2 + : _valid_T_794 + ? 3'h3 + : _valid_T_779 ? 3'h4 : _valid_T_760 ? 3'h5 : {2'h3, ~_valid_T_737}; + wire [2:0] idx_6 = + _valid_T_951 + ? 3'h0 + : _valid_T_948 + ? 3'h1 + : _valid_T_941 + ? 3'h2 + : _valid_T_930 + ? 3'h3 + : _valid_T_915 ? 3'h4 : _valid_T_896 ? 3'h5 : {2'h3, ~_valid_T_873}; + wire [2:0] idx_7 = + _valid_T_1087 + ? 3'h0 + : _valid_T_1084 + ? 3'h1 + : _valid_T_1077 + ? 3'h2 + : _valid_T_1066 + ? 3'h3 + : _valid_T_1051 ? 3'h4 : _valid_T_1032 ? 3'h5 : {2'h3, ~_valid_T_1009}; + always @(posedge clock or posedge reset) begin + if (reset) begin + mem_0_pc <= 32'h0; + mem_0_addr <= 32'h0; + mem_0_adrx <= 32'h0; + mem_0_data <= 32'h0; + mem_0_index <= 5'h0; + mem_0_size <= 5'h0; + mem_0_fullsize <= 5'h0; + mem_0_write <= 1'h0; + mem_0_sext <= 1'h0; + mem_0_iload <= 1'h0; + mem_0_fencei <= 1'h0; + mem_0_flushat <= 1'h0; + mem_0_flushall <= 1'h0; + mem_0_sldst <= 1'h0; + mem_0_vldst <= 1'h0; + mem_0_fldst <= 1'h0; + mem_0_regionType <= 2'h0; + mem_0_mask <= 16'h0; + mem_0_last <= 1'h0; + mem_1_pc <= 32'h0; + mem_1_addr <= 32'h0; + mem_1_adrx <= 32'h0; + mem_1_data <= 32'h0; + mem_1_index <= 5'h0; + mem_1_size <= 5'h0; + mem_1_fullsize <= 5'h0; + mem_1_write <= 1'h0; + mem_1_sext <= 1'h0; + mem_1_iload <= 1'h0; + mem_1_fencei <= 1'h0; + mem_1_flushat <= 1'h0; + mem_1_flushall <= 1'h0; + mem_1_sldst <= 1'h0; + mem_1_vldst <= 1'h0; + mem_1_fldst <= 1'h0; + mem_1_regionType <= 2'h0; + mem_1_mask <= 16'h0; + mem_1_last <= 1'h0; + mem_2_pc <= 32'h0; + mem_2_addr <= 32'h0; + mem_2_adrx <= 32'h0; + mem_2_data <= 32'h0; + mem_2_index <= 5'h0; + mem_2_size <= 5'h0; + mem_2_fullsize <= 5'h0; + mem_2_write <= 1'h0; + mem_2_sext <= 1'h0; + mem_2_iload <= 1'h0; + mem_2_fencei <= 1'h0; + mem_2_flushat <= 1'h0; + mem_2_flushall <= 1'h0; + mem_2_sldst <= 1'h0; + mem_2_vldst <= 1'h0; + mem_2_fldst <= 1'h0; + mem_2_regionType <= 2'h0; + mem_2_mask <= 16'h0; + mem_2_last <= 1'h0; + mem_3_pc <= 32'h0; + mem_3_addr <= 32'h0; + mem_3_adrx <= 32'h0; + mem_3_data <= 32'h0; + mem_3_index <= 5'h0; + mem_3_size <= 5'h0; + mem_3_fullsize <= 5'h0; + mem_3_write <= 1'h0; + mem_3_sext <= 1'h0; + mem_3_iload <= 1'h0; + mem_3_fencei <= 1'h0; + mem_3_flushat <= 1'h0; + mem_3_flushall <= 1'h0; + mem_3_sldst <= 1'h0; + mem_3_vldst <= 1'h0; + mem_3_fldst <= 1'h0; + mem_3_regionType <= 2'h0; + mem_3_mask <= 16'h0; + mem_3_last <= 1'h0; + mem_4_pc <= 32'h0; + mem_4_addr <= 32'h0; + mem_4_adrx <= 32'h0; + mem_4_data <= 32'h0; + mem_4_index <= 5'h0; + mem_4_size <= 5'h0; + mem_4_fullsize <= 5'h0; + mem_4_write <= 1'h0; + mem_4_sext <= 1'h0; + mem_4_iload <= 1'h0; + mem_4_fencei <= 1'h0; + mem_4_flushat <= 1'h0; + mem_4_flushall <= 1'h0; + mem_4_sldst <= 1'h0; + mem_4_vldst <= 1'h0; + mem_4_fldst <= 1'h0; + mem_4_regionType <= 2'h0; + mem_4_mask <= 16'h0; + mem_4_last <= 1'h0; + mem_5_pc <= 32'h0; + mem_5_addr <= 32'h0; + mem_5_adrx <= 32'h0; + mem_5_data <= 32'h0; + mem_5_index <= 5'h0; + mem_5_size <= 5'h0; + mem_5_fullsize <= 5'h0; + mem_5_write <= 1'h0; + mem_5_sext <= 1'h0; + mem_5_iload <= 1'h0; + mem_5_fencei <= 1'h0; + mem_5_flushat <= 1'h0; + mem_5_flushall <= 1'h0; + mem_5_sldst <= 1'h0; + mem_5_vldst <= 1'h0; + mem_5_fldst <= 1'h0; + mem_5_regionType <= 2'h0; + mem_5_mask <= 16'h0; + mem_5_last <= 1'h0; + mem_6_pc <= 32'h0; + mem_6_addr <= 32'h0; + mem_6_adrx <= 32'h0; + mem_6_data <= 32'h0; + mem_6_index <= 5'h0; + mem_6_size <= 5'h0; + mem_6_fullsize <= 5'h0; + mem_6_write <= 1'h0; + mem_6_sext <= 1'h0; + mem_6_iload <= 1'h0; + mem_6_fencei <= 1'h0; + mem_6_flushat <= 1'h0; + mem_6_flushall <= 1'h0; + mem_6_sldst <= 1'h0; + mem_6_vldst <= 1'h0; + mem_6_fldst <= 1'h0; + mem_6_regionType <= 2'h0; + mem_6_mask <= 16'h0; + mem_6_last <= 1'h0; + mem_7_pc <= 32'h0; + mem_7_addr <= 32'h0; + mem_7_adrx <= 32'h0; + mem_7_data <= 32'h0; + mem_7_index <= 5'h0; + mem_7_size <= 5'h0; + mem_7_fullsize <= 5'h0; + mem_7_write <= 1'h0; + mem_7_sext <= 1'h0; + mem_7_iload <= 1'h0; + mem_7_fencei <= 1'h0; + mem_7_flushat <= 1'h0; + mem_7_flushall <= 1'h0; + mem_7_sldst <= 1'h0; + mem_7_vldst <= 1'h0; + mem_7_fldst <= 1'h0; + mem_7_regionType <= 2'h0; + mem_7_mask <= 16'h0; + mem_7_last <= 1'h0; + inxpos_0 <= 3'h0; + inxpos_1 <= 3'h1; + inxpos_2 <= 3'h2; + inxpos_3 <= 3'h3; + inxpos_4 <= 3'h4; + inxpos_5 <= 3'h5; + inxpos_6 <= 3'h6; + inxpos_7 <= 3'h7; + outpos <= 4'h0; + mcount <= 4'h0; + end + else begin + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_135} + {1'h0, _valid_T_132}} + + {1'h0, {1'h0, _valid_T_125} + {1'h0, _valid_T_114}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_99} + {1'h0, _valid_T_80}} + + {1'h0, + {1'h0, _valid_T_57} + + {1'h0, + _valid_T_133 & _inxvalid_T_25 | _valid_T_129 & _inxvalid_T_149 + | _valid_T_121 & _inxvalid_T_268 | _valid_T_109 + & _inxvalid_T_379 | _valid_T_93 & _inxvalid_T_479 + | _valid_T_73 & _inxvalid_T_565 | _valid_T_49 + & _inxvalid_T_634 | inxpos_7 == 3'h0 + & _inxvalid_T_683}}}))) begin + mem_0_pc <= _GEN_8[idx]; + mem_0_addr <= _GEN_9[idx]; + mem_0_adrx <= _GEN_10[idx]; + mem_0_data <= _GEN_11[idx]; + mem_0_index <= _GEN_12[idx]; + mem_0_size <= _GEN_13[idx]; + mem_0_fullsize <= _GEN_14[idx]; + mem_0_write <= _GEN_15[idx]; + mem_0_sext <= _GEN_16[idx]; + mem_0_iload <= _GEN_17[idx]; + mem_0_fencei <= _GEN_18[idx]; + mem_0_flushat <= _GEN_19[idx]; + mem_0_flushall <= _GEN_20[idx]; + mem_0_sldst <= _GEN_21[idx]; + mem_0_vldst <= _GEN_22[idx]; + mem_0_fldst <= _GEN_23[idx]; + mem_0_regionType <= _GEN_24[idx]; + mem_0_mask <= _GEN_25[idx]; + mem_0_last <= _GEN_46[idx]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_271} + {1'h0, _valid_T_268}} + + {1'h0, {1'h0, _valid_T_261} + {1'h0, _valid_T_250}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_235} + {1'h0, _valid_T_216}} + + {1'h0, + {1'h0, _valid_T_193} + + {1'h0, + _valid_T_269 & _inxvalid_T_25 | _valid_T_265 & _inxvalid_T_149 + | _valid_T_257 & _inxvalid_T_268 | _valid_T_245 + & _inxvalid_T_379 | _valid_T_229 & _inxvalid_T_479 + | _valid_T_209 & _inxvalid_T_565 | _valid_T_185 + & _inxvalid_T_634 | inxpos_7 == 3'h1 + & _inxvalid_T_683}}}))) begin + mem_1_pc <= _GEN_8[idx_1]; + mem_1_addr <= _GEN_9[idx_1]; + mem_1_adrx <= _GEN_10[idx_1]; + mem_1_data <= _GEN_11[idx_1]; + mem_1_index <= _GEN_12[idx_1]; + mem_1_size <= _GEN_13[idx_1]; + mem_1_fullsize <= _GEN_14[idx_1]; + mem_1_write <= _GEN_15[idx_1]; + mem_1_sext <= _GEN_16[idx_1]; + mem_1_iload <= _GEN_17[idx_1]; + mem_1_fencei <= _GEN_18[idx_1]; + mem_1_flushat <= _GEN_19[idx_1]; + mem_1_flushall <= _GEN_20[idx_1]; + mem_1_sldst <= _GEN_21[idx_1]; + mem_1_vldst <= _GEN_22[idx_1]; + mem_1_fldst <= _GEN_23[idx_1]; + mem_1_regionType <= _GEN_24[idx_1]; + mem_1_mask <= _GEN_25[idx_1]; + mem_1_last <= _GEN_47[idx_1]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_407} + {1'h0, _valid_T_404}} + + {1'h0, {1'h0, _valid_T_397} + {1'h0, _valid_T_386}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_371} + {1'h0, _valid_T_352}} + + {1'h0, + {1'h0, _valid_T_329} + + {1'h0, + _valid_T_405 & _inxvalid_T_25 | _valid_T_401 & _inxvalid_T_149 + | _valid_T_393 & _inxvalid_T_268 | _valid_T_381 + & _inxvalid_T_379 | _valid_T_365 & _inxvalid_T_479 + | _valid_T_345 & _inxvalid_T_565 | _valid_T_321 + & _inxvalid_T_634 | inxpos_7 == 3'h2 + & _inxvalid_T_683}}}))) begin + mem_2_pc <= _GEN_8[idx_2]; + mem_2_addr <= _GEN_9[idx_2]; + mem_2_adrx <= _GEN_10[idx_2]; + mem_2_data <= _GEN_11[idx_2]; + mem_2_index <= _GEN_12[idx_2]; + mem_2_size <= _GEN_13[idx_2]; + mem_2_fullsize <= _GEN_14[idx_2]; + mem_2_write <= _GEN_15[idx_2]; + mem_2_sext <= _GEN_16[idx_2]; + mem_2_iload <= _GEN_17[idx_2]; + mem_2_fencei <= _GEN_18[idx_2]; + mem_2_flushat <= _GEN_19[idx_2]; + mem_2_flushall <= _GEN_20[idx_2]; + mem_2_sldst <= _GEN_21[idx_2]; + mem_2_vldst <= _GEN_22[idx_2]; + mem_2_fldst <= _GEN_23[idx_2]; + mem_2_regionType <= _GEN_24[idx_2]; + mem_2_mask <= _GEN_25[idx_2]; + mem_2_last <= _GEN_48[idx_2]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_543} + {1'h0, _valid_T_540}} + + {1'h0, {1'h0, _valid_T_533} + {1'h0, _valid_T_522}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_507} + {1'h0, _valid_T_488}} + + {1'h0, + {1'h0, _valid_T_465} + + {1'h0, + _valid_T_541 & _inxvalid_T_25 | _valid_T_537 & _inxvalid_T_149 + | _valid_T_529 & _inxvalid_T_268 | _valid_T_517 + & _inxvalid_T_379 | _valid_T_501 & _inxvalid_T_479 + | _valid_T_481 & _inxvalid_T_565 | _valid_T_457 + & _inxvalid_T_634 | inxpos_7 == 3'h3 + & _inxvalid_T_683}}}))) begin + mem_3_pc <= _GEN_8[idx_3]; + mem_3_addr <= _GEN_9[idx_3]; + mem_3_adrx <= _GEN_10[idx_3]; + mem_3_data <= _GEN_11[idx_3]; + mem_3_index <= _GEN_12[idx_3]; + mem_3_size <= _GEN_13[idx_3]; + mem_3_fullsize <= _GEN_14[idx_3]; + mem_3_write <= _GEN_15[idx_3]; + mem_3_sext <= _GEN_16[idx_3]; + mem_3_iload <= _GEN_17[idx_3]; + mem_3_fencei <= _GEN_18[idx_3]; + mem_3_flushat <= _GEN_19[idx_3]; + mem_3_flushall <= _GEN_20[idx_3]; + mem_3_sldst <= _GEN_21[idx_3]; + mem_3_vldst <= _GEN_22[idx_3]; + mem_3_fldst <= _GEN_23[idx_3]; + mem_3_regionType <= _GEN_24[idx_3]; + mem_3_mask <= _GEN_25[idx_3]; + mem_3_last <= _GEN_49[idx_3]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_679} + {1'h0, _valid_T_676}} + + {1'h0, {1'h0, _valid_T_669} + {1'h0, _valid_T_658}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_643} + {1'h0, _valid_T_624}} + + {1'h0, + {1'h0, _valid_T_601} + + {1'h0, + _valid_T_677 & _inxvalid_T_25 | _valid_T_673 & _inxvalid_T_149 + | _valid_T_665 & _inxvalid_T_268 | _valid_T_653 + & _inxvalid_T_379 | _valid_T_637 & _inxvalid_T_479 + | _valid_T_617 & _inxvalid_T_565 | _valid_T_593 + & _inxvalid_T_634 | inxpos_7 == 3'h4 + & _inxvalid_T_683}}}))) begin + mem_4_pc <= _GEN_8[idx_4]; + mem_4_addr <= _GEN_9[idx_4]; + mem_4_adrx <= _GEN_10[idx_4]; + mem_4_data <= _GEN_11[idx_4]; + mem_4_index <= _GEN_12[idx_4]; + mem_4_size <= _GEN_13[idx_4]; + mem_4_fullsize <= _GEN_14[idx_4]; + mem_4_write <= _GEN_15[idx_4]; + mem_4_sext <= _GEN_16[idx_4]; + mem_4_iload <= _GEN_17[idx_4]; + mem_4_fencei <= _GEN_18[idx_4]; + mem_4_flushat <= _GEN_19[idx_4]; + mem_4_flushall <= _GEN_20[idx_4]; + mem_4_sldst <= _GEN_21[idx_4]; + mem_4_vldst <= _GEN_22[idx_4]; + mem_4_fldst <= _GEN_23[idx_4]; + mem_4_regionType <= _GEN_24[idx_4]; + mem_4_mask <= _GEN_25[idx_4]; + mem_4_last <= _GEN_50[idx_4]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_815} + {1'h0, _valid_T_812}} + + {1'h0, {1'h0, _valid_T_805} + {1'h0, _valid_T_794}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_779} + {1'h0, _valid_T_760}} + + {1'h0, + {1'h0, _valid_T_737} + + {1'h0, + _valid_T_813 & _inxvalid_T_25 | _valid_T_809 & _inxvalid_T_149 + | _valid_T_801 & _inxvalid_T_268 | _valid_T_789 + & _inxvalid_T_379 | _valid_T_773 & _inxvalid_T_479 + | _valid_T_753 & _inxvalid_T_565 | _valid_T_729 + & _inxvalid_T_634 | inxpos_7 == 3'h5 + & _inxvalid_T_683}}}))) begin + mem_5_pc <= _GEN_8[idx_5]; + mem_5_addr <= _GEN_9[idx_5]; + mem_5_adrx <= _GEN_10[idx_5]; + mem_5_data <= _GEN_11[idx_5]; + mem_5_index <= _GEN_12[idx_5]; + mem_5_size <= _GEN_13[idx_5]; + mem_5_fullsize <= _GEN_14[idx_5]; + mem_5_write <= _GEN_15[idx_5]; + mem_5_sext <= _GEN_16[idx_5]; + mem_5_iload <= _GEN_17[idx_5]; + mem_5_fencei <= _GEN_18[idx_5]; + mem_5_flushat <= _GEN_19[idx_5]; + mem_5_flushall <= _GEN_20[idx_5]; + mem_5_sldst <= _GEN_21[idx_5]; + mem_5_vldst <= _GEN_22[idx_5]; + mem_5_fldst <= _GEN_23[idx_5]; + mem_5_regionType <= _GEN_24[idx_5]; + mem_5_mask <= _GEN_25[idx_5]; + mem_5_last <= _GEN_51[idx_5]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_951} + {1'h0, _valid_T_948}} + + {1'h0, {1'h0, _valid_T_941} + {1'h0, _valid_T_930}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_915} + {1'h0, _valid_T_896}} + + {1'h0, + {1'h0, _valid_T_873} + + {1'h0, + _valid_T_949 & _inxvalid_T_25 | _valid_T_945 & _inxvalid_T_149 + | _valid_T_937 & _inxvalid_T_268 | _valid_T_925 + & _inxvalid_T_379 | _valid_T_909 & _inxvalid_T_479 + | _valid_T_889 & _inxvalid_T_565 | _valid_T_865 + & _inxvalid_T_634 | inxpos_7 == 3'h6 + & _inxvalid_T_683}}}))) begin + mem_6_pc <= _GEN_8[idx_6]; + mem_6_addr <= _GEN_9[idx_6]; + mem_6_adrx <= _GEN_10[idx_6]; + mem_6_data <= _GEN_11[idx_6]; + mem_6_index <= _GEN_12[idx_6]; + mem_6_size <= _GEN_13[idx_6]; + mem_6_fullsize <= _GEN_14[idx_6]; + mem_6_write <= _GEN_15[idx_6]; + mem_6_sext <= _GEN_16[idx_6]; + mem_6_iload <= _GEN_17[idx_6]; + mem_6_fencei <= _GEN_18[idx_6]; + mem_6_flushat <= _GEN_19[idx_6]; + mem_6_flushall <= _GEN_20[idx_6]; + mem_6_sldst <= _GEN_21[idx_6]; + mem_6_vldst <= _GEN_22[idx_6]; + mem_6_fldst <= _GEN_23[idx_6]; + mem_6_regionType <= _GEN_24[idx_6]; + mem_6_mask <= _GEN_25[idx_6]; + mem_6_last <= _GEN_52[idx_6]; + end + if (ivalid + & (|({1'h0, + {1'h0, {1'h0, _valid_T_1087} + {1'h0, _valid_T_1084}} + + {1'h0, {1'h0, _valid_T_1077} + {1'h0, _valid_T_1066}}} + + {1'h0, + {1'h0, {1'h0, _valid_T_1051} + {1'h0, _valid_T_1032}} + + {1'h0, + {1'h0, _valid_T_1009} + + {1'h0, + (&inxpos_0) & _inxvalid_T_25 | (&inxpos_1) & _inxvalid_T_149 + | (&inxpos_2) & _inxvalid_T_268 | (&inxpos_3) + & _inxvalid_T_379 | (&inxpos_4) & _inxvalid_T_479 + | (&inxpos_5) & _inxvalid_T_565 | (&inxpos_6) + & _inxvalid_T_634 | (&inxpos_7) + & _inxvalid_T_683}}}))) begin + mem_7_pc <= _GEN_8[idx_7]; + mem_7_addr <= _GEN_9[idx_7]; + mem_7_adrx <= _GEN_10[idx_7]; + mem_7_data <= _GEN_11[idx_7]; + mem_7_index <= _GEN_12[idx_7]; + mem_7_size <= _GEN_13[idx_7]; + mem_7_fullsize <= _GEN_14[idx_7]; + mem_7_write <= _GEN_15[idx_7]; + mem_7_sext <= _GEN_16[idx_7]; + mem_7_iload <= _GEN_17[idx_7]; + mem_7_fencei <= _GEN_18[idx_7]; + mem_7_flushat <= _GEN_19[idx_7]; + mem_7_flushall <= _GEN_20[idx_7]; + mem_7_sldst <= _GEN_21[idx_7]; + mem_7_vldst <= _GEN_22[idx_7]; + mem_7_fldst <= _GEN_23[idx_7]; + mem_7_regionType <= _GEN_24[idx_7]; + mem_7_mask <= _GEN_25[idx_7]; + mem_7_last <= _GEN_53[idx_7]; + end + if (ivalid) begin + inxpos_0 <= inxpos_0 + icount[2:0]; + inxpos_1 <= inxpos_1 + icount[2:0]; + inxpos_2 <= inxpos_2 + icount[2:0]; + inxpos_3 <= inxpos_3 + icount[2:0]; + inxpos_4 <= inxpos_4 + icount[2:0]; + inxpos_5 <= inxpos_5 + icount[2:0]; + inxpos_6 <= inxpos_6 + icount[2:0]; + inxpos_7 <= inxpos_7 + icount[2:0]; + end + if (dec) + outpos <= outpos_c < 5'h8 ? outpos_c[3:0] : outpos - 4'h7; + if (ivalid | dec) + mcount <= mcount + (ivalid ? icount : 4'h0) - {3'h0, dec}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:49]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [5:0] i = 6'h0; i < 6'h32; i += 6'h1) begin + _RANDOM[i] = `RANDOM; + end + mem_0_pc = _RANDOM[6'h0]; + mem_0_addr = _RANDOM[6'h1]; + mem_0_adrx = _RANDOM[6'h2]; + mem_0_data = _RANDOM[6'h3]; + mem_0_index = _RANDOM[6'h4][4:0]; + mem_0_size = _RANDOM[6'h4][9:5]; + mem_0_fullsize = _RANDOM[6'h4][14:10]; + mem_0_write = _RANDOM[6'h4][15]; + mem_0_sext = _RANDOM[6'h4][16]; + mem_0_iload = _RANDOM[6'h4][17]; + mem_0_fencei = _RANDOM[6'h4][18]; + mem_0_flushat = _RANDOM[6'h4][19]; + mem_0_flushall = _RANDOM[6'h4][20]; + mem_0_sldst = _RANDOM[6'h4][21]; + mem_0_vldst = _RANDOM[6'h4][22]; + mem_0_fldst = _RANDOM[6'h4][23]; + mem_0_regionType = _RANDOM[6'h4][25:24]; + mem_0_mask = {_RANDOM[6'h4][31:26], _RANDOM[6'h5][9:0]}; + mem_0_last = _RANDOM[6'h5][10]; + mem_1_pc = {_RANDOM[6'h5][31:11], _RANDOM[6'h6][10:0]}; + mem_1_addr = {_RANDOM[6'h6][31:11], _RANDOM[6'h7][10:0]}; + mem_1_adrx = {_RANDOM[6'h7][31:11], _RANDOM[6'h8][10:0]}; + mem_1_data = {_RANDOM[6'h8][31:11], _RANDOM[6'h9][10:0]}; + mem_1_index = _RANDOM[6'h9][15:11]; + mem_1_size = _RANDOM[6'h9][20:16]; + mem_1_fullsize = _RANDOM[6'h9][25:21]; + mem_1_write = _RANDOM[6'h9][26]; + mem_1_sext = _RANDOM[6'h9][27]; + mem_1_iload = _RANDOM[6'h9][28]; + mem_1_fencei = _RANDOM[6'h9][29]; + mem_1_flushat = _RANDOM[6'h9][30]; + mem_1_flushall = _RANDOM[6'h9][31]; + mem_1_sldst = _RANDOM[6'hA][0]; + mem_1_vldst = _RANDOM[6'hA][1]; + mem_1_fldst = _RANDOM[6'hA][2]; + mem_1_regionType = _RANDOM[6'hA][4:3]; + mem_1_mask = _RANDOM[6'hA][20:5]; + mem_1_last = _RANDOM[6'hA][21]; + mem_2_pc = {_RANDOM[6'hA][31:22], _RANDOM[6'hB][21:0]}; + mem_2_addr = {_RANDOM[6'hB][31:22], _RANDOM[6'hC][21:0]}; + mem_2_adrx = {_RANDOM[6'hC][31:22], _RANDOM[6'hD][21:0]}; + mem_2_data = {_RANDOM[6'hD][31:22], _RANDOM[6'hE][21:0]}; + mem_2_index = _RANDOM[6'hE][26:22]; + mem_2_size = _RANDOM[6'hE][31:27]; + mem_2_fullsize = _RANDOM[6'hF][4:0]; + mem_2_write = _RANDOM[6'hF][5]; + mem_2_sext = _RANDOM[6'hF][6]; + mem_2_iload = _RANDOM[6'hF][7]; + mem_2_fencei = _RANDOM[6'hF][8]; + mem_2_flushat = _RANDOM[6'hF][9]; + mem_2_flushall = _RANDOM[6'hF][10]; + mem_2_sldst = _RANDOM[6'hF][11]; + mem_2_vldst = _RANDOM[6'hF][12]; + mem_2_fldst = _RANDOM[6'hF][13]; + mem_2_regionType = _RANDOM[6'hF][15:14]; + mem_2_mask = _RANDOM[6'hF][31:16]; + mem_2_last = _RANDOM[6'h10][0]; + mem_3_pc = {_RANDOM[6'h10][31:1], _RANDOM[6'h11][0]}; + mem_3_addr = {_RANDOM[6'h11][31:1], _RANDOM[6'h12][0]}; + mem_3_adrx = {_RANDOM[6'h12][31:1], _RANDOM[6'h13][0]}; + mem_3_data = {_RANDOM[6'h13][31:1], _RANDOM[6'h14][0]}; + mem_3_index = _RANDOM[6'h14][5:1]; + mem_3_size = _RANDOM[6'h14][10:6]; + mem_3_fullsize = _RANDOM[6'h14][15:11]; + mem_3_write = _RANDOM[6'h14][16]; + mem_3_sext = _RANDOM[6'h14][17]; + mem_3_iload = _RANDOM[6'h14][18]; + mem_3_fencei = _RANDOM[6'h14][19]; + mem_3_flushat = _RANDOM[6'h14][20]; + mem_3_flushall = _RANDOM[6'h14][21]; + mem_3_sldst = _RANDOM[6'h14][22]; + mem_3_vldst = _RANDOM[6'h14][23]; + mem_3_fldst = _RANDOM[6'h14][24]; + mem_3_regionType = _RANDOM[6'h14][26:25]; + mem_3_mask = {_RANDOM[6'h14][31:27], _RANDOM[6'h15][10:0]}; + mem_3_last = _RANDOM[6'h15][11]; + mem_4_pc = {_RANDOM[6'h15][31:12], _RANDOM[6'h16][11:0]}; + mem_4_addr = {_RANDOM[6'h16][31:12], _RANDOM[6'h17][11:0]}; + mem_4_adrx = {_RANDOM[6'h17][31:12], _RANDOM[6'h18][11:0]}; + mem_4_data = {_RANDOM[6'h18][31:12], _RANDOM[6'h19][11:0]}; + mem_4_index = _RANDOM[6'h19][16:12]; + mem_4_size = _RANDOM[6'h19][21:17]; + mem_4_fullsize = _RANDOM[6'h19][26:22]; + mem_4_write = _RANDOM[6'h19][27]; + mem_4_sext = _RANDOM[6'h19][28]; + mem_4_iload = _RANDOM[6'h19][29]; + mem_4_fencei = _RANDOM[6'h19][30]; + mem_4_flushat = _RANDOM[6'h19][31]; + mem_4_flushall = _RANDOM[6'h1A][0]; + mem_4_sldst = _RANDOM[6'h1A][1]; + mem_4_vldst = _RANDOM[6'h1A][2]; + mem_4_fldst = _RANDOM[6'h1A][3]; + mem_4_regionType = _RANDOM[6'h1A][5:4]; + mem_4_mask = _RANDOM[6'h1A][21:6]; + mem_4_last = _RANDOM[6'h1A][22]; + mem_5_pc = {_RANDOM[6'h1A][31:23], _RANDOM[6'h1B][22:0]}; + mem_5_addr = {_RANDOM[6'h1B][31:23], _RANDOM[6'h1C][22:0]}; + mem_5_adrx = {_RANDOM[6'h1C][31:23], _RANDOM[6'h1D][22:0]}; + mem_5_data = {_RANDOM[6'h1D][31:23], _RANDOM[6'h1E][22:0]}; + mem_5_index = _RANDOM[6'h1E][27:23]; + mem_5_size = {_RANDOM[6'h1E][31:28], _RANDOM[6'h1F][0]}; + mem_5_fullsize = _RANDOM[6'h1F][5:1]; + mem_5_write = _RANDOM[6'h1F][6]; + mem_5_sext = _RANDOM[6'h1F][7]; + mem_5_iload = _RANDOM[6'h1F][8]; + mem_5_fencei = _RANDOM[6'h1F][9]; + mem_5_flushat = _RANDOM[6'h1F][10]; + mem_5_flushall = _RANDOM[6'h1F][11]; + mem_5_sldst = _RANDOM[6'h1F][12]; + mem_5_vldst = _RANDOM[6'h1F][13]; + mem_5_fldst = _RANDOM[6'h1F][14]; + mem_5_regionType = _RANDOM[6'h1F][16:15]; + mem_5_mask = {_RANDOM[6'h1F][31:17], _RANDOM[6'h20][0]}; + mem_5_last = _RANDOM[6'h20][1]; + mem_6_pc = {_RANDOM[6'h20][31:2], _RANDOM[6'h21][1:0]}; + mem_6_addr = {_RANDOM[6'h21][31:2], _RANDOM[6'h22][1:0]}; + mem_6_adrx = {_RANDOM[6'h22][31:2], _RANDOM[6'h23][1:0]}; + mem_6_data = {_RANDOM[6'h23][31:2], _RANDOM[6'h24][1:0]}; + mem_6_index = _RANDOM[6'h24][6:2]; + mem_6_size = _RANDOM[6'h24][11:7]; + mem_6_fullsize = _RANDOM[6'h24][16:12]; + mem_6_write = _RANDOM[6'h24][17]; + mem_6_sext = _RANDOM[6'h24][18]; + mem_6_iload = _RANDOM[6'h24][19]; + mem_6_fencei = _RANDOM[6'h24][20]; + mem_6_flushat = _RANDOM[6'h24][21]; + mem_6_flushall = _RANDOM[6'h24][22]; + mem_6_sldst = _RANDOM[6'h24][23]; + mem_6_vldst = _RANDOM[6'h24][24]; + mem_6_fldst = _RANDOM[6'h24][25]; + mem_6_regionType = _RANDOM[6'h24][27:26]; + mem_6_mask = {_RANDOM[6'h24][31:28], _RANDOM[6'h25][11:0]}; + mem_6_last = _RANDOM[6'h25][12]; + mem_7_pc = {_RANDOM[6'h25][31:13], _RANDOM[6'h26][12:0]}; + mem_7_addr = {_RANDOM[6'h26][31:13], _RANDOM[6'h27][12:0]}; + mem_7_adrx = {_RANDOM[6'h27][31:13], _RANDOM[6'h28][12:0]}; + mem_7_data = {_RANDOM[6'h28][31:13], _RANDOM[6'h29][12:0]}; + mem_7_index = _RANDOM[6'h29][17:13]; + mem_7_size = _RANDOM[6'h29][22:18]; + mem_7_fullsize = _RANDOM[6'h29][27:23]; + mem_7_write = _RANDOM[6'h29][28]; + mem_7_sext = _RANDOM[6'h29][29]; + mem_7_iload = _RANDOM[6'h29][30]; + mem_7_fencei = _RANDOM[6'h29][31]; + mem_7_flushat = _RANDOM[6'h2A][0]; + mem_7_flushall = _RANDOM[6'h2A][1]; + mem_7_sldst = _RANDOM[6'h2A][2]; + mem_7_vldst = _RANDOM[6'h2A][3]; + mem_7_fldst = _RANDOM[6'h2A][4]; + mem_7_regionType = _RANDOM[6'h2A][6:5]; + mem_7_mask = _RANDOM[6'h2A][22:7]; + mem_7_last = _RANDOM[6'h2A][23]; + inxpos_0 = _RANDOM[6'h30][5:3]; + inxpos_1 = _RANDOM[6'h30][8:6]; + inxpos_2 = _RANDOM[6'h30][11:9]; + inxpos_3 = _RANDOM[6'h30][14:12]; + inxpos_4 = _RANDOM[6'h30][17:15]; + inxpos_5 = _RANDOM[6'h30][20:18]; + inxpos_6 = _RANDOM[6'h30][23:21]; + inxpos_7 = _RANDOM[6'h30][26:24]; + outpos = _RANDOM[6'h30][30:27]; + mcount = {_RANDOM[6'h30][31], _RANDOM[6'h31][2:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + mem_0_pc = 32'h0; + mem_0_addr = 32'h0; + mem_0_adrx = 32'h0; + mem_0_data = 32'h0; + mem_0_index = 5'h0; + mem_0_size = 5'h0; + mem_0_fullsize = 5'h0; + mem_0_write = 1'h0; + mem_0_sext = 1'h0; + mem_0_iload = 1'h0; + mem_0_fencei = 1'h0; + mem_0_flushat = 1'h0; + mem_0_flushall = 1'h0; + mem_0_sldst = 1'h0; + mem_0_vldst = 1'h0; + mem_0_fldst = 1'h0; + mem_0_regionType = 2'h0; + mem_0_mask = 16'h0; + mem_0_last = 1'h0; + mem_1_pc = 32'h0; + mem_1_addr = 32'h0; + mem_1_adrx = 32'h0; + mem_1_data = 32'h0; + mem_1_index = 5'h0; + mem_1_size = 5'h0; + mem_1_fullsize = 5'h0; + mem_1_write = 1'h0; + mem_1_sext = 1'h0; + mem_1_iload = 1'h0; + mem_1_fencei = 1'h0; + mem_1_flushat = 1'h0; + mem_1_flushall = 1'h0; + mem_1_sldst = 1'h0; + mem_1_vldst = 1'h0; + mem_1_fldst = 1'h0; + mem_1_regionType = 2'h0; + mem_1_mask = 16'h0; + mem_1_last = 1'h0; + mem_2_pc = 32'h0; + mem_2_addr = 32'h0; + mem_2_adrx = 32'h0; + mem_2_data = 32'h0; + mem_2_index = 5'h0; + mem_2_size = 5'h0; + mem_2_fullsize = 5'h0; + mem_2_write = 1'h0; + mem_2_sext = 1'h0; + mem_2_iload = 1'h0; + mem_2_fencei = 1'h0; + mem_2_flushat = 1'h0; + mem_2_flushall = 1'h0; + mem_2_sldst = 1'h0; + mem_2_vldst = 1'h0; + mem_2_fldst = 1'h0; + mem_2_regionType = 2'h0; + mem_2_mask = 16'h0; + mem_2_last = 1'h0; + mem_3_pc = 32'h0; + mem_3_addr = 32'h0; + mem_3_adrx = 32'h0; + mem_3_data = 32'h0; + mem_3_index = 5'h0; + mem_3_size = 5'h0; + mem_3_fullsize = 5'h0; + mem_3_write = 1'h0; + mem_3_sext = 1'h0; + mem_3_iload = 1'h0; + mem_3_fencei = 1'h0; + mem_3_flushat = 1'h0; + mem_3_flushall = 1'h0; + mem_3_sldst = 1'h0; + mem_3_vldst = 1'h0; + mem_3_fldst = 1'h0; + mem_3_regionType = 2'h0; + mem_3_mask = 16'h0; + mem_3_last = 1'h0; + mem_4_pc = 32'h0; + mem_4_addr = 32'h0; + mem_4_adrx = 32'h0; + mem_4_data = 32'h0; + mem_4_index = 5'h0; + mem_4_size = 5'h0; + mem_4_fullsize = 5'h0; + mem_4_write = 1'h0; + mem_4_sext = 1'h0; + mem_4_iload = 1'h0; + mem_4_fencei = 1'h0; + mem_4_flushat = 1'h0; + mem_4_flushall = 1'h0; + mem_4_sldst = 1'h0; + mem_4_vldst = 1'h0; + mem_4_fldst = 1'h0; + mem_4_regionType = 2'h0; + mem_4_mask = 16'h0; + mem_4_last = 1'h0; + mem_5_pc = 32'h0; + mem_5_addr = 32'h0; + mem_5_adrx = 32'h0; + mem_5_data = 32'h0; + mem_5_index = 5'h0; + mem_5_size = 5'h0; + mem_5_fullsize = 5'h0; + mem_5_write = 1'h0; + mem_5_sext = 1'h0; + mem_5_iload = 1'h0; + mem_5_fencei = 1'h0; + mem_5_flushat = 1'h0; + mem_5_flushall = 1'h0; + mem_5_sldst = 1'h0; + mem_5_vldst = 1'h0; + mem_5_fldst = 1'h0; + mem_5_regionType = 2'h0; + mem_5_mask = 16'h0; + mem_5_last = 1'h0; + mem_6_pc = 32'h0; + mem_6_addr = 32'h0; + mem_6_adrx = 32'h0; + mem_6_data = 32'h0; + mem_6_index = 5'h0; + mem_6_size = 5'h0; + mem_6_fullsize = 5'h0; + mem_6_write = 1'h0; + mem_6_sext = 1'h0; + mem_6_iload = 1'h0; + mem_6_fencei = 1'h0; + mem_6_flushat = 1'h0; + mem_6_flushall = 1'h0; + mem_6_sldst = 1'h0; + mem_6_vldst = 1'h0; + mem_6_fldst = 1'h0; + mem_6_regionType = 2'h0; + mem_6_mask = 16'h0; + mem_6_last = 1'h0; + mem_7_pc = 32'h0; + mem_7_addr = 32'h0; + mem_7_adrx = 32'h0; + mem_7_data = 32'h0; + mem_7_index = 5'h0; + mem_7_size = 5'h0; + mem_7_fullsize = 5'h0; + mem_7_write = 1'h0; + mem_7_sext = 1'h0; + mem_7_iload = 1'h0; + mem_7_fencei = 1'h0; + mem_7_flushat = 1'h0; + mem_7_flushall = 1'h0; + mem_7_sldst = 1'h0; + mem_7_vldst = 1'h0; + mem_7_fldst = 1'h0; + mem_7_regionType = 2'h0; + mem_7_mask = 16'h0; + mem_7_last = 1'h0; + inxpos_0 = 3'h0; + inxpos_1 = 3'h1; + inxpos_2 = 3'h2; + inxpos_3 = 3'h3; + inxpos_4 = 3'h4; + inxpos_5 = 3'h5; + inxpos_6 = 3'h6; + inxpos_7 = 3'h7; + outpos = 4'h0; + mcount = 4'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Slice mslice ( + .clock (clock), + .reset (reset), + .io_in_ready (_mslice_io_in_ready), + .io_in_valid (mslice_io_in_valid), + .io_in_bits_pc + ((|mcount) ? _GEN_27[outpos] : _GEN_26 ? _GEN_8[idx_8] : io_in_bits_0_bits_pc), + .io_in_bits_addr + ((|mcount) ? _GEN_28[outpos] : _GEN_26 ? _GEN_9[idx_8] : io_in_bits_0_bits_addr), + .io_in_bits_adrx + ((|mcount) ? _GEN_29[outpos] : _GEN_26 ? _GEN_10[idx_8] : io_in_bits_0_bits_adrx), + .io_in_bits_data + ((|mcount) ? _GEN_30[outpos] : _GEN_26 ? _GEN_11[idx_8] : io_in_bits_0_bits_data), + .io_in_bits_index + ((|mcount) ? _GEN_31[outpos] : _GEN_26 ? _GEN_12[idx_8] : io_in_bits_0_bits_index), + .io_in_bits_size + ((|mcount) ? _GEN_32[outpos] : _GEN_26 ? _GEN_13[idx_8] : io_in_bits_0_bits_size), + .io_in_bits_fullsize + ((|mcount) + ? _GEN_33[outpos] + : _GEN_26 ? _GEN_14[idx_8] : io_in_bits_0_bits_fullsize), + .io_in_bits_write + ((|mcount) ? _GEN_34[outpos] : _GEN_26 ? _GEN_15[idx_8] : io_in_bits_0_bits_write), + .io_in_bits_sext + ((|mcount) ? _GEN_35[outpos] : _GEN_26 ? _GEN_16[idx_8] : io_in_bits_0_bits_sext), + .io_in_bits_iload + ((|mcount) ? _GEN_36[outpos] : _GEN_26 ? _GEN_17[idx_8] : io_in_bits_0_bits_iload), + .io_in_bits_fencei + ((|mcount) ? _GEN_37[outpos] : _GEN_26 ? _GEN_18[idx_8] : io_in_bits_0_bits_fencei), + .io_in_bits_flushat + ((|mcount) + ? _GEN_38[outpos] + : _GEN_26 ? _GEN_19[idx_8] : io_in_bits_0_bits_flushat), + .io_in_bits_flushall + ((|mcount) + ? _GEN_39[outpos] + : _GEN_26 ? _GEN_20[idx_8] : io_in_bits_0_bits_flushall), + .io_in_bits_sldst + ((|mcount) ? _GEN_40[outpos] : _GEN_26 ? _GEN_21[idx_8] : io_in_bits_0_bits_sldst), + .io_in_bits_vldst + ((|mcount) ? _GEN_41[outpos] : _GEN_26 ? _GEN_22[idx_8] : io_in_bits_0_bits_vldst), + .io_in_bits_fldst + ((|mcount) ? _GEN_42[outpos] : _GEN_26 ? _GEN_23[idx_8] : io_in_bits_0_bits_fldst), + .io_in_bits_regionType + ((|mcount) + ? _GEN_43[outpos] + : _GEN_26 ? _GEN_24[idx_8] : io_in_bits_0_bits_regionType), + .io_in_bits_mask + ((|mcount) ? _GEN_44[outpos] : _GEN_26 ? _GEN_25[idx_8] : io_in_bits_0_bits_mask), + .io_in_bits_last ((|mcount) ? _GEN_45[outpos] : _GEN_26 & _GEN[idx_8]), + .io_out_ready (io_out_ready), + .io_out_valid (_mslice_io_out_valid), + .io_out_bits_pc (io_out_bits_pc), + .io_out_bits_addr (io_out_bits_addr), + .io_out_bits_adrx (io_out_bits_adrx), + .io_out_bits_data (io_out_bits_data), + .io_out_bits_index (io_out_bits_index), + .io_out_bits_size (io_out_bits_size), + .io_out_bits_fullsize (io_out_bits_fullsize), + .io_out_bits_write (io_out_bits_write), + .io_out_bits_sext (io_out_bits_sext), + .io_out_bits_iload (io_out_bits_iload), + .io_out_bits_fencei (io_out_bits_fencei), + .io_out_bits_flushat (io_out_bits_flushat), + .io_out_bits_flushall (io_out_bits_flushall), + .io_out_bits_sldst (io_out_bits_sldst), + .io_out_bits_vldst (io_out_bits_vldst), + .io_out_bits_fldst (io_out_bits_fldst), + .io_out_bits_regionType (io_out_bits_regionType), + .io_out_bits_mask (io_out_bits_mask), + .io_out_bits_last (io_out_bits_last) + ); + assign io_out_valid = _mslice_io_out_valid; + assign io_count = mcount + {3'h0, _mslice_io_out_valid}; +endmodule + +module Slice_1( + input clock, + reset, + io_in_valid, + input [31:0] io_in_bits_addr, + input [4:0] io_in_bits_index, + io_in_bits_size, + io_in_bits_fullsize, + input io_in_bits_sext, + io_in_bits_iload, + io_in_bits_sldst, + io_in_bits_fldst, + input [1:0] io_in_bits_regionType, + input [15:0] io_in_bits_mask, + input io_in_bits_last, + output io_out_valid, + output [31:0] io_out_bits_addr, + output [4:0] io_out_bits_index, + io_out_bits_size, + io_out_bits_fullsize, + output io_out_bits_sext, + io_out_bits_iload, + io_out_bits_sldst, + io_out_bits_fldst, + output [1:0] io_out_bits_regionType, + output [15:0] io_out_bits_mask, + output io_out_bits_last, + output [1:0] io_count +); + + reg [1:0] ipos; + reg [1:0] opos; + reg [1:0] count; + reg [31:0] mem_0_addr; + reg [4:0] mem_0_index; + reg [4:0] mem_0_size; + reg [4:0] mem_0_fullsize; + reg mem_0_sext; + reg mem_0_iload; + reg mem_0_sldst; + reg mem_0_fldst; + reg [1:0] mem_0_regionType; + reg [15:0] mem_0_mask; + reg mem_0_last; + reg [31:0] mem_1_addr; + reg [4:0] mem_1_index; + reg [4:0] mem_1_size; + reg [4:0] mem_1_fullsize; + reg mem_1_sext; + reg mem_1_iload; + reg mem_1_sldst; + reg mem_1_fldst; + reg [1:0] mem_1_regionType; + reg [15:0] mem_1_mask; + reg mem_1_last; + wire io_out_valid_0 = ipos != opos; + wire full = ipos[0] == opos[0] & ipos[1] != opos[1]; + wire _GEN = io_in_valid & ~io_out_valid_0; + wire _GEN_0 = io_in_valid & io_out_valid_0; + always @(posedge clock or posedge reset) begin + if (reset) begin + ipos <= 2'h0; + opos <= 2'h0; + count <= 2'h0; + mem_0_addr <= 32'h0; + mem_0_index <= 5'h0; + mem_0_size <= 5'h0; + mem_0_fullsize <= 5'h0; + mem_0_sext <= 1'h0; + mem_0_iload <= 1'h0; + mem_0_sldst <= 1'h0; + mem_0_fldst <= 1'h0; + mem_0_regionType <= 2'h0; + mem_0_mask <= 16'h0; + mem_0_last <= 1'h0; + mem_1_addr <= 32'h0; + mem_1_index <= 5'h0; + mem_1_size <= 5'h0; + mem_1_fullsize <= 5'h0; + mem_1_sext <= 1'h0; + mem_1_iload <= 1'h0; + mem_1_sldst <= 1'h0; + mem_1_fldst <= 1'h0; + mem_1_regionType <= 2'h0; + mem_1_mask <= 16'h0; + mem_1_last <= 1'h0; + end + else begin + if (io_in_valid) + ipos <= ipos + 2'h1; + if (io_out_valid_0) + opos <= opos + 2'h1; + if (~(io_in_valid == io_out_valid_0)) + count <= count + {1'h0, io_in_valid} - {1'h0, io_out_valid_0}; + if (io_out_valid_0 & full) begin + mem_0_addr <= mem_1_addr; + mem_0_index <= mem_1_index; + mem_0_size <= mem_1_size; + mem_0_fullsize <= mem_1_fullsize; + mem_0_sext <= mem_1_sext; + mem_0_iload <= mem_1_iload; + mem_0_sldst <= mem_1_sldst; + mem_0_fldst <= mem_1_fldst; + mem_0_regionType <= mem_1_regionType; + mem_0_mask <= mem_1_mask; + mem_0_last <= mem_1_last; + end + else if (_GEN & ipos == opos | _GEN_0 & ~full) begin + mem_0_addr <= io_in_bits_addr; + mem_0_index <= io_in_bits_index; + mem_0_size <= io_in_bits_size; + mem_0_fullsize <= io_in_bits_fullsize; + mem_0_sext <= io_in_bits_sext; + mem_0_iload <= io_in_bits_iload; + mem_0_sldst <= io_in_bits_sldst; + mem_0_fldst <= io_in_bits_fldst; + mem_0_regionType <= io_in_bits_regionType; + mem_0_mask <= io_in_bits_mask; + mem_0_last <= io_in_bits_last; + end + if (_GEN & io_out_valid_0 | _GEN_0 & full) begin + mem_1_addr <= io_in_bits_addr; + mem_1_index <= io_in_bits_index; + mem_1_size <= io_in_bits_size; + mem_1_fullsize <= io_in_bits_fullsize; + mem_1_sext <= io_in_bits_sext; + mem_1_iload <= io_in_bits_iload; + mem_1_sldst <= io_in_bits_sldst; + mem_1_fldst <= io_in_bits_fldst; + mem_1_regionType <= io_in_bits_regionType; + mem_1_mask <= io_in_bits_mask; + mem_1_last <= io_in_bits_last; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:4]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + ipos = _RANDOM[3'h0][1:0]; + opos = _RANDOM[3'h0][3:2]; + count = _RANDOM[3'h0][5:4]; + mem_0_addr = {_RANDOM[3'h0][31:6], _RANDOM[3'h1][5:0]}; + mem_0_index = _RANDOM[3'h1][10:6]; + mem_0_size = _RANDOM[3'h1][15:11]; + mem_0_fullsize = _RANDOM[3'h1][20:16]; + mem_0_sext = _RANDOM[3'h1][21]; + mem_0_iload = _RANDOM[3'h1][22]; + mem_0_sldst = _RANDOM[3'h1][23]; + mem_0_fldst = _RANDOM[3'h1][24]; + mem_0_regionType = _RANDOM[3'h1][26:25]; + mem_0_mask = {_RANDOM[3'h1][31:27], _RANDOM[3'h2][10:0]}; + mem_0_last = _RANDOM[3'h2][11]; + mem_1_addr = {_RANDOM[3'h2][31:12], _RANDOM[3'h3][11:0]}; + mem_1_index = _RANDOM[3'h3][16:12]; + mem_1_size = _RANDOM[3'h3][21:17]; + mem_1_fullsize = _RANDOM[3'h3][26:22]; + mem_1_sext = _RANDOM[3'h3][27]; + mem_1_iload = _RANDOM[3'h3][28]; + mem_1_sldst = _RANDOM[3'h3][29]; + mem_1_fldst = _RANDOM[3'h3][30]; + mem_1_regionType = {_RANDOM[3'h3][31], _RANDOM[3'h4][0]}; + mem_1_mask = _RANDOM[3'h4][16:1]; + mem_1_last = _RANDOM[3'h4][17]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ipos = 2'h0; + opos = 2'h0; + count = 2'h0; + mem_0_addr = 32'h0; + mem_0_index = 5'h0; + mem_0_size = 5'h0; + mem_0_fullsize = 5'h0; + mem_0_sext = 1'h0; + mem_0_iload = 1'h0; + mem_0_sldst = 1'h0; + mem_0_fldst = 1'h0; + mem_0_regionType = 2'h0; + mem_0_mask = 16'h0; + mem_0_last = 1'h0; + mem_1_addr = 32'h0; + mem_1_index = 5'h0; + mem_1_size = 5'h0; + mem_1_fullsize = 5'h0; + mem_1_sext = 1'h0; + mem_1_iload = 1'h0; + mem_1_sldst = 1'h0; + mem_1_fldst = 1'h0; + mem_1_regionType = 2'h0; + mem_1_mask = 16'h0; + mem_1_last = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_out_valid = io_out_valid_0; + assign io_out_bits_addr = mem_0_addr; + assign io_out_bits_index = mem_0_index; + assign io_out_bits_size = mem_0_size; + assign io_out_bits_fullsize = mem_0_fullsize; + assign io_out_bits_sext = mem_0_sext; + assign io_out_bits_iload = mem_0_iload; + assign io_out_bits_sldst = mem_0_sldst; + assign io_out_bits_fldst = mem_0_fldst; + assign io_out_bits_regionType = mem_0_regionType; + assign io_out_bits_mask = mem_0_mask; + assign io_out_bits_last = mem_0_last; + assign io_count = count; +endmodule + +module LsuV1( + input clock, + reset, + output io_req_0_ready, + input io_req_0_valid, + io_req_0_bits_store, + input [4:0] io_req_0_bits_addr, + io_req_0_bits_op, + input [31:0] io_req_0_bits_pc, + output io_req_1_ready, + input io_req_1_valid, + io_req_1_bits_store, + input [4:0] io_req_1_bits_addr, + io_req_1_bits_op, + input [31:0] io_req_1_bits_pc, + output io_req_2_ready, + input io_req_2_valid, + io_req_2_bits_store, + input [4:0] io_req_2_bits_addr, + io_req_2_bits_op, + input [31:0] io_req_2_bits_pc, + output io_req_3_ready, + input io_req_3_valid, + io_req_3_bits_store, + input [4:0] io_req_3_bits_addr, + io_req_3_bits_op, + input [31:0] io_req_3_bits_pc, + io_busPort_addr_0, + io_busPort_addr_1, + io_busPort_addr_2, + io_busPort_addr_3, + io_busPort_data_0, + io_busPort_data_1, + io_busPort_data_2, + io_busPort_data_3, + io_busPort_flt_data_0, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data, + output io_rd_flt_valid, + output [4:0] io_rd_flt_bits_addr, + output [31:0] io_rd_flt_bits_data, + output io_ibus_valid, + input io_ibus_ready, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + output io_dbus_valid, + io_dbus_write, + output [31:0] io_dbus_addr, + output [127:0] io_dbus_wdata, + output [15:0] io_dbus_wmask, + input [127:0] io_dbus_rdata, + output io_flush_valid, + input io_flush_ready, + output io_flush_fencei, + output [31:0] io_flush_pcNext, + output io_fault_valid, + io_fault_bits_write, + output [31:0] io_fault_bits_addr, + io_fault_bits_epc, + output io_ebus_dbus_valid, + input io_ebus_dbus_ready, + output io_ebus_dbus_write, + output [31:0] io_ebus_dbus_pc, + io_ebus_dbus_addr, + output [4:0] io_ebus_dbus_size, + output [127:0] io_ebus_dbus_wdata, + input [127:0] io_ebus_dbus_rdata, + input io_ebus_fault_valid, + io_ebus_fault_bits_write, + input [31:0] io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, + output [1:0] io_storeCount, + output io_active +); + + wire io_ibus_valid_0; + wire io_ebus_dbus_valid_0; + wire [1:0] _opsext_T_11; + wire opload_3; + wire [4:0] _opiload_T_23; + wire [1:0] _opsext_T_8; + wire opload_2; + wire [4:0] _opiload_T_17; + wire [1:0] _opsext_T_5; + wire opload_1; + wire [4:0] _opiload_T_11; + wire [1:0] _opsext_T_2; + wire opload; + wire [4:0] _opiload_T_5; + wire _data_io_out_valid; + wire [31:0] _data_io_out_bits_addr; + wire [4:0] _data_io_out_bits_index; + wire [4:0] _data_io_out_bits_size; + wire [4:0] _data_io_out_bits_fullsize; + wire _data_io_out_bits_sext; + wire _data_io_out_bits_iload; + wire _data_io_out_bits_sldst; + wire _data_io_out_bits_fldst; + wire [1:0] _data_io_out_bits_regionType; + wire [15:0] _data_io_out_bits_mask; + wire _data_io_out_bits_last; + wire [1:0] _data_io_count; + wire _ctrl_io_out_valid; + wire [31:0] _ctrl_io_out_bits_pc; + wire [31:0] _ctrl_io_out_bits_addr; + wire [31:0] _ctrl_io_out_bits_adrx; + wire [31:0] _ctrl_io_out_bits_data; + wire [4:0] _ctrl_io_out_bits_index; + wire [4:0] _ctrl_io_out_bits_size; + wire [4:0] _ctrl_io_out_bits_fullsize; + wire _ctrl_io_out_bits_write; + wire _ctrl_io_out_bits_sext; + wire _ctrl_io_out_bits_iload; + wire _ctrl_io_out_bits_fencei; + wire _ctrl_io_out_bits_flushat; + wire _ctrl_io_out_bits_flushall; + wire _ctrl_io_out_bits_sldst; + wire _ctrl_io_out_bits_vldst; + wire _ctrl_io_out_bits_fldst; + wire [1:0] _ctrl_io_out_bits_regionType; + wire [15:0] _ctrl_io_out_bits_mask; + wire _ctrl_io_out_bits_last; + wire [3:0] _ctrl_io_count; + wire ctrlready_0 = _ctrl_io_count < 4'h2; + wire ctrlready_1 = _ctrl_io_count < 4'h4; + wire ctrlready_2 = _ctrl_io_count < 4'h6; + wire itcm = io_busPort_addr_0 < 32'h2000; + wire dtcm = (|(io_busPort_addr_0[31:16])) & io_busPort_addr_0 < 32'h18000; + wire _opsize_T_1 = io_req_0_bits_op == 5'h7; + wire _opsize_T_7 = io_req_0_bits_op == 5'h6; + wire _opsize_T_12 = io_req_0_bits_op == 5'h5; + wire _opsize_T = io_req_0_bits_op == 5'h2; + wire _opsize_T_5 = io_req_0_bits_op == 5'h1; + wire _opsize_T_10 = io_req_0_bits_op == 5'h0; + wire _opsize_T_6 = io_req_0_bits_op == 5'h4; + wire _opsize_T_11 = io_req_0_bits_op == 5'h3; + assign _opiload_T_5 = {_opsize_T_11, _opsize_T_6, _opsize_T_10, _opsize_T_5, _opsize_T}; + wire opfldst = io_req_0_bits_op == 5'hC; + assign opload = (|_opiload_T_5) | opfldst & ~io_req_0_bits_store; + wire opfencei = io_req_0_bits_op == 5'h8; + wire opflushat = io_req_0_bits_op == 5'h9; + wire opflushall = io_req_0_bits_op == 5'hA; + wire opsldst = + ((|{_opsize_T_12, _opsize_T_7, _opsize_T_1}) | opload) & io_req_0_bits_op != 5'hC; + wire opvldst = io_req_0_bits_op == 5'hB; + assign _opsext_T_2 = {_opsize_T_5, _opsize_T_10}; + wire [2:0] _opsize_T_3 = {opfldst, _opsize_T_1, _opsize_T}; + wire [2:0] _opsize_T_8 = {_opsize_T_7, _opsize_T_6, _opsize_T_5}; + wire [2:0] _opsize_T_13 = {_opsize_T_12, _opsize_T_11, _opsize_T_10}; + wire [1:0] regionType = + dtcm + ? 2'h1 + : itcm + ? 2'h0 + : {1'h1, ~(io_busPort_addr_0 > 32'h2FFFF & io_busPort_addr_0 < 32'h32000)}; + wire twoLines = + {26'h0, + {2'h0, io_busPort_addr_0[3:0]} + + {3'h0, |_opsize_T_3, |_opsize_T_8, |_opsize_T_13}} > 32'h10 & (itcm | dtcm); + wire [2:0] belowLineBoundary = 3'h0 - io_busPort_addr_0[2:0]; + wire [2:0] txnSizes_0 = + twoLines ? belowLineBoundary : {|_opsize_T_3, |_opsize_T_8, |_opsize_T_13}; + wire [2:0] txnSizes_1 = + twoLines ? {|_opsize_T_3, |_opsize_T_8, |_opsize_T_13} - belowLineBoundary : 3'h0; + wire _mask0_T_2 = txnSizes_0 > 3'h2; + wire _mask0_T_4 = txnSizes_0 > 3'h4; + wire _mask0_T_5 = txnSizes_0 > 3'h5; + wire [15:0] _mask0_T_25 = + io_busPort_addr_0[0] + ? {8'h0, + &txnSizes_0, + _mask0_T_5, + _mask0_T_4, + txnSizes_0[2], + _mask0_T_2, + |(txnSizes_0[2:1]), + |txnSizes_0, + 1'h0} + : {9'h0, + &txnSizes_0, + _mask0_T_5, + _mask0_T_4, + txnSizes_0[2], + _mask0_T_2, + |(txnSizes_0[2:1]), + |txnSizes_0}; + wire [15:0] _mask0_T_29 = + io_busPort_addr_0[1] ? {_mask0_T_25[13:0], _mask0_T_25[15:14]} : _mask0_T_25; + wire [15:0] _mask0_T_33 = + io_busPort_addr_0[2] ? {_mask0_T_29[11:0], _mask0_T_29[15:12]} : _mask0_T_29; + wire _mask1_T_2 = txnSizes_1 > 3'h2; + wire _mask1_T_4 = txnSizes_1 > 3'h4; + wire _mask1_T_5 = txnSizes_1 > 3'h5; + wire [3:0] _mask1_T_17 = io_busPort_addr_0[3:0] + {1'h0, txnSizes_0}; + wire [15:0] _mask1_T_27 = + _mask1_T_17[0] + ? {8'h0, + &txnSizes_1, + _mask1_T_5, + _mask1_T_4, + txnSizes_1[2], + _mask1_T_2, + |(txnSizes_1[2:1]), + |txnSizes_1, + 1'h0} + : {9'h0, + &txnSizes_1, + _mask1_T_5, + _mask1_T_4, + txnSizes_1[2], + _mask1_T_2, + |(txnSizes_1[2:1]), + |txnSizes_1}; + wire [15:0] _mask1_T_31 = + _mask1_T_17[1] ? {_mask1_T_27[13:0], _mask1_T_27[15:14]} : _mask1_T_27; + wire [15:0] _mask1_T_35 = + _mask1_T_17[2] ? {_mask1_T_31[11:0], _mask1_T_31[15:12]} : _mask1_T_31; + wire ctrl_io_in_bits_1_valid = io_req_0_valid & ctrlready_0; + wire [31:0] ctrl_io_in_bits_1_bits_data = + opfldst ? io_busPort_flt_data_0 : io_busPort_data_0; + wire [4:0] ctrl_io_in_bits_1_bits_fullsize = + {2'h0, |_opsize_T_3, |_opsize_T_8, |_opsize_T_13}; + wire [31:0] _ctrl_io_in_bits_0_bits_data_T_24 = + txnSizes_0[0] + ? {ctrl_io_in_bits_1_bits_data[7:0], ctrl_io_in_bits_1_bits_data[31:8]} + : ctrl_io_in_bits_1_bits_data; + wire itcm_1 = io_busPort_addr_1 < 32'h2000; + wire dtcm_1 = (|(io_busPort_addr_1[31:16])) & io_busPort_addr_1 < 32'h18000; + wire _opsize_T_16 = io_req_1_bits_op == 5'h7; + wire _opsize_T_22 = io_req_1_bits_op == 5'h6; + wire _opsize_T_27 = io_req_1_bits_op == 5'h5; + wire _opsize_T_15 = io_req_1_bits_op == 5'h2; + wire _opsize_T_20 = io_req_1_bits_op == 5'h1; + wire _opsize_T_25 = io_req_1_bits_op == 5'h0; + wire _opsize_T_21 = io_req_1_bits_op == 5'h4; + wire _opsize_T_26 = io_req_1_bits_op == 5'h3; + assign _opiload_T_11 = + {_opsize_T_26, _opsize_T_21, _opsize_T_25, _opsize_T_20, _opsize_T_15}; + wire opfldst_1 = io_req_1_bits_op == 5'hC; + assign opload_1 = (|_opiload_T_11) | opfldst_1 & ~io_req_1_bits_store; + wire opfencei_1 = io_req_1_bits_op == 5'h8; + wire opflushat_1 = io_req_1_bits_op == 5'h9; + wire opflushall_1 = io_req_1_bits_op == 5'hA; + wire opsldst_1 = + ((|{_opsize_T_27, _opsize_T_22, _opsize_T_16}) | opload_1) & io_req_1_bits_op != 5'hC; + wire opvldst_1 = io_req_1_bits_op == 5'hB; + assign _opsext_T_5 = {_opsize_T_20, _opsize_T_25}; + wire [2:0] _opsize_T_18 = {opfldst_1, _opsize_T_16, _opsize_T_15}; + wire [2:0] _opsize_T_23 = {_opsize_T_22, _opsize_T_21, _opsize_T_20}; + wire [2:0] _opsize_T_28 = {_opsize_T_27, _opsize_T_26, _opsize_T_25}; + wire [1:0] regionType_1 = + dtcm_1 + ? 2'h1 + : itcm_1 + ? 2'h0 + : {1'h1, ~(io_busPort_addr_1 > 32'h2FFFF & io_busPort_addr_1 < 32'h32000)}; + wire twoLines_1 = + {26'h0, + {2'h0, io_busPort_addr_1[3:0]} + + {3'h0, |_opsize_T_18, |_opsize_T_23, |_opsize_T_28}} > 32'h10 + & (itcm_1 | dtcm_1); + wire [2:0] belowLineBoundary_1 = 3'h0 - io_busPort_addr_1[2:0]; + wire [2:0] txnSizes_1_0 = + twoLines_1 ? belowLineBoundary_1 : {|_opsize_T_18, |_opsize_T_23, |_opsize_T_28}; + wire [2:0] txnSizes_1_1 = + twoLines_1 + ? {|_opsize_T_18, |_opsize_T_23, |_opsize_T_28} - belowLineBoundary_1 + : 3'h0; + wire _mask0_T_40 = txnSizes_1_0 > 3'h2; + wire _mask0_T_42 = txnSizes_1_0 > 3'h4; + wire _mask0_T_43 = txnSizes_1_0 > 3'h5; + wire [15:0] _mask0_T_63 = + io_busPort_addr_1[0] + ? {8'h0, + &txnSizes_1_0, + _mask0_T_43, + _mask0_T_42, + txnSizes_1_0[2], + _mask0_T_40, + |(txnSizes_1_0[2:1]), + |txnSizes_1_0, + 1'h0} + : {9'h0, + &txnSizes_1_0, + _mask0_T_43, + _mask0_T_42, + txnSizes_1_0[2], + _mask0_T_40, + |(txnSizes_1_0[2:1]), + |txnSizes_1_0}; + wire [15:0] _mask0_T_67 = + io_busPort_addr_1[1] ? {_mask0_T_63[13:0], _mask0_T_63[15:14]} : _mask0_T_63; + wire [15:0] _mask0_T_71 = + io_busPort_addr_1[2] ? {_mask0_T_67[11:0], _mask0_T_67[15:12]} : _mask0_T_67; + wire _mask1_T_42 = txnSizes_1_1 > 3'h2; + wire _mask1_T_44 = txnSizes_1_1 > 3'h4; + wire _mask1_T_45 = txnSizes_1_1 > 3'h5; + wire [3:0] _mask1_T_57 = io_busPort_addr_1[3:0] + {1'h0, txnSizes_1_0}; + wire [15:0] _mask1_T_67 = + _mask1_T_57[0] + ? {8'h0, + &txnSizes_1_1, + _mask1_T_45, + _mask1_T_44, + txnSizes_1_1[2], + _mask1_T_42, + |(txnSizes_1_1[2:1]), + |txnSizes_1_1, + 1'h0} + : {9'h0, + &txnSizes_1_1, + _mask1_T_45, + _mask1_T_44, + txnSizes_1_1[2], + _mask1_T_42, + |(txnSizes_1_1[2:1]), + |txnSizes_1_1}; + wire [15:0] _mask1_T_71 = + _mask1_T_57[1] ? {_mask1_T_67[13:0], _mask1_T_67[15:14]} : _mask1_T_67; + wire [15:0] _mask1_T_75 = + _mask1_T_57[2] ? {_mask1_T_71[11:0], _mask1_T_71[15:12]} : _mask1_T_71; + wire ctrl_io_in_bits_3_valid = io_req_1_valid & ctrlready_1; + wire [31:0] ctrl_io_in_bits_3_bits_data = opfldst_1 ? 32'h0 : io_busPort_data_1; + wire [4:0] ctrl_io_in_bits_3_bits_fullsize = + {2'h0, |_opsize_T_18, |_opsize_T_23, |_opsize_T_28}; + wire [31:0] _ctrl_io_in_bits_2_bits_data_T_24 = + txnSizes_1_0[0] + ? {ctrl_io_in_bits_3_bits_data[7:0], ctrl_io_in_bits_3_bits_data[31:8]} + : ctrl_io_in_bits_3_bits_data; + wire itcm_2 = io_busPort_addr_2 < 32'h2000; + wire dtcm_2 = (|(io_busPort_addr_2[31:16])) & io_busPort_addr_2 < 32'h18000; + wire _opsize_T_31 = io_req_2_bits_op == 5'h7; + wire _opsize_T_37 = io_req_2_bits_op == 5'h6; + wire _opsize_T_42 = io_req_2_bits_op == 5'h5; + wire _opsize_T_30 = io_req_2_bits_op == 5'h2; + wire _opsize_T_35 = io_req_2_bits_op == 5'h1; + wire _opsize_T_40 = io_req_2_bits_op == 5'h0; + wire _opsize_T_36 = io_req_2_bits_op == 5'h4; + wire _opsize_T_41 = io_req_2_bits_op == 5'h3; + assign _opiload_T_17 = + {_opsize_T_41, _opsize_T_36, _opsize_T_40, _opsize_T_35, _opsize_T_30}; + wire opfldst_2 = io_req_2_bits_op == 5'hC; + assign opload_2 = (|_opiload_T_17) | opfldst_2 & ~io_req_2_bits_store; + wire opfencei_2 = io_req_2_bits_op == 5'h8; + wire opflushat_2 = io_req_2_bits_op == 5'h9; + wire opflushall_2 = io_req_2_bits_op == 5'hA; + wire opsldst_2 = + ((|{_opsize_T_42, _opsize_T_37, _opsize_T_31}) | opload_2) & io_req_2_bits_op != 5'hC; + wire opvldst_2 = io_req_2_bits_op == 5'hB; + assign _opsext_T_8 = {_opsize_T_35, _opsize_T_40}; + wire [2:0] _opsize_T_33 = {opfldst_2, _opsize_T_31, _opsize_T_30}; + wire [2:0] _opsize_T_38 = {_opsize_T_37, _opsize_T_36, _opsize_T_35}; + wire [2:0] _opsize_T_43 = {_opsize_T_42, _opsize_T_41, _opsize_T_40}; + wire [1:0] regionType_2 = + dtcm_2 + ? 2'h1 + : itcm_2 + ? 2'h0 + : {1'h1, ~(io_busPort_addr_2 > 32'h2FFFF & io_busPort_addr_2 < 32'h32000)}; + wire twoLines_2 = + {26'h0, + {2'h0, io_busPort_addr_2[3:0]} + + {3'h0, |_opsize_T_33, |_opsize_T_38, |_opsize_T_43}} > 32'h10 + & (itcm_2 | dtcm_2); + wire [2:0] belowLineBoundary_2 = 3'h0 - io_busPort_addr_2[2:0]; + wire [2:0] txnSizes_2_0 = + twoLines_2 ? belowLineBoundary_2 : {|_opsize_T_33, |_opsize_T_38, |_opsize_T_43}; + wire [2:0] txnSizes_2_1 = + twoLines_2 + ? {|_opsize_T_33, |_opsize_T_38, |_opsize_T_43} - belowLineBoundary_2 + : 3'h0; + wire _mask0_T_78 = txnSizes_2_0 > 3'h2; + wire _mask0_T_80 = txnSizes_2_0 > 3'h4; + wire _mask0_T_81 = txnSizes_2_0 > 3'h5; + wire [15:0] _mask0_T_101 = + io_busPort_addr_2[0] + ? {8'h0, + &txnSizes_2_0, + _mask0_T_81, + _mask0_T_80, + txnSizes_2_0[2], + _mask0_T_78, + |(txnSizes_2_0[2:1]), + |txnSizes_2_0, + 1'h0} + : {9'h0, + &txnSizes_2_0, + _mask0_T_81, + _mask0_T_80, + txnSizes_2_0[2], + _mask0_T_78, + |(txnSizes_2_0[2:1]), + |txnSizes_2_0}; + wire [15:0] _mask0_T_105 = + io_busPort_addr_2[1] ? {_mask0_T_101[13:0], _mask0_T_101[15:14]} : _mask0_T_101; + wire [15:0] _mask0_T_109 = + io_busPort_addr_2[2] ? {_mask0_T_105[11:0], _mask0_T_105[15:12]} : _mask0_T_105; + wire _mask1_T_82 = txnSizes_2_1 > 3'h2; + wire _mask1_T_84 = txnSizes_2_1 > 3'h4; + wire _mask1_T_85 = txnSizes_2_1 > 3'h5; + wire [3:0] _mask1_T_97 = io_busPort_addr_2[3:0] + {1'h0, txnSizes_2_0}; + wire [15:0] _mask1_T_107 = + _mask1_T_97[0] + ? {8'h0, + &txnSizes_2_1, + _mask1_T_85, + _mask1_T_84, + txnSizes_2_1[2], + _mask1_T_82, + |(txnSizes_2_1[2:1]), + |txnSizes_2_1, + 1'h0} + : {9'h0, + &txnSizes_2_1, + _mask1_T_85, + _mask1_T_84, + txnSizes_2_1[2], + _mask1_T_82, + |(txnSizes_2_1[2:1]), + |txnSizes_2_1}; + wire [15:0] _mask1_T_111 = + _mask1_T_97[1] ? {_mask1_T_107[13:0], _mask1_T_107[15:14]} : _mask1_T_107; + wire [15:0] _mask1_T_115 = + _mask1_T_97[2] ? {_mask1_T_111[11:0], _mask1_T_111[15:12]} : _mask1_T_111; + wire ctrl_io_in_bits_5_valid = io_req_2_valid & ctrlready_2; + wire [31:0] ctrl_io_in_bits_5_bits_data = opfldst_2 ? 32'h0 : io_busPort_data_2; + wire [4:0] ctrl_io_in_bits_5_bits_fullsize = + {2'h0, |_opsize_T_33, |_opsize_T_38, |_opsize_T_43}; + wire [31:0] _ctrl_io_in_bits_4_bits_data_T_24 = + txnSizes_2_0[0] + ? {ctrl_io_in_bits_5_bits_data[7:0], ctrl_io_in_bits_5_bits_data[31:8]} + : ctrl_io_in_bits_5_bits_data; + wire itcm_3 = io_busPort_addr_3 < 32'h2000; + wire dtcm_3 = (|(io_busPort_addr_3[31:16])) & io_busPort_addr_3 < 32'h18000; + wire _opsize_T_46 = io_req_3_bits_op == 5'h7; + wire _opsize_T_52 = io_req_3_bits_op == 5'h6; + wire _opsize_T_57 = io_req_3_bits_op == 5'h5; + wire _opsize_T_45 = io_req_3_bits_op == 5'h2; + wire _opsize_T_50 = io_req_3_bits_op == 5'h1; + wire _opsize_T_55 = io_req_3_bits_op == 5'h0; + wire _opsize_T_51 = io_req_3_bits_op == 5'h4; + wire _opsize_T_56 = io_req_3_bits_op == 5'h3; + assign _opiload_T_23 = + {_opsize_T_56, _opsize_T_51, _opsize_T_55, _opsize_T_50, _opsize_T_45}; + wire opfldst_3 = io_req_3_bits_op == 5'hC; + assign opload_3 = (|_opiload_T_23) | opfldst_3 & ~io_req_3_bits_store; + wire opfencei_3 = io_req_3_bits_op == 5'h8; + wire opflushat_3 = io_req_3_bits_op == 5'h9; + wire opflushall_3 = io_req_3_bits_op == 5'hA; + wire opsldst_3 = + ((|{_opsize_T_57, _opsize_T_52, _opsize_T_46}) | opload_3) & io_req_3_bits_op != 5'hC; + wire opvldst_3 = io_req_3_bits_op == 5'hB; + assign _opsext_T_11 = {_opsize_T_50, _opsize_T_55}; + wire [2:0] _opsize_T_48 = {opfldst_3, _opsize_T_46, _opsize_T_45}; + wire [2:0] _opsize_T_53 = {_opsize_T_52, _opsize_T_51, _opsize_T_50}; + wire [2:0] _opsize_T_58 = {_opsize_T_57, _opsize_T_56, _opsize_T_55}; + wire [1:0] regionType_3 = + dtcm_3 + ? 2'h1 + : itcm_3 + ? 2'h0 + : {1'h1, ~(io_busPort_addr_3 > 32'h2FFFF & io_busPort_addr_3 < 32'h32000)}; + wire twoLines_3 = + {26'h0, + {2'h0, io_busPort_addr_3[3:0]} + + {3'h0, |_opsize_T_48, |_opsize_T_53, |_opsize_T_58}} > 32'h10 + & (itcm_3 | dtcm_3); + wire [2:0] belowLineBoundary_3 = 3'h0 - io_busPort_addr_3[2:0]; + wire [2:0] txnSizes_3_0 = + twoLines_3 ? belowLineBoundary_3 : {|_opsize_T_48, |_opsize_T_53, |_opsize_T_58}; + wire [2:0] txnSizes_3_1 = + twoLines_3 + ? {|_opsize_T_48, |_opsize_T_53, |_opsize_T_58} - belowLineBoundary_3 + : 3'h0; + wire _mask0_T_116 = txnSizes_3_0 > 3'h2; + wire _mask0_T_118 = txnSizes_3_0 > 3'h4; + wire _mask0_T_119 = txnSizes_3_0 > 3'h5; + wire [15:0] _mask0_T_139 = + io_busPort_addr_3[0] + ? {8'h0, + &txnSizes_3_0, + _mask0_T_119, + _mask0_T_118, + txnSizes_3_0[2], + _mask0_T_116, + |(txnSizes_3_0[2:1]), + |txnSizes_3_0, + 1'h0} + : {9'h0, + &txnSizes_3_0, + _mask0_T_119, + _mask0_T_118, + txnSizes_3_0[2], + _mask0_T_116, + |(txnSizes_3_0[2:1]), + |txnSizes_3_0}; + wire [15:0] _mask0_T_143 = + io_busPort_addr_3[1] ? {_mask0_T_139[13:0], _mask0_T_139[15:14]} : _mask0_T_139; + wire [15:0] _mask0_T_147 = + io_busPort_addr_3[2] ? {_mask0_T_143[11:0], _mask0_T_143[15:12]} : _mask0_T_143; + wire _mask1_T_122 = txnSizes_3_1 > 3'h2; + wire _mask1_T_124 = txnSizes_3_1 > 3'h4; + wire _mask1_T_125 = txnSizes_3_1 > 3'h5; + wire [3:0] _mask1_T_137 = io_busPort_addr_3[3:0] + {1'h0, txnSizes_3_0}; + wire [15:0] _mask1_T_147 = + _mask1_T_137[0] + ? {8'h0, + &txnSizes_3_1, + _mask1_T_125, + _mask1_T_124, + txnSizes_3_1[2], + _mask1_T_122, + |(txnSizes_3_1[2:1]), + |txnSizes_3_1, + 1'h0} + : {9'h0, + &txnSizes_3_1, + _mask1_T_125, + _mask1_T_124, + txnSizes_3_1[2], + _mask1_T_122, + |(txnSizes_3_1[2:1]), + |txnSizes_3_1}; + wire [15:0] _mask1_T_151 = + _mask1_T_137[1] ? {_mask1_T_147[13:0], _mask1_T_147[15:14]} : _mask1_T_147; + wire [15:0] _mask1_T_155 = + _mask1_T_137[2] ? {_mask1_T_151[11:0], _mask1_T_151[15:12]} : _mask1_T_151; + wire ctrl_io_in_bits_7_valid = io_req_3_valid & ~(_ctrl_io_count[3]); + wire [31:0] ctrl_io_in_bits_7_bits_data = opfldst_3 ? 32'h0 : io_busPort_data_3; + wire [4:0] ctrl_io_in_bits_7_bits_fullsize = + {2'h0, |_opsize_T_48, |_opsize_T_53, |_opsize_T_58}; + wire [31:0] _ctrl_io_in_bits_6_bits_data_T_24 = + txnSizes_3_0[0] + ? {ctrl_io_in_bits_7_bits_data[7:0], ctrl_io_in_bits_7_bits_data[31:8]} + : ctrl_io_in_bits_7_bits_data; + wire [15:0] wmaskT = 16'hFFFF >> 5'h10 - _ctrl_io_out_bits_size; + wire [30:0] _wmaskS_T_1 = {15'h0, wmaskT} << _ctrl_io_out_bits_addr[3:0]; + wire [127:0] wdata = + {2{{2{(_ctrl_io_out_bits_addr[1:0] == 2'h0 ? _ctrl_io_out_bits_data : 32'h0) + | (_ctrl_io_out_bits_addr[1:0] == 2'h1 + ? {_ctrl_io_out_bits_data[23:0], _ctrl_io_out_bits_data[31:24]} + : 32'h0) + | (_ctrl_io_out_bits_addr[1:0] == 2'h2 + ? {_ctrl_io_out_bits_data[15:0], _ctrl_io_out_bits_data[31:16]} + : 32'h0) + | ((&(_ctrl_io_out_bits_addr[1:0])) + ? {_ctrl_io_out_bits_data[7:0], _ctrl_io_out_bits_data[31:8]} + : 32'h0)}}}}; + wire _dataFired_T_3 = io_ebus_dbus_valid_0 & io_ebus_dbus_ready; + wire _dataFired_T_7 = io_ibus_valid_0 & io_ibus_ready; + wire _imem_store_fault_T = _ctrl_io_out_bits_sldst | _ctrl_io_out_bits_fldst; + wire io_dbus_valid_0 = + _ctrl_io_out_valid & _imem_store_fault_T & _ctrl_io_out_bits_regionType == 2'h1; + wire [31:0] io_dbus_addr_0 = {1'h0, _ctrl_io_out_bits_addr[30:0]}; + assign io_ebus_dbus_valid_0 = + _ctrl_io_out_valid & _imem_store_fault_T + & ((&_ctrl_io_out_bits_regionType) | _ctrl_io_out_bits_regionType == 2'h2); + wire _imem_store_fault_T_2 = _ctrl_io_out_bits_regionType == 2'h0; + assign io_ibus_valid_0 = + _ctrl_io_out_valid & _imem_store_fault_T & _imem_store_fault_T_2 + & ~_ctrl_io_out_bits_write; + wire imem_store_fault = + _ctrl_io_out_valid & _imem_store_fault_T & _imem_store_fault_T_2 + & _ctrl_io_out_bits_write; + wire io_flush_valid_0 = + _ctrl_io_out_valid + & (_ctrl_io_out_bits_fencei | _ctrl_io_out_bits_flushat | _ctrl_io_out_bits_flushall); + wire rvalid = _data_io_out_valid & _data_io_out_bits_last; + wire [127:0] srdataMasked = + (_data_io_out_bits_regionType == 2'h2 | (&_data_io_out_bits_regionType) + ? io_ebus_dbus_rdata + : _data_io_out_bits_regionType == 2'h0 ? io_ibus_rdata : io_dbus_rdata) + & {{8{_data_io_out_bits_mask[15]}}, + {8{_data_io_out_bits_mask[14]}}, + {8{_data_io_out_bits_mask[13]}}, + {8{_data_io_out_bits_mask[12]}}, + {8{_data_io_out_bits_mask[11]}}, + {8{_data_io_out_bits_mask[10]}}, + {8{_data_io_out_bits_mask[9]}}, + {8{_data_io_out_bits_mask[8]}}, + {8{_data_io_out_bits_mask[7]}}, + {8{_data_io_out_bits_mask[6]}}, + {8{_data_io_out_bits_mask[5]}}, + {8{_data_io_out_bits_mask[4]}}, + {8{_data_io_out_bits_mask[3]}}, + {8{_data_io_out_bits_mask[2]}}, + {8{_data_io_out_bits_mask[1]}}, + {8{_data_io_out_bits_mask[0]}}}; + reg [127:0] prevSrdataReg; + wire io_rd_pre_pipe_valid = rvalid & _data_io_out_bits_iload; + reg io_rd_pipe_pipe_v; + reg [4:0] io_rd_pipe_pipe_b_addr; + reg [31:0] io_rd_pipe_pipe_b_data; + wire io_rd_flt_pre_pipe_valid = rvalid & _data_io_out_bits_fldst; + reg io_rd_flt_pipe_pipe_v; + reg [4:0] io_rd_flt_pipe_pipe_b_addr; + reg [31:0] io_rd_flt_pipe_pipe_b_data; + always @(posedge clock or posedge reset) begin + if (reset) begin + prevSrdataReg <= 128'h0; + io_rd_pipe_pipe_v <= 1'h0; + io_rd_flt_pipe_pipe_v <= 1'h0; + end + else begin + prevSrdataReg <= srdataMasked; + io_rd_pipe_pipe_v <= io_rd_pre_pipe_valid; + io_rd_flt_pipe_pipe_v <= io_rd_flt_pre_pipe_valid; + end + end // always @(posedge, posedge) + wire [127:0] _combinedSrdata_T = + srdataMasked + | (_data_io_out_bits_fullsize == _data_io_out_bits_size ? 128'h0 : prevSrdataReg); + wire _combinedSrdata_sizeMask_T_75 = _data_io_out_bits_fullsize == 5'h4; + wire _combinedSrdata_sizeMask_T_76 = _data_io_out_bits_fullsize == 5'h3; + wire _combinedSrdata_signExtend_T_90 = _data_io_out_bits_fullsize == 5'h2; + wire [31:0] _GEN = + (_data_io_out_bits_addr[3:0] == 4'h0 + ? _combinedSrdata_T[31:0] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[15] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[7] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h1 + ? _combinedSrdata_T[39:8] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[23] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[15] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h2 + ? _combinedSrdata_T[47:16] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[31] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[23] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h3 + ? _combinedSrdata_T[55:24] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[39] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[31] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h4 + ? _combinedSrdata_T[63:32] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[47] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[39] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h5 + ? _combinedSrdata_T[71:40] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[55] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[47] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h6 + ? _combinedSrdata_T[79:48] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[63] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[55] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h7 + ? _combinedSrdata_T[87:56] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[71] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[63] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h8 + ? _combinedSrdata_T[95:64] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[79] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[71] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'h9 + ? _combinedSrdata_T[103:72] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[87] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[79] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'hA + ? _combinedSrdata_T[111:80] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[95] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[87] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'hB + ? _combinedSrdata_T[119:88] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[103] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[95] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'hC + ? _combinedSrdata_T[127:96] + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[111] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[103] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'hD + ? {_combinedSrdata_T[7:0], _combinedSrdata_T[127:104]} + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[119] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[111] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | (_data_io_out_bits_addr[3:0] == 4'hE + ? {_combinedSrdata_T[15:0], _combinedSrdata_T[127:112]} + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[127] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[119] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0) + | ((&(_data_io_out_bits_addr[3:0])) + ? {_combinedSrdata_T[23:0], _combinedSrdata_T[127:120]} + & (_combinedSrdata_sizeMask_T_75 + ? 32'hFFFFFFFF + : _combinedSrdata_sizeMask_T_76 + ? 32'hFFFFFF + : _combinedSrdata_signExtend_T_90 ? 32'hFFFF : 32'hFF) + | (_data_io_out_bits_sext + ? (_combinedSrdata_signExtend_T_90 + ? (_combinedSrdata_T[7] ? 32'hFFFF0000 : 32'h0) + : _combinedSrdata_T[127] ? 32'hFFFFFF00 : 32'h0) + : 32'h0) + : 32'h0); + always @(posedge clock) begin + if (io_rd_pre_pipe_valid) begin + io_rd_pipe_pipe_b_addr <= _data_io_out_bits_index; + io_rd_pipe_pipe_b_data <= _data_io_out_bits_sldst ? _GEN : 32'h0; + end + if (io_rd_flt_pre_pipe_valid) begin + io_rd_flt_pipe_pipe_b_addr <= _data_io_out_bits_index; + io_rd_flt_pipe_pipe_b_data <= _data_io_out_bits_fldst ? _GEN : 32'h0; + end + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:6]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + prevSrdataReg = {_RANDOM[3'h0], _RANDOM[3'h1], _RANDOM[3'h2], _RANDOM[3'h3]}; + io_rd_pipe_pipe_v = _RANDOM[3'h4][0]; + io_rd_pipe_pipe_b_addr = _RANDOM[3'h4][5:1]; + io_rd_pipe_pipe_b_data = {_RANDOM[3'h4][31:6], _RANDOM[3'h5][5:0]}; + io_rd_flt_pipe_pipe_v = _RANDOM[3'h5][6]; + io_rd_flt_pipe_pipe_b_addr = _RANDOM[3'h5][11:7]; + io_rd_flt_pipe_pipe_b_data = {_RANDOM[3'h5][31:12], _RANDOM[3'h6][11:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + prevSrdataReg = 128'h0; + io_rd_pipe_pipe_v = 1'h0; + io_rd_flt_pipe_pipe_v = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FifoX ctrl ( + .clock (clock), + .reset (reset), + .io_in_valid + (io_req_0_valid | io_req_1_valid | io_req_2_valid | io_req_3_valid), + .io_in_bits_0_valid (ctrl_io_in_bits_1_valid & twoLines), + .io_in_bits_0_bits_pc (io_req_0_bits_pc), + .io_in_bits_0_bits_addr ({io_busPort_addr_0[31:4] + 28'h1, 4'h0}), + .io_in_bits_0_bits_adrx ({io_busPort_addr_0[31:4] + 28'h1, 4'h0} + 32'h10), + .io_in_bits_0_bits_data + (txnSizes_0[1] + ? {_ctrl_io_in_bits_0_bits_data_T_24[15:0], + _ctrl_io_in_bits_0_bits_data_T_24[31:16]} + : _ctrl_io_in_bits_0_bits_data_T_24), + .io_in_bits_0_bits_index (io_req_0_bits_addr), + .io_in_bits_0_bits_size ({2'h0, txnSizes_1}), + .io_in_bits_0_bits_fullsize (ctrl_io_in_bits_1_bits_fullsize), + .io_in_bits_0_bits_write (~opload), + .io_in_bits_0_bits_sext (|_opsext_T_2), + .io_in_bits_0_bits_iload (|_opiload_T_5), + .io_in_bits_0_bits_fencei (opfencei), + .io_in_bits_0_bits_flushat (opflushat), + .io_in_bits_0_bits_flushall (opflushall), + .io_in_bits_0_bits_sldst (opsldst), + .io_in_bits_0_bits_vldst (opvldst), + .io_in_bits_0_bits_fldst (opfldst), + .io_in_bits_0_bits_regionType (regionType), + .io_in_bits_0_bits_mask + (_mask1_T_17[3] ? {_mask1_T_35[7:0], _mask1_T_35[15:8]} : _mask1_T_35), + .io_in_bits_1_valid (ctrl_io_in_bits_1_valid), + .io_in_bits_1_bits_pc (io_req_0_bits_pc), + .io_in_bits_1_bits_addr (io_busPort_addr_0), + .io_in_bits_1_bits_adrx (io_busPort_addr_0 + 32'h10), + .io_in_bits_1_bits_data (ctrl_io_in_bits_1_bits_data), + .io_in_bits_1_bits_index (io_req_0_bits_addr), + .io_in_bits_1_bits_size ({2'h0, txnSizes_0}), + .io_in_bits_1_bits_fullsize (ctrl_io_in_bits_1_bits_fullsize), + .io_in_bits_1_bits_write (~opload), + .io_in_bits_1_bits_sext (|_opsext_T_2), + .io_in_bits_1_bits_iload (|_opiload_T_5), + .io_in_bits_1_bits_fencei (opfencei), + .io_in_bits_1_bits_flushat (opflushat), + .io_in_bits_1_bits_flushall (opflushall), + .io_in_bits_1_bits_sldst (opsldst), + .io_in_bits_1_bits_vldst (opvldst), + .io_in_bits_1_bits_fldst (opfldst), + .io_in_bits_1_bits_regionType (regionType), + .io_in_bits_1_bits_mask + (io_busPort_addr_0[3] ? {_mask0_T_33[7:0], _mask0_T_33[15:8]} : _mask0_T_33), + .io_in_bits_2_valid (ctrl_io_in_bits_3_valid & twoLines_1), + .io_in_bits_2_bits_pc (io_req_1_bits_pc), + .io_in_bits_2_bits_addr ({io_busPort_addr_1[31:4] + 28'h1, 4'h0}), + .io_in_bits_2_bits_adrx ({io_busPort_addr_1[31:4] + 28'h1, 4'h0} + 32'h10), + .io_in_bits_2_bits_data + (txnSizes_1_0[1] + ? {_ctrl_io_in_bits_2_bits_data_T_24[15:0], + _ctrl_io_in_bits_2_bits_data_T_24[31:16]} + : _ctrl_io_in_bits_2_bits_data_T_24), + .io_in_bits_2_bits_index (io_req_1_bits_addr), + .io_in_bits_2_bits_size ({2'h0, txnSizes_1_1}), + .io_in_bits_2_bits_fullsize (ctrl_io_in_bits_3_bits_fullsize), + .io_in_bits_2_bits_write (~opload_1), + .io_in_bits_2_bits_sext (|_opsext_T_5), + .io_in_bits_2_bits_iload (|_opiload_T_11), + .io_in_bits_2_bits_fencei (opfencei_1), + .io_in_bits_2_bits_flushat (opflushat_1), + .io_in_bits_2_bits_flushall (opflushall_1), + .io_in_bits_2_bits_sldst (opsldst_1), + .io_in_bits_2_bits_vldst (opvldst_1), + .io_in_bits_2_bits_fldst (opfldst_1), + .io_in_bits_2_bits_regionType (regionType_1), + .io_in_bits_2_bits_mask + (_mask1_T_57[3] ? {_mask1_T_75[7:0], _mask1_T_75[15:8]} : _mask1_T_75), + .io_in_bits_3_valid (ctrl_io_in_bits_3_valid), + .io_in_bits_3_bits_pc (io_req_1_bits_pc), + .io_in_bits_3_bits_addr (io_busPort_addr_1), + .io_in_bits_3_bits_adrx (io_busPort_addr_1 + 32'h10), + .io_in_bits_3_bits_data (ctrl_io_in_bits_3_bits_data), + .io_in_bits_3_bits_index (io_req_1_bits_addr), + .io_in_bits_3_bits_size ({2'h0, txnSizes_1_0}), + .io_in_bits_3_bits_fullsize (ctrl_io_in_bits_3_bits_fullsize), + .io_in_bits_3_bits_write (~opload_1), + .io_in_bits_3_bits_sext (|_opsext_T_5), + .io_in_bits_3_bits_iload (|_opiload_T_11), + .io_in_bits_3_bits_fencei (opfencei_1), + .io_in_bits_3_bits_flushat (opflushat_1), + .io_in_bits_3_bits_flushall (opflushall_1), + .io_in_bits_3_bits_sldst (opsldst_1), + .io_in_bits_3_bits_vldst (opvldst_1), + .io_in_bits_3_bits_fldst (opfldst_1), + .io_in_bits_3_bits_regionType (regionType_1), + .io_in_bits_3_bits_mask + (io_busPort_addr_1[3] ? {_mask0_T_71[7:0], _mask0_T_71[15:8]} : _mask0_T_71), + .io_in_bits_4_valid (ctrl_io_in_bits_5_valid & twoLines_2), + .io_in_bits_4_bits_pc (io_req_2_bits_pc), + .io_in_bits_4_bits_addr ({io_busPort_addr_2[31:4] + 28'h1, 4'h0}), + .io_in_bits_4_bits_adrx ({io_busPort_addr_2[31:4] + 28'h1, 4'h0} + 32'h10), + .io_in_bits_4_bits_data + (txnSizes_2_0[1] + ? {_ctrl_io_in_bits_4_bits_data_T_24[15:0], + _ctrl_io_in_bits_4_bits_data_T_24[31:16]} + : _ctrl_io_in_bits_4_bits_data_T_24), + .io_in_bits_4_bits_index (io_req_2_bits_addr), + .io_in_bits_4_bits_size ({2'h0, txnSizes_2_1}), + .io_in_bits_4_bits_fullsize (ctrl_io_in_bits_5_bits_fullsize), + .io_in_bits_4_bits_write (~opload_2), + .io_in_bits_4_bits_sext (|_opsext_T_8), + .io_in_bits_4_bits_iload (|_opiload_T_17), + .io_in_bits_4_bits_fencei (opfencei_2), + .io_in_bits_4_bits_flushat (opflushat_2), + .io_in_bits_4_bits_flushall (opflushall_2), + .io_in_bits_4_bits_sldst (opsldst_2), + .io_in_bits_4_bits_vldst (opvldst_2), + .io_in_bits_4_bits_fldst (opfldst_2), + .io_in_bits_4_bits_regionType (regionType_2), + .io_in_bits_4_bits_mask + (_mask1_T_97[3] ? {_mask1_T_115[7:0], _mask1_T_115[15:8]} : _mask1_T_115), + .io_in_bits_5_valid (ctrl_io_in_bits_5_valid), + .io_in_bits_5_bits_pc (io_req_2_bits_pc), + .io_in_bits_5_bits_addr (io_busPort_addr_2), + .io_in_bits_5_bits_adrx (io_busPort_addr_2 + 32'h10), + .io_in_bits_5_bits_data (ctrl_io_in_bits_5_bits_data), + .io_in_bits_5_bits_index (io_req_2_bits_addr), + .io_in_bits_5_bits_size ({2'h0, txnSizes_2_0}), + .io_in_bits_5_bits_fullsize (ctrl_io_in_bits_5_bits_fullsize), + .io_in_bits_5_bits_write (~opload_2), + .io_in_bits_5_bits_sext (|_opsext_T_8), + .io_in_bits_5_bits_iload (|_opiload_T_17), + .io_in_bits_5_bits_fencei (opfencei_2), + .io_in_bits_5_bits_flushat (opflushat_2), + .io_in_bits_5_bits_flushall (opflushall_2), + .io_in_bits_5_bits_sldst (opsldst_2), + .io_in_bits_5_bits_vldst (opvldst_2), + .io_in_bits_5_bits_fldst (opfldst_2), + .io_in_bits_5_bits_regionType (regionType_2), + .io_in_bits_5_bits_mask + (io_busPort_addr_2[3] ? {_mask0_T_109[7:0], _mask0_T_109[15:8]} : _mask0_T_109), + .io_in_bits_6_valid (ctrl_io_in_bits_7_valid & twoLines_3), + .io_in_bits_6_bits_pc (io_req_3_bits_pc), + .io_in_bits_6_bits_addr ({io_busPort_addr_3[31:4] + 28'h1, 4'h0}), + .io_in_bits_6_bits_adrx ({io_busPort_addr_3[31:4] + 28'h1, 4'h0} + 32'h10), + .io_in_bits_6_bits_data + (txnSizes_3_0[1] + ? {_ctrl_io_in_bits_6_bits_data_T_24[15:0], + _ctrl_io_in_bits_6_bits_data_T_24[31:16]} + : _ctrl_io_in_bits_6_bits_data_T_24), + .io_in_bits_6_bits_index (io_req_3_bits_addr), + .io_in_bits_6_bits_size ({2'h0, txnSizes_3_1}), + .io_in_bits_6_bits_fullsize (ctrl_io_in_bits_7_bits_fullsize), + .io_in_bits_6_bits_write (~opload_3), + .io_in_bits_6_bits_sext (|_opsext_T_11), + .io_in_bits_6_bits_iload (|_opiload_T_23), + .io_in_bits_6_bits_fencei (opfencei_3), + .io_in_bits_6_bits_flushat (opflushat_3), + .io_in_bits_6_bits_flushall (opflushall_3), + .io_in_bits_6_bits_sldst (opsldst_3), + .io_in_bits_6_bits_vldst (opvldst_3), + .io_in_bits_6_bits_fldst (opfldst_3), + .io_in_bits_6_bits_regionType (regionType_3), + .io_in_bits_6_bits_mask + (_mask1_T_137[3] ? {_mask1_T_155[7:0], _mask1_T_155[15:8]} : _mask1_T_155), + .io_in_bits_7_valid (ctrl_io_in_bits_7_valid), + .io_in_bits_7_bits_pc (io_req_3_bits_pc), + .io_in_bits_7_bits_addr (io_busPort_addr_3), + .io_in_bits_7_bits_adrx (io_busPort_addr_3 + 32'h10), + .io_in_bits_7_bits_data (ctrl_io_in_bits_7_bits_data), + .io_in_bits_7_bits_index (io_req_3_bits_addr), + .io_in_bits_7_bits_size ({2'h0, txnSizes_3_0}), + .io_in_bits_7_bits_fullsize (ctrl_io_in_bits_7_bits_fullsize), + .io_in_bits_7_bits_write (~opload_3), + .io_in_bits_7_bits_sext (|_opsext_T_11), + .io_in_bits_7_bits_iload (|_opiload_T_23), + .io_in_bits_7_bits_fencei (opfencei_3), + .io_in_bits_7_bits_flushat (opflushat_3), + .io_in_bits_7_bits_flushall (opflushall_3), + .io_in_bits_7_bits_sldst (opsldst_3), + .io_in_bits_7_bits_vldst (opvldst_3), + .io_in_bits_7_bits_fldst (opfldst_3), + .io_in_bits_7_bits_regionType (regionType_3), + .io_in_bits_7_bits_mask + (io_busPort_addr_3[3] ? {_mask0_T_147[7:0], _mask0_T_147[15:8]} : _mask0_T_147), + .io_out_ready + (io_flush_valid_0 & io_flush_ready | imem_store_fault | _ctrl_io_out_bits_vldst + | io_dbus_valid_0 | _dataFired_T_3 | _dataFired_T_7), + .io_out_valid (_ctrl_io_out_valid), + .io_out_bits_pc (_ctrl_io_out_bits_pc), + .io_out_bits_addr (_ctrl_io_out_bits_addr), + .io_out_bits_adrx (_ctrl_io_out_bits_adrx), + .io_out_bits_data (_ctrl_io_out_bits_data), + .io_out_bits_index (_ctrl_io_out_bits_index), + .io_out_bits_size (_ctrl_io_out_bits_size), + .io_out_bits_fullsize (_ctrl_io_out_bits_fullsize), + .io_out_bits_write (_ctrl_io_out_bits_write), + .io_out_bits_sext (_ctrl_io_out_bits_sext), + .io_out_bits_iload (_ctrl_io_out_bits_iload), + .io_out_bits_fencei (_ctrl_io_out_bits_fencei), + .io_out_bits_flushat (_ctrl_io_out_bits_flushat), + .io_out_bits_flushall (_ctrl_io_out_bits_flushall), + .io_out_bits_sldst (_ctrl_io_out_bits_sldst), + .io_out_bits_vldst (_ctrl_io_out_bits_vldst), + .io_out_bits_fldst (_ctrl_io_out_bits_fldst), + .io_out_bits_regionType (_ctrl_io_out_bits_regionType), + .io_out_bits_mask (_ctrl_io_out_bits_mask), + .io_out_bits_last (_ctrl_io_out_bits_last), + .io_count (_ctrl_io_count) + ); + Slice_1 data ( + .clock (clock), + .reset (reset), + .io_in_valid + (io_dbus_valid_0 & ~_ctrl_io_out_bits_write | _dataFired_T_3 + & ~_ctrl_io_out_bits_write | _dataFired_T_7), + .io_in_bits_addr (_ctrl_io_out_bits_addr), + .io_in_bits_index (_ctrl_io_out_bits_index), + .io_in_bits_size (_ctrl_io_out_bits_size), + .io_in_bits_fullsize (_ctrl_io_out_bits_fullsize), + .io_in_bits_sext (_ctrl_io_out_bits_sext), + .io_in_bits_iload (_ctrl_io_out_bits_iload), + .io_in_bits_sldst (_ctrl_io_out_bits_sldst), + .io_in_bits_fldst (_ctrl_io_out_bits_fldst), + .io_in_bits_regionType (_ctrl_io_out_bits_regionType), + .io_in_bits_mask (_ctrl_io_out_bits_mask), + .io_in_bits_last (_ctrl_io_out_bits_last), + .io_out_valid (_data_io_out_valid), + .io_out_bits_addr (_data_io_out_bits_addr), + .io_out_bits_index (_data_io_out_bits_index), + .io_out_bits_size (_data_io_out_bits_size), + .io_out_bits_fullsize (_data_io_out_bits_fullsize), + .io_out_bits_sext (_data_io_out_bits_sext), + .io_out_bits_iload (_data_io_out_bits_iload), + .io_out_bits_sldst (_data_io_out_bits_sldst), + .io_out_bits_fldst (_data_io_out_bits_fldst), + .io_out_bits_regionType (_data_io_out_bits_regionType), + .io_out_bits_mask (_data_io_out_bits_mask), + .io_out_bits_last (_data_io_out_bits_last), + .io_count (_data_io_count) + ); + assign io_req_0_ready = ctrlready_0; + assign io_req_1_ready = ctrlready_1; + assign io_req_2_ready = ctrlready_2; + assign io_req_3_ready = ~(_ctrl_io_count[3]); + assign io_rd_valid = io_rd_pipe_pipe_v; + assign io_rd_bits_addr = io_rd_pipe_pipe_b_addr; + assign io_rd_bits_data = io_rd_pipe_pipe_b_data; + assign io_rd_flt_valid = io_rd_flt_pipe_pipe_v; + assign io_rd_flt_bits_addr = io_rd_flt_pipe_pipe_b_addr; + assign io_rd_flt_bits_data = io_rd_flt_pipe_pipe_b_data; + assign io_ibus_valid = io_ibus_valid_0; + assign io_ibus_addr = _ctrl_io_out_bits_addr; + assign io_dbus_valid = io_dbus_valid_0; + assign io_dbus_write = _ctrl_io_out_bits_write; + assign io_dbus_addr = io_dbus_addr_0; + assign io_dbus_wdata = wdata; + assign io_dbus_wmask = + _wmaskS_T_1[15:0] | wmaskT >> 5'h10 - {1'h0, _ctrl_io_out_bits_addr[3:0]}; + assign io_flush_valid = io_flush_valid_0; + assign io_flush_fencei = _ctrl_io_out_bits_fencei; + assign io_flush_pcNext = _ctrl_io_out_bits_pc + 32'h4; + assign io_fault_valid = imem_store_fault | io_ebus_fault_valid; + assign io_fault_bits_write = + imem_store_fault | io_ebus_fault_valid & io_ebus_fault_bits_write; + assign io_fault_bits_addr = + imem_store_fault + ? _ctrl_io_out_bits_addr + : io_ebus_fault_valid ? io_ebus_fault_bits_addr : 32'h0; + assign io_fault_bits_epc = + imem_store_fault + ? _ctrl_io_out_bits_pc + : io_ebus_fault_valid ? io_ebus_fault_bits_epc : 32'h0; + assign io_ebus_dbus_valid = io_ebus_dbus_valid_0; + assign io_ebus_dbus_write = _ctrl_io_out_bits_write; + assign io_ebus_dbus_pc = _ctrl_io_out_bits_pc; + assign io_ebus_dbus_addr = _ctrl_io_out_bits_addr; + assign io_ebus_dbus_size = _ctrl_io_out_bits_size; + assign io_ebus_dbus_wdata = wdata; + assign io_storeCount = + {1'h0, io_ebus_dbus_valid_0 & _ctrl_io_out_bits_write} + + {1'h0, io_dbus_valid_0 & _ctrl_io_out_bits_write}; + assign io_active = |{_ctrl_io_count, _data_io_count}; +endmodule + +module Arbiter4_MluCmd( + input io_in_0_valid, + input [4:0] io_in_0_bits_addr, + input [2:0] io_in_0_bits_op, + input io_in_1_valid, + input [4:0] io_in_1_bits_addr, + input [2:0] io_in_1_bits_op, + input io_in_2_valid, + input [4:0] io_in_2_bits_addr, + input [2:0] io_in_2_bits_op, + input io_in_3_valid, + input [4:0] io_in_3_bits_addr, + input [2:0] io_in_3_bits_op, + output io_out_valid, + output [4:0] io_out_bits_addr, + output [2:0] io_out_bits_op, + output [1:0] io_chosen +); + + assign io_out_valid = io_in_0_valid | io_in_1_valid | io_in_2_valid | io_in_3_valid; + assign io_out_bits_addr = + io_in_0_valid + ? io_in_0_bits_addr + : io_in_1_valid + ? io_in_1_bits_addr + : io_in_2_valid ? io_in_2_bits_addr : io_in_3_bits_addr; + assign io_out_bits_op = + io_in_0_valid + ? io_in_0_bits_op + : io_in_1_valid + ? io_in_1_bits_op + : io_in_2_valid ? io_in_2_bits_op : io_in_3_bits_op; + assign io_chosen = io_in_0_valid ? 2'h0 : io_in_1_valid ? 2'h1 : {1'h1, ~io_in_2_valid}; +endmodule + +module Queue1_MluStage1( + input clock, + reset, + io_enq_valid, + input [4:0] io_enq_bits_rd, + input [2:0] io_enq_bits_op, + input [3:0] io_enq_bits_sel, + output io_deq_valid, + output [4:0] io_deq_bits_rd, + output [2:0] io_deq_bits_op, + output [3:0] io_deq_bits_sel +); + + reg [11:0] ram; + reg full; + always @(posedge clock or posedge reset) begin + if (reset) + full <= 1'h0; + else if (~(io_enq_valid == full)) + full <= io_enq_valid; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_enq_valid) + ram <= {io_enq_bits_rd, io_enq_bits_op, io_enq_bits_sel}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + full = _RANDOM[/*Zero width*/ 1'b0][0]; + ram = _RANDOM[/*Zero width*/ 1'b0][12:1]; + `endif // RANDOMIZE_REG_INIT + if (reset) + full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_deq_valid = full; + assign io_deq_bits_rd = ram[11:7]; + assign io_deq_bits_op = ram[6:4]; + assign io_deq_bits_sel = ram[3:0]; +endmodule + +module Queue1_MluStage2( + input clock, + reset, + io_enq_valid, + input [4:0] io_enq_bits_rd, + input [2:0] io_enq_bits_op, + input [65:0] io_enq_bits_prod, + output io_deq_valid, + output [4:0] io_deq_bits_rd, + output [2:0] io_deq_bits_op, + output [65:0] io_deq_bits_prod +); + + reg [73:0] ram; + reg full; + always @(posedge clock or posedge reset) begin + if (reset) + full <= 1'h0; + else if (~(io_enq_valid == full)) + full <= io_enq_valid; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (io_enq_valid) + ram <= {io_enq_bits_rd, io_enq_bits_op, io_enq_bits_prod}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + full = _RANDOM[2'h0][0]; + ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2][10:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) + full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_deq_valid = full; + assign io_deq_bits_rd = ram[73:69]; + assign io_deq_bits_op = ram[68:66]; + assign io_deq_bits_prod = ram[65:0]; +endmodule + +module Mlu( + input clock, + reset, + io_req_0_valid, + input [4:0] io_req_0_bits_addr, + input [2:0] io_req_0_bits_op, + input io_req_1_valid, + input [4:0] io_req_1_bits_addr, + input [2:0] io_req_1_bits_op, + input io_req_2_valid, + input [4:0] io_req_2_bits_addr, + input [2:0] io_req_2_bits_op, + input io_req_3_valid, + input [4:0] io_req_3_bits_addr, + input [2:0] io_req_3_bits_op, + input io_rs1_0_valid, + input [31:0] io_rs1_0_data, + input io_rs1_1_valid, + input [31:0] io_rs1_1_data, + input io_rs1_2_valid, + input [31:0] io_rs1_2_data, + input io_rs1_3_valid, + input [31:0] io_rs1_3_data, + input io_rs2_0_valid, + input [31:0] io_rs2_0_data, + input io_rs2_1_valid, + input [31:0] io_rs2_1_data, + input io_rs2_2_valid, + input [31:0] io_rs2_2_data, + input io_rs2_3_valid, + input [31:0] io_rs2_3_data, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data +); + + wire [2:0] _stage3Input_q_io_deq_bits_op; + wire [65:0] _stage3Input_q_io_deq_bits_prod; + wire _stage2Input_q_io_deq_valid; + wire [4:0] _stage2Input_q_io_deq_bits_rd; + wire [2:0] _stage2Input_q_io_deq_bits_op; + wire [3:0] _stage2Input_q_io_deq_bits_sel; + wire _arb_io_out_valid; + wire [4:0] _arb_io_out_bits_addr; + wire [2:0] _arb_io_out_bits_op; + wire [1:0] _arb_io_chosen; + wire [31:0] rs1 = + (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[0] + ? io_rs1_0_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[1] + ? io_rs1_1_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[2] + ? io_rs1_2_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[3] + ? io_rs1_3_data + : 32'h0); + wire [31:0] rs2 = + (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[0] + ? io_rs2_0_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[1] + ? io_rs2_1_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[2] + ? io_rs2_2_data + : 32'h0) + | (_stage2Input_q_io_deq_valid & _stage2Input_q_io_deq_bits_sel[3] + ? io_rs2_3_data + : 32'h0); + wire rs2signed = _stage2Input_q_io_deq_bits_op == 3'h1; + Arbiter4_MluCmd arb ( + .io_in_0_valid (io_req_0_valid), + .io_in_0_bits_addr (io_req_0_bits_addr), + .io_in_0_bits_op (io_req_0_bits_op), + .io_in_1_valid (io_req_1_valid), + .io_in_1_bits_addr (io_req_1_bits_addr), + .io_in_1_bits_op (io_req_1_bits_op), + .io_in_2_valid (io_req_2_valid), + .io_in_2_bits_addr (io_req_2_bits_addr), + .io_in_2_bits_op (io_req_2_bits_op), + .io_in_3_valid (io_req_3_valid), + .io_in_3_bits_addr (io_req_3_bits_addr), + .io_in_3_bits_op (io_req_3_bits_op), + .io_out_valid (_arb_io_out_valid), + .io_out_bits_addr (_arb_io_out_bits_addr), + .io_out_bits_op (_arb_io_out_bits_op), + .io_chosen (_arb_io_chosen) + ); + Queue1_MluStage1 stage2Input_q ( + .clock (clock), + .reset (reset), + .io_enq_valid (_arb_io_out_valid), + .io_enq_bits_rd (_arb_io_out_bits_addr), + .io_enq_bits_op (_arb_io_out_bits_op), + .io_enq_bits_sel (4'h1 << _arb_io_chosen), + .io_deq_valid (_stage2Input_q_io_deq_valid), + .io_deq_bits_rd (_stage2Input_q_io_deq_bits_rd), + .io_deq_bits_op (_stage2Input_q_io_deq_bits_op), + .io_deq_bits_sel (_stage2Input_q_io_deq_bits_sel) + ); + Queue1_MluStage2 stage3Input_q ( + .clock (clock), + .reset (reset), + .io_enq_valid (_stage2Input_q_io_deq_valid), + .io_enq_bits_rd (_stage2Input_q_io_deq_bits_rd), + .io_enq_bits_op (_stage2Input_q_io_deq_bits_op), + .io_enq_bits_prod + ({{34{(_stage2Input_q_io_deq_bits_op == 3'h2 | rs2signed) & rs1[31]}}, rs1} + * {{34{rs2signed & rs2[31]}}, rs2}), + .io_deq_valid (io_rd_valid), + .io_deq_bits_rd (io_rd_bits_addr), + .io_deq_bits_op (_stage3Input_q_io_deq_bits_op), + .io_deq_bits_prod (_stage3Input_q_io_deq_bits_prod) + ); + assign io_rd_bits_data = + _stage3Input_q_io_deq_bits_op == 3'h0 + ? _stage3Input_q_io_deq_bits_prod[31:0] + : (|{_stage3Input_q_io_deq_bits_op == 3'h3, + _stage3Input_q_io_deq_bits_op == 3'h2, + _stage3Input_q_io_deq_bits_op == 3'h1}) + ? _stage3Input_q_io_deq_bits_prod[63:32] + : 32'h0; +endmodule + +module Dvu( + input clock, + reset, + output io_req_ready, + input io_req_valid, + input [4:0] io_req_bits_addr, + input [1:0] io_req_bits_op, + input [31:0] io_rs1_data, + io_rs2_data, + input io_rd_ready, + output io_rd_valid, + output [4:0] io_rd_bits_addr, + output [31:0] io_rd_bits_data +); + + reg active; + reg compute; + reg [4:0] addr1; + reg signed1; + reg divide1; + reg [4:0] addr2; + reg signed2d; + reg signed2r; + reg divide2; + reg [5:0] count; + reg [31:0] divide; + reg [31:0] remain; + reg [31:0] denom; + wire io_req_ready_0 = ~active & ~compute & ~(count[5]); + wire _divide1_T_1 = io_req_bits_op == 2'h0; + wire [31:0] inp = signed1 & io_rs1_data[31] ? ~io_rs1_data + 32'h1 : io_rs1_data; + wire [15:0] _clz_T_12 = {8'h0, inp[15:8]} | {inp[7:0], 8'h0}; + wire [15:0] _clz_T_22 = + {4'h0, _clz_T_12[15:4] & 12'hF0F} | {_clz_T_12[11:0] & 12'hF0F, 4'h0}; + wire [15:0] _clz_T_32 = + {2'h0, _clz_T_22[15:2] & 14'h3333} | {_clz_T_22[13:0] & 14'h3333, 2'h0}; + wire [14:0] _clz_T_42 = + _clz_T_32[15:1] & 15'h5555 | {1'h0, _clz_T_32[12:0] & 13'h1555, 1'h0}; + wire [7:0] _clz_T_53 = {4'h0, inp[23:20]} | {inp[19:16], 4'h0}; + wire [7:0] _clz_T_63 = {2'h0, _clz_T_53[7:2] & 6'h33} | {_clz_T_53[5:0] & 6'h33, 2'h0}; + wire [7:0] _clz_T_73 = {1'h0, _clz_T_63[7:1] & 7'h55} | {_clz_T_63[6:0] & 7'h55, 1'h0}; + wire [4:0] clz = + ~(|io_rs2_data) | inp[31] | inp[30] + ? 5'h0 + : inp[29] + ? 5'h1 + : inp[28] + ? 5'h2 + : inp[27] + ? 5'h3 + : inp[26] + ? 5'h4 + : inp[25] + ? 5'h5 + : inp[24] + ? 5'h6 + : _clz_T_73[0] + ? 5'h7 + : _clz_T_73[1] + ? 5'h8 + : _clz_T_73[2] + ? 5'h9 + : _clz_T_73[3] + ? 5'hA + : _clz_T_73[4] + ? 5'hB + : _clz_T_73[5] + ? 5'hC + : _clz_T_73[6] + ? 5'hD + : _clz_T_73[7] + ? 5'hE + : _clz_T_42[0] + ? 5'hF + : _clz_T_42[1] + ? 5'h10 + : _clz_T_42[2] + ? 5'h11 + : _clz_T_42[3] + ? 5'h12 + : _clz_T_42[4] + ? 5'h13 + : _clz_T_42[5] + ? 5'h14 + : _clz_T_42[6] + ? 5'h15 + : _clz_T_42[7] + ? 5'h16 + : _clz_T_42[8] + ? 5'h17 + : _clz_T_42[9] + ? 5'h18 + : _clz_T_42[10] + ? 5'h19 + : _clz_T_42[11] + ? 5'h1A + : _clz_T_42[12] + ? 5'h1B + : _clz_T_42[13] + ? 5'h1C + : _clz_T_42[14] + ? 5'h1D + : 5'h1E; + wire [62:0] _divide_T = {31'h0, inp} << clz; + wire [32:0] subtract = {1'h0, remain[30:0], divide[31]} - {1'h0, denom}; + wire _divide1_T = io_req_valid & io_req_ready_0; + always @(posedge clock or posedge reset) begin + if (reset) begin + active <= 1'h0; + compute <= 1'h0; + addr1 <= 5'h0; + signed1 <= 1'h0; + divide1 <= 1'h0; + addr2 <= 5'h0; + signed2d <= 1'h0; + signed2r <= 1'h0; + divide2 <= 1'h0; + count <= 6'h0; + divide <= 32'h0; + remain <= 32'h0; + denom <= 32'h0; + end + else begin + active <= _divide1_T | count != 6'h1E & active; + compute <= active; + if (_divide1_T) begin + addr1 <= io_req_bits_addr; + signed1 <= |{io_req_bits_op == 2'h2, _divide1_T_1}; + divide1 <= |{io_req_bits_op == 2'h1, _divide1_T_1}; + end + if (active & ~compute) begin + addr2 <= addr1; + signed2d <= signed1 & io_rs1_data[31] != io_rs2_data[31] & (|io_rs2_data); + signed2r <= signed1 & io_rs1_data[31]; + divide2 <= divide1; + count <= {1'h0, clz}; + divide <= _divide_T[31:0]; + remain <= 32'h0; + denom <= signed1 & io_rs2_data[31] ? ~io_rs2_data + 32'h1 : io_rs2_data; + end + else if (compute & ~(count[5])) begin + count <= count + 6'h1; + divide <= subtract[32] ? {divide[30:0], 1'h0} : {divide[30:0], 1'h1}; + remain <= subtract[32] ? {remain[30:0], divide[31]} : subtract[31:0]; + end + else if (count[5] & io_rd_ready) + count <= 6'h0; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + active = _RANDOM[2'h0][0]; + compute = _RANDOM[2'h0][1]; + addr1 = _RANDOM[2'h0][6:2]; + signed1 = _RANDOM[2'h0][7]; + divide1 = _RANDOM[2'h0][8]; + addr2 = _RANDOM[2'h0][13:9]; + signed2d = _RANDOM[2'h0][14]; + signed2r = _RANDOM[2'h0][15]; + divide2 = _RANDOM[2'h0][16]; + count = _RANDOM[2'h0][22:17]; + divide = {_RANDOM[2'h0][31:23], _RANDOM[2'h1][22:0]}; + remain = {_RANDOM[2'h1][31:23], _RANDOM[2'h2][22:0]}; + denom = {_RANDOM[2'h2][31:23], _RANDOM[2'h3][22:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + active = 1'h0; + compute = 1'h0; + addr1 = 5'h0; + signed1 = 1'h0; + divide1 = 1'h0; + addr2 = 5'h0; + signed2d = 1'h0; + signed2r = 1'h0; + divide2 = 1'h0; + count = 6'h0; + divide = 32'h0; + remain = 32'h0; + denom = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_req_ready = io_req_ready_0; + assign io_rd_valid = count[5]; + assign io_rd_bits_addr = addr2; + assign io_rd_bits_data = + divide2 ? (signed2d ? ~divide + 32'h1 : divide) : signed2r ? ~remain + 32'h1 : remain; +endmodule + +module FaultManager( + input io_in_fault_0_csr, + io_in_fault_0_jal, + io_in_fault_0_jalr, + io_in_fault_0_bxx, + io_in_fault_0_undef, + io_in_fault_1_jal, + io_in_fault_1_jalr, + io_in_fault_1_bxx, + io_in_fault_2_jal, + io_in_fault_2_jalr, + io_in_fault_2_bxx, + io_in_fault_3_jal, + io_in_fault_3_jalr, + io_in_fault_3_bxx, + input [31:0] io_in_pc_0_pc, + io_in_pc_1_pc, + io_in_pc_2_pc, + io_in_pc_3_pc, + input io_in_memory_fault_valid, + io_in_memory_fault_bits_write, + input [31:0] io_in_memory_fault_bits_addr, + io_in_memory_fault_bits_epc, + input io_in_ibus_fault, + input [31:0] io_in_undef_0_inst, + io_in_undef_1_inst, + io_in_undef_2_inst, + io_in_undef_3_inst, + io_in_jal_0_target, + io_in_jal_1_target, + io_in_jal_2_target, + io_in_jal_3_target, + io_in_jalr_0_target, + io_in_jalr_1_target, + io_in_jalr_2_target, + io_in_jalr_3_target, + output io_out_valid, + output [31:0] io_out_bits_mepc, + io_out_bits_mtval, + io_out_bits_mcause +); + + wire faults_0 = + io_in_fault_0_csr | io_in_fault_0_jal | io_in_fault_0_jalr | io_in_fault_0_bxx + | io_in_fault_0_undef; + wire faults_1 = io_in_fault_1_jal | io_in_fault_1_jalr | io_in_fault_1_bxx; + wire faults_2 = io_in_fault_2_jal | io_in_fault_2_jalr | io_in_fault_2_bxx; + wire fault = + faults_0 | faults_1 | faults_2 | io_in_fault_3_jal | io_in_fault_3_jalr + | io_in_fault_3_bxx; + wire [1:0] first_fault = faults_0 ? 2'h0 : faults_1 ? 2'h1 : {1'h1, ~faults_2}; + wire [1:0] undef_fault_idx = io_in_fault_0_undef ? 2'h0 : 2'h3; + wire jal_fault = + io_in_fault_0_jal | io_in_fault_1_jal | io_in_fault_2_jal | io_in_fault_3_jal; + wire [1:0] jal_fault_idx = + io_in_fault_0_jal ? 2'h0 : io_in_fault_1_jal ? 2'h1 : {1'h1, ~io_in_fault_2_jal}; + wire jalr_fault = + io_in_fault_0_jalr | io_in_fault_1_jalr | io_in_fault_2_jalr | io_in_fault_3_jalr; + wire [1:0] jalr_fault_idx = + io_in_fault_0_jalr ? 2'h0 : io_in_fault_1_jalr ? 2'h1 : {1'h1, ~io_in_fault_2_jalr}; + wire bxx_fault = + io_in_fault_0_bxx | io_in_fault_1_bxx | io_in_fault_2_bxx | io_in_fault_3_bxx; + wire instr_access_fault = io_in_memory_fault_valid & io_in_ibus_fault; + wire load_fault = + io_in_memory_fault_valid & ~io_in_memory_fault_bits_write & ~io_in_ibus_fault; + wire store_fault = + io_in_memory_fault_valid & io_in_memory_fault_bits_write & ~io_in_ibus_fault; + wire [3:0][31:0] _GEN = + {{io_in_pc_3_pc}, {io_in_pc_2_pc}, {io_in_pc_1_pc}, {io_in_pc_0_pc}}; + wire _io_out_bits_mtval_T = + (io_in_fault_0_csr ? 2'h0 : 2'h3) == first_fault; + wire _io_out_bits_mtval_T_2 = jal_fault_idx == first_fault; + wire _io_out_bits_mtval_T_4 = jalr_fault_idx == first_fault; + wire _io_out_bits_mtval_T_7 = + (io_in_fault_0_bxx + ? 2'h0 + : io_in_fault_1_bxx ? 2'h1 : {1'h1, ~io_in_fault_2_bxx}) == first_fault; + wire _io_out_bits_mtval_T_9 = undef_fault_idx == first_fault; + wire [3:0][31:0] _GEN_0 = + {{io_in_jalr_3_target}, + {io_in_jalr_2_target}, + {io_in_jalr_1_target}, + {io_in_jalr_0_target}}; + wire [3:0][31:0] _GEN_1 = + {{io_in_undef_3_inst}, + {io_in_undef_2_inst}, + {io_in_undef_1_inst}, + {io_in_undef_0_inst}}; + wire [3:0][31:0] _GEN_2 = + {{io_in_jal_3_target}, + {io_in_jal_2_target}, + {io_in_jal_1_target}, + {io_in_jal_0_target}}; + assign io_out_valid = fault | io_in_memory_fault_valid; + assign io_out_bits_mepc = + load_fault | store_fault | instr_access_fault + ? io_in_memory_fault_bits_epc + : fault ? _GEN[first_fault] : 32'h0; + assign io_out_bits_mtval = + load_fault | store_fault + ? io_in_memory_fault_bits_addr + : instr_access_fault | io_in_fault_0_csr & _io_out_bits_mtval_T + ? 32'h0 + : jal_fault & _io_out_bits_mtval_T_2 + ? _GEN_2[jal_fault_idx] + : jalr_fault & _io_out_bits_mtval_T_4 + ? _GEN_0[jalr_fault_idx] & 32'hFFFFFFFE + : bxx_fault & _io_out_bits_mtval_T_7 + | ~(io_in_fault_0_undef & _io_out_bits_mtval_T_9) + ? 32'h0 + : _GEN_1[undef_fault_idx]; + assign io_out_bits_mcause = + load_fault + ? 32'h5 + : store_fault + ? 32'h7 + : instr_access_fault + ? 32'h1 + : io_in_fault_0_csr & _io_out_bits_mtval_T + ? 32'h2 + : jal_fault & _io_out_bits_mtval_T_2 | jalr_fault + & _io_out_bits_mtval_T_4 | bxx_fault & _io_out_bits_mtval_T_7 + ? 32'h0 + : {30'h0, io_in_fault_0_undef & _io_out_bits_mtval_T_9, 1'h0}; +endmodule + +module Queue1_FloatInstruction( + input clock, + reset, + io_enq_valid, + input [2:0] io_enq_bits_opcode, + input [4:0] io_enq_bits_funct5, + io_enq_bits_rs3, + io_enq_bits_rs2, + io_enq_bits_rs1, + input [2:0] io_enq_bits_rm, + input [31:0] io_enq_bits_inst, + io_enq_bits_pc, + input io_enq_bits_scalar_rd, + io_enq_bits_scalar_rs1, + input [4:0] io_enq_bits_rd, + input io_enq_bits_uses_rs3, + io_enq_bits_uses_rs2, + io_deq_ready, + output io_deq_valid, + output [2:0] io_deq_bits_opcode, + output [4:0] io_deq_bits_funct5, + io_deq_bits_rs3, + io_deq_bits_rs2, + io_deq_bits_rs1, + output [2:0] io_deq_bits_rm, + output io_deq_bits_scalar_rd, + output [4:0] io_deq_bits_rd, + output io_count +); + + reg [98:0] ram; + wire io_enq_ready; + reg full; + wire do_enq = io_enq_ready & io_enq_valid; + assign io_enq_ready = ~full; + always @(posedge clock or posedge reset) begin + if (reset) + full <= 1'h0; + else if (~(do_enq == (io_deq_ready & full))) + full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= + {io_enq_bits_opcode, + io_enq_bits_funct5, + io_enq_bits_rs3, + io_enq_bits_rs2, + io_enq_bits_rs1, + io_enq_bits_rm, + io_enq_bits_inst, + io_enq_bits_pc, + io_enq_bits_scalar_rd, + io_enq_bits_scalar_rs1, + io_enq_bits_rd, + io_enq_bits_uses_rs3, + io_enq_bits_uses_rs2}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:3]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin + _RANDOM[i[1:0]] = `RANDOM; + end + full = _RANDOM[2'h0][0]; + ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2], _RANDOM[2'h3][3:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) + full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_deq_valid = full; + assign io_deq_bits_opcode = ram[98:96]; + assign io_deq_bits_funct5 = ram[95:91]; + assign io_deq_bits_rs3 = ram[90:86]; + assign io_deq_bits_rs2 = ram[85:81]; + assign io_deq_bits_rs1 = ram[80:76]; + assign io_deq_bits_rm = ram[75:73]; + assign io_deq_bits_scalar_rd = ram[8]; + assign io_deq_bits_rd = ram[6:2]; + assign io_count = full; +endmodule + + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +// VCS coverage exclude_module +module ram_2x37( + input R0_addr, + R0_en, + R0_clk, + output [36:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [36:0] W0_data +); + + reg [36:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [63:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + for (logic [6:0] j = 7'h0; j < 7'h40; j += 7'h20) begin + _RANDOM_MEM[j[5:0] +: 32] = `RANDOM; + end + Memory[i[0]] = _RANDOM_MEM[36:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 37'bx; +endmodule + +module Queue2_RegfileWriteDataIO( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [4:0] io_enq_bits_addr, + input [31:0] io_enq_bits_data, + input io_deq_ready, + output io_deq_valid, + output [4:0] io_deq_bits_addr, + output [31:0] io_deq_bits_data +); + + wire [36:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + wrap = _RANDOM[/*Zero width*/ 1'b0][0]; + wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + wrap = 1'h0; + wrap_1 = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x37 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_addr, io_enq_bits_data}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_addr = _ram_ext_R0_data[36:32]; + assign io_deq_bits_data = _ram_ext_R0_data[31:0]; +endmodule + +module FloatCore( + input clock, + reset, + output io_inst_ready, + input io_inst_valid, + input [2:0] io_inst_bits_opcode, + input [4:0] io_inst_bits_funct5, + io_inst_bits_rs3, + io_inst_bits_rs2, + io_inst_bits_rs1, + input [2:0] io_inst_bits_rm, + input [31:0] io_inst_bits_inst, + io_inst_bits_pc, + input io_inst_bits_scalar_rd, + io_inst_bits_scalar_rs1, + input [4:0] io_inst_bits_rd, + input io_inst_bits_uses_rs3, + io_inst_bits_uses_rs2, + output io_read_ports_0_valid, + output [4:0] io_read_ports_0_addr, + input [22:0] io_read_ports_0_data_mantissa, + input [7:0] io_read_ports_0_data_exponent, + input io_read_ports_0_data_sign, + output io_read_ports_1_valid, + output [4:0] io_read_ports_1_addr, + input [22:0] io_read_ports_1_data_mantissa, + input [7:0] io_read_ports_1_data_exponent, + input io_read_ports_1_data_sign, + output io_read_ports_2_valid, + output [4:0] io_read_ports_2_addr, + input [22:0] io_read_ports_2_data_mantissa, + input [7:0] io_read_ports_2_data_exponent, + input io_read_ports_2_data_sign, + output io_write_ports_0_valid, + output [4:0] io_write_ports_0_addr, + output [22:0] io_write_ports_0_data_mantissa, + output [7:0] io_write_ports_0_data_exponent, + output io_write_ports_0_data_sign, + io_write_ports_1_valid, + output [4:0] io_write_ports_1_addr, + output [22:0] io_write_ports_1_data_mantissa, + output [7:0] io_write_ports_1_data_exponent, + output io_write_ports_1_data_sign, + input [31:0] io_rs1_data, + input io_scalar_rd_ready, + output io_scalar_rd_valid, + output [4:0] io_scalar_rd_bits_addr, + output [31:0] io_scalar_rd_bits_data, + output io_csr_in_fflags_valid, + output [4:0] io_csr_in_fflags_bits, + input [2:0] io_csr_out_frm, + input io_lsu_rd_valid, + input [4:0] io_lsu_rd_bits_addr, + input [31:0] io_lsu_rd_bits_data +); + + wire instQueue_io_deq_ready; + wire _floatCoreWrapper_io_out_ready_i_T_4; + wire _floatCoreWrapper_io_in_valid_i_T_3; + wire _scalar_rd_pipe_q_io_enq_ready; + wire _floatCoreWrapper_in_ready_o; + wire _floatCoreWrapper_out_valid_o; + wire [31:0] _floatCoreWrapper_result_o; + wire _instQueue_io_deq_valid; + wire [2:0] _instQueue_io_deq_bits_opcode; + wire [4:0] _instQueue_io_deq_bits_funct5; + wire [4:0] _instQueue_io_deq_bits_rs3; + wire [4:0] _instQueue_io_deq_bits_rs2; + wire [4:0] _instQueue_io_deq_bits_rs1; + wire [2:0] _instQueue_io_deq_bits_rm; + wire _instQueue_io_deq_bits_scalar_rd; + wire [4:0] _instQueue_io_deq_bits_rd; + wire _instQueue_io_count; + wire _opfp_mod_T_6 = _instQueue_io_deq_bits_funct5 == 5'h4; + wire _opfp_mod_T_8 = _instQueue_io_deq_bits_funct5 == 5'h18; + wire _fmv_x_w_T_2 = _instQueue_io_deq_bits_funct5 == 5'h1C; + wire _opfp_mod_T_10 = _instQueue_io_deq_bits_funct5 == 5'h1A; + wire [3:0] opfp_operation = + _opfp_mod_T_10 + ? 4'hC + : _fmv_x_w_T_2 + ? 4'h9 + : _instQueue_io_deq_bits_funct5 == 5'h14 + ? 4'h8 + : _opfp_mod_T_8 + ? 4'hB + : {1'h0, + _instQueue_io_deq_bits_funct5 == 5'h5 + ? 3'h7 + : _opfp_mod_T_6 + ? 3'h6 + : _instQueue_io_deq_bits_funct5 == 5'hB + ? 3'h5 + : _instQueue_io_deq_bits_funct5 == 5'h3 + ? 3'h4 + : {2'h1, _instQueue_io_deq_bits_funct5 == 5'h2}}; + wire [7:0][3:0] _GEN = + {{4'h2}, {4'h1}, {4'h1}, {4'h0}, {4'h0}, {opfp_operation}, {4'hF}, {4'h2}}; + wire [3:0] op_i = _GEN[_instQueue_io_deq_bits_opcode]; + wire _read_port_2_valid_T = op_i == 4'h0; + wire _read_port_2_valid_T_1 = op_i == 4'h1; + wire _fmv_w_x_T = _instQueue_io_deq_bits_opcode == 3'h2; + wire _floatCoreWrapper_io_operands_i_0_T_1 = opfp_operation == 4'hC; + wire _fmv_w_x_T_4 = _instQueue_io_deq_bits_rm == 3'h0; + wire fmv_x_w = + _instQueue_io_deq_valid & _fmv_w_x_T & _fmv_x_w_T_2 & _fmv_w_x_T_4; + wire fmv_w_x = + _instQueue_io_deq_valid & _fmv_w_x_T & _instQueue_io_deq_bits_funct5 == 5'h1E + & _fmv_w_x_T_4; + wire fmv = fmv_x_w | fmv_w_x; + wire _op2_addr_T = op_i == 4'h2; + reg fpuActive; + wire _io_csr_in_fflags_valid_T = + instQueue_io_deq_ready & _instQueue_io_deq_valid; + wire _instQueue_io_deq_ready_T = + _floatCoreWrapper_io_in_valid_i_T_3 & _floatCoreWrapper_in_ready_o; + assign _floatCoreWrapper_io_in_valid_i_T_3 = + _instQueue_io_deq_valid & ~fmv & ~fpuActive; + wire [31:0] _io_write_ports_0_data_T = + fmv_w_x ? io_rs1_data : _floatCoreWrapper_result_o; + assign _floatCoreWrapper_io_out_ready_i_T_4 = + _instQueue_io_deq_valid & _instQueue_io_deq_bits_scalar_rd + & _scalar_rd_pipe_q_io_enq_ready | _instQueue_io_deq_valid + & ~_instQueue_io_deq_bits_scalar_rd; + assign instQueue_io_deq_ready = + (_instQueue_io_deq_ready_T | fpuActive) & _floatCoreWrapper_io_out_ready_i_T_4 + & _floatCoreWrapper_out_valid_o | fmv; + always @(posedge clock or posedge reset) begin + if (reset) + fpuActive <= 1'h0; + else + fpuActive <= ~_io_csr_in_fflags_valid_T & (_instQueue_io_deq_ready_T | fpuActive); + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + fpuActive = _RANDOM[/*Zero width*/ 1'b0][0]; + `endif // RANDOMIZE_REG_INIT + if (reset) + fpuActive = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Queue1_FloatInstruction instQueue ( + .clock (clock), + .reset (reset), + .io_enq_valid (io_inst_valid), + .io_enq_bits_opcode (io_inst_bits_opcode), + .io_enq_bits_funct5 (io_inst_bits_funct5), + .io_enq_bits_rs3 (io_inst_bits_rs3), + .io_enq_bits_rs2 (io_inst_bits_rs2), + .io_enq_bits_rs1 (io_inst_bits_rs1), + .io_enq_bits_rm (io_inst_bits_rm), + .io_enq_bits_inst (io_inst_bits_inst), + .io_enq_bits_pc (io_inst_bits_pc), + .io_enq_bits_scalar_rd (io_inst_bits_scalar_rd), + .io_enq_bits_scalar_rs1 (io_inst_bits_scalar_rs1), + .io_enq_bits_rd (io_inst_bits_rd), + .io_enq_bits_uses_rs3 (io_inst_bits_uses_rs3), + .io_enq_bits_uses_rs2 (io_inst_bits_uses_rs2), + .io_deq_ready (instQueue_io_deq_ready), + .io_deq_valid (_instQueue_io_deq_valid), + .io_deq_bits_opcode (_instQueue_io_deq_bits_opcode), + .io_deq_bits_funct5 (_instQueue_io_deq_bits_funct5), + .io_deq_bits_rs3 (_instQueue_io_deq_bits_rs3), + .io_deq_bits_rs2 (_instQueue_io_deq_bits_rs2), + .io_deq_bits_rs1 (_instQueue_io_deq_bits_rs1), + .io_deq_bits_rm (_instQueue_io_deq_bits_rm), + .io_deq_bits_scalar_rd (_instQueue_io_deq_bits_scalar_rd), + .io_deq_bits_rd (_instQueue_io_deq_bits_rd), + .io_count (_instQueue_io_count) + ); + FloatCoreWrapper floatCoreWrapper ( + .clk_i (clock), + .rst_ni (~reset), + .in_valid_i (_floatCoreWrapper_io_in_valid_i_T_3), + .in_ready_o (_floatCoreWrapper_in_ready_o), + .operands_i_0 + (_fmv_w_x_T & _floatCoreWrapper_io_operands_i_0_T_1 + ? io_rs1_data + : {io_read_ports_0_data_sign, + io_read_ports_0_data_exponent, + io_read_ports_0_data_mantissa}), + .operands_i_1 + ({io_read_ports_1_data_sign, + io_read_ports_1_data_exponent, + io_read_ports_1_data_mantissa}), + .operands_i_2 + ({io_read_ports_2_data_sign, + io_read_ports_2_data_exponent, + io_read_ports_2_data_mantissa}), + .op_i (op_i), + .op_mod_i + (_instQueue_io_deq_bits_opcode != 3'h6 + & (_instQueue_io_deq_bits_opcode == 3'h5 | _instQueue_io_deq_bits_opcode == 3'h4 + | _instQueue_io_deq_bits_opcode != 3'h3 & _instQueue_io_deq_bits_opcode == 3'h2 + & (_opfp_mod_T_10 | _opfp_mod_T_8 + ? _instQueue_io_deq_bits_rs2[0] + : _opfp_mod_T_6 | _instQueue_io_deq_bits_funct5 == 5'h1))), + .rnd_mode_i + ((&_instQueue_io_deq_bits_rm) ? io_csr_out_frm : _instQueue_io_deq_bits_rm), + .flush_i (1'h0), + .out_valid_o (_floatCoreWrapper_out_valid_o), + .out_ready_i (_floatCoreWrapper_io_out_ready_i_T_4), + .result_o (_floatCoreWrapper_result_o), + .status_o (io_csr_in_fflags_bits), + .busy_o (/* unused */) + ); + Queue2_RegfileWriteDataIO scalar_rd_pipe_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (_scalar_rd_pipe_q_io_enq_ready), + .io_enq_valid + ((_instQueue_io_deq_ready_T | fpuActive) & _floatCoreWrapper_out_valid_o + & _floatCoreWrapper_io_out_ready_i_T_4 & _instQueue_io_deq_bits_scalar_rd + | fmv_x_w), + .io_enq_bits_addr (_instQueue_io_deq_bits_rd), + .io_enq_bits_data + (fmv_x_w + ? {io_read_ports_0_data_sign, + io_read_ports_0_data_exponent, + io_read_ports_0_data_mantissa} + : _floatCoreWrapper_result_o), + .io_deq_ready (io_scalar_rd_ready), + .io_deq_valid (io_scalar_rd_valid), + .io_deq_bits_addr (io_scalar_rd_bits_addr), + .io_deq_bits_data (io_scalar_rd_bits_data) + ); + assign io_inst_ready = ~_instQueue_io_count; + assign io_read_ports_0_valid = op_i != 4'h2 & _instQueue_io_deq_valid; + assign io_read_ports_0_addr = _instQueue_io_deq_bits_rs1; + assign io_read_ports_1_valid = + ((|{_read_port_2_valid_T_1, _read_port_2_valid_T}) | _fmv_w_x_T + & {_floatCoreWrapper_io_operands_i_0_T_1, + opfp_operation == 4'hB, + opfp_operation == 4'h9, + opfp_operation == 4'h5} == 4'h0) & _instQueue_io_deq_valid; + assign io_read_ports_1_addr = + _op2_addr_T ? _instQueue_io_deq_bits_rs1 : _instQueue_io_deq_bits_rs2; + assign io_read_ports_2_valid = + ((|{_read_port_2_valid_T_1, _read_port_2_valid_T}) | _fmv_w_x_T + & opfp_operation == 4'h2) & _instQueue_io_deq_valid; + assign io_read_ports_2_addr = + _op2_addr_T ? _instQueue_io_deq_bits_rs2 : _instQueue_io_deq_bits_rs3; + assign io_write_ports_0_valid = + (_floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T + & ~_instQueue_io_deq_bits_scalar_rd | fmv_w_x) + & ~(_instQueue_io_deq_valid & _instQueue_io_deq_bits_opcode == 3'h1); + assign io_write_ports_0_addr = _instQueue_io_deq_bits_rd; + assign io_write_ports_0_data_mantissa = _io_write_ports_0_data_T[22:0]; + assign io_write_ports_0_data_exponent = _io_write_ports_0_data_T[30:23]; + assign io_write_ports_0_data_sign = _io_write_ports_0_data_T[31]; + assign io_write_ports_1_valid = io_lsu_rd_valid; + assign io_write_ports_1_addr = io_lsu_rd_bits_addr; + assign io_write_ports_1_data_mantissa = io_lsu_rd_bits_data[22:0]; + assign io_write_ports_1_data_exponent = io_lsu_rd_bits_data[30:23]; + assign io_write_ports_1_data_sign = io_lsu_rd_bits_data[31]; + assign io_csr_in_fflags_valid = + _floatCoreWrapper_out_valid_o & _io_csr_in_fflags_valid_T & ~fmv; +endmodule + +module FRegfile( + input clock, + reset, + io_read_ports_0_valid, + input [4:0] io_read_ports_0_addr, + output [22:0] io_read_ports_0_data_mantissa, + output [7:0] io_read_ports_0_data_exponent, + output io_read_ports_0_data_sign, + input io_read_ports_1_valid, + input [4:0] io_read_ports_1_addr, + output [22:0] io_read_ports_1_data_mantissa, + output [7:0] io_read_ports_1_data_exponent, + output io_read_ports_1_data_sign, + input io_read_ports_2_valid, + input [4:0] io_read_ports_2_addr, + output [22:0] io_read_ports_2_data_mantissa, + output [7:0] io_read_ports_2_data_exponent, + output io_read_ports_2_data_sign, + input io_write_ports_0_valid, + input [4:0] io_write_ports_0_addr, + input [22:0] io_write_ports_0_data_mantissa, + input [7:0] io_write_ports_0_data_exponent, + input io_write_ports_0_data_sign, + io_write_ports_1_valid, + input [4:0] io_write_ports_1_addr, + input [22:0] io_write_ports_1_data_mantissa, + input [7:0] io_write_ports_1_data_exponent, + input io_write_ports_1_data_sign, + input [31:0] io_scoreboard_set, + output [31:0] io_scoreboard, + io_busPort_data_0, + input [4:0] io_busPortAddr +); + + reg [22:0] fregfile_0_mantissa; + reg [7:0] fregfile_0_exponent; + reg fregfile_0_sign; + reg [22:0] fregfile_1_mantissa; + reg [7:0] fregfile_1_exponent; + reg fregfile_1_sign; + reg [22:0] fregfile_2_mantissa; + reg [7:0] fregfile_2_exponent; + reg fregfile_2_sign; + reg [22:0] fregfile_3_mantissa; + reg [7:0] fregfile_3_exponent; + reg fregfile_3_sign; + reg [22:0] fregfile_4_mantissa; + reg [7:0] fregfile_4_exponent; + reg fregfile_4_sign; + reg [22:0] fregfile_5_mantissa; + reg [7:0] fregfile_5_exponent; + reg fregfile_5_sign; + reg [22:0] fregfile_6_mantissa; + reg [7:0] fregfile_6_exponent; + reg fregfile_6_sign; + reg [22:0] fregfile_7_mantissa; + reg [7:0] fregfile_7_exponent; + reg fregfile_7_sign; + reg [22:0] fregfile_8_mantissa; + reg [7:0] fregfile_8_exponent; + reg fregfile_8_sign; + reg [22:0] fregfile_9_mantissa; + reg [7:0] fregfile_9_exponent; + reg fregfile_9_sign; + reg [22:0] fregfile_10_mantissa; + reg [7:0] fregfile_10_exponent; + reg fregfile_10_sign; + reg [22:0] fregfile_11_mantissa; + reg [7:0] fregfile_11_exponent; + reg fregfile_11_sign; + reg [22:0] fregfile_12_mantissa; + reg [7:0] fregfile_12_exponent; + reg fregfile_12_sign; + reg [22:0] fregfile_13_mantissa; + reg [7:0] fregfile_13_exponent; + reg fregfile_13_sign; + reg [22:0] fregfile_14_mantissa; + reg [7:0] fregfile_14_exponent; + reg fregfile_14_sign; + reg [22:0] fregfile_15_mantissa; + reg [7:0] fregfile_15_exponent; + reg fregfile_15_sign; + reg [22:0] fregfile_16_mantissa; + reg [7:0] fregfile_16_exponent; + reg fregfile_16_sign; + reg [22:0] fregfile_17_mantissa; + reg [7:0] fregfile_17_exponent; + reg fregfile_17_sign; + reg [22:0] fregfile_18_mantissa; + reg [7:0] fregfile_18_exponent; + reg fregfile_18_sign; + reg [22:0] fregfile_19_mantissa; + reg [7:0] fregfile_19_exponent; + reg fregfile_19_sign; + reg [22:0] fregfile_20_mantissa; + reg [7:0] fregfile_20_exponent; + reg fregfile_20_sign; + reg [22:0] fregfile_21_mantissa; + reg [7:0] fregfile_21_exponent; + reg fregfile_21_sign; + reg [22:0] fregfile_22_mantissa; + reg [7:0] fregfile_22_exponent; + reg fregfile_22_sign; + reg [22:0] fregfile_23_mantissa; + reg [7:0] fregfile_23_exponent; + reg fregfile_23_sign; + reg [22:0] fregfile_24_mantissa; + reg [7:0] fregfile_24_exponent; + reg fregfile_24_sign; + reg [22:0] fregfile_25_mantissa; + reg [7:0] fregfile_25_exponent; + reg fregfile_25_sign; + reg [22:0] fregfile_26_mantissa; + reg [7:0] fregfile_26_exponent; + reg fregfile_26_sign; + reg [22:0] fregfile_27_mantissa; + reg [7:0] fregfile_27_exponent; + reg fregfile_27_sign; + reg [22:0] fregfile_28_mantissa; + reg [7:0] fregfile_28_exponent; + reg fregfile_28_sign; + reg [22:0] fregfile_29_mantissa; + reg [7:0] fregfile_29_exponent; + reg fregfile_29_sign; + reg [22:0] fregfile_30_mantissa; + reg [7:0] fregfile_30_exponent; + reg fregfile_30_sign; + reg [22:0] fregfile_31_mantissa; + reg [7:0] fregfile_31_exponent; + reg fregfile_31_sign; + reg [31:0] scoreboard; + reg scoreboard_error; + wire [31:0][22:0] _GEN = + {{fregfile_31_mantissa}, + {fregfile_30_mantissa}, + {fregfile_29_mantissa}, + {fregfile_28_mantissa}, + {fregfile_27_mantissa}, + {fregfile_26_mantissa}, + {fregfile_25_mantissa}, + {fregfile_24_mantissa}, + {fregfile_23_mantissa}, + {fregfile_22_mantissa}, + {fregfile_21_mantissa}, + {fregfile_20_mantissa}, + {fregfile_19_mantissa}, + {fregfile_18_mantissa}, + {fregfile_17_mantissa}, + {fregfile_16_mantissa}, + {fregfile_15_mantissa}, + {fregfile_14_mantissa}, + {fregfile_13_mantissa}, + {fregfile_12_mantissa}, + {fregfile_11_mantissa}, + {fregfile_10_mantissa}, + {fregfile_9_mantissa}, + {fregfile_8_mantissa}, + {fregfile_7_mantissa}, + {fregfile_6_mantissa}, + {fregfile_5_mantissa}, + {fregfile_4_mantissa}, + {fregfile_3_mantissa}, + {fregfile_2_mantissa}, + {fregfile_1_mantissa}, + {fregfile_0_mantissa}}; + wire [31:0][7:0] _GEN_0 = + {{fregfile_31_exponent}, + {fregfile_30_exponent}, + {fregfile_29_exponent}, + {fregfile_28_exponent}, + {fregfile_27_exponent}, + {fregfile_26_exponent}, + {fregfile_25_exponent}, + {fregfile_24_exponent}, + {fregfile_23_exponent}, + {fregfile_22_exponent}, + {fregfile_21_exponent}, + {fregfile_20_exponent}, + {fregfile_19_exponent}, + {fregfile_18_exponent}, + {fregfile_17_exponent}, + {fregfile_16_exponent}, + {fregfile_15_exponent}, + {fregfile_14_exponent}, + {fregfile_13_exponent}, + {fregfile_12_exponent}, + {fregfile_11_exponent}, + {fregfile_10_exponent}, + {fregfile_9_exponent}, + {fregfile_8_exponent}, + {fregfile_7_exponent}, + {fregfile_6_exponent}, + {fregfile_5_exponent}, + {fregfile_4_exponent}, + {fregfile_3_exponent}, + {fregfile_2_exponent}, + {fregfile_1_exponent}, + {fregfile_0_exponent}}; + wire [31:0] _GEN_1 = + {{fregfile_31_sign}, + {fregfile_30_sign}, + {fregfile_29_sign}, + {fregfile_28_sign}, + {fregfile_27_sign}, + {fregfile_26_sign}, + {fregfile_25_sign}, + {fregfile_24_sign}, + {fregfile_23_sign}, + {fregfile_22_sign}, + {fregfile_21_sign}, + {fregfile_20_sign}, + {fregfile_19_sign}, + {fregfile_18_sign}, + {fregfile_17_sign}, + {fregfile_16_sign}, + {fregfile_15_sign}, + {fregfile_14_sign}, + {fregfile_13_sign}, + {fregfile_12_sign}, + {fregfile_11_sign}, + {fregfile_10_sign}, + {fregfile_9_sign}, + {fregfile_8_sign}, + {fregfile_7_sign}, + {fregfile_6_sign}, + {fregfile_5_sign}, + {fregfile_4_sign}, + {fregfile_3_sign}, + {fregfile_2_sign}, + {fregfile_1_sign}, + {fregfile_0_sign}}; + wire _io_busPort_data_0_T_1 = + io_write_ports_0_valid & io_write_ports_0_addr == io_read_ports_1_addr; + wire [31:0] scoreboard_clr = + (io_write_ports_0_valid ? 32'h1 << io_write_ports_0_addr : 32'h0) + | (io_write_ports_1_valid ? 32'h1 << io_write_ports_1_addr : 32'h0); + wire valid_0 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h0; + wire valid_0_1 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1; + wire valid_0_2 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h2; + wire valid_0_3 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h3; + wire valid_0_4 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h4; + wire valid_0_5 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h5; + wire valid_0_6 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h6; + wire valid_0_7 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h7; + wire valid_0_8 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h8; + wire valid_0_9 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h9; + wire valid_0_10 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hA; + wire valid_0_11 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hB; + wire valid_0_12 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hC; + wire valid_0_13 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hD; + wire valid_0_14 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hE; + wire valid_0_15 = io_write_ports_0_valid & io_write_ports_0_addr == 5'hF; + wire valid_0_16 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h10; + wire valid_0_17 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h11; + wire valid_0_18 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h12; + wire valid_0_19 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h13; + wire valid_0_20 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h14; + wire valid_0_21 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h15; + wire valid_0_22 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h16; + wire valid_0_23 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h17; + wire valid_0_24 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h18; + wire valid_0_25 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h19; + wire valid_0_26 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1A; + wire valid_0_27 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1B; + wire valid_0_28 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1C; + wire valid_0_29 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1D; + wire valid_0_30 = io_write_ports_0_valid & io_write_ports_0_addr == 5'h1E; + wire valid_0_31 = io_write_ports_0_valid & (&io_write_ports_0_addr); + always @(posedge clock or posedge reset) begin + if (reset) begin + fregfile_0_mantissa <= 23'h0; + fregfile_0_exponent <= 8'h0; + fregfile_0_sign <= 1'h0; + fregfile_1_mantissa <= 23'h0; + fregfile_1_exponent <= 8'h0; + fregfile_1_sign <= 1'h0; + fregfile_2_mantissa <= 23'h0; + fregfile_2_exponent <= 8'h0; + fregfile_2_sign <= 1'h0; + fregfile_3_mantissa <= 23'h0; + fregfile_3_exponent <= 8'h0; + fregfile_3_sign <= 1'h0; + fregfile_4_mantissa <= 23'h0; + fregfile_4_exponent <= 8'h0; + fregfile_4_sign <= 1'h0; + fregfile_5_mantissa <= 23'h0; + fregfile_5_exponent <= 8'h0; + fregfile_5_sign <= 1'h0; + fregfile_6_mantissa <= 23'h0; + fregfile_6_exponent <= 8'h0; + fregfile_6_sign <= 1'h0; + fregfile_7_mantissa <= 23'h0; + fregfile_7_exponent <= 8'h0; + fregfile_7_sign <= 1'h0; + fregfile_8_mantissa <= 23'h0; + fregfile_8_exponent <= 8'h0; + fregfile_8_sign <= 1'h0; + fregfile_9_mantissa <= 23'h0; + fregfile_9_exponent <= 8'h0; + fregfile_9_sign <= 1'h0; + fregfile_10_mantissa <= 23'h0; + fregfile_10_exponent <= 8'h0; + fregfile_10_sign <= 1'h0; + fregfile_11_mantissa <= 23'h0; + fregfile_11_exponent <= 8'h0; + fregfile_11_sign <= 1'h0; + fregfile_12_mantissa <= 23'h0; + fregfile_12_exponent <= 8'h0; + fregfile_12_sign <= 1'h0; + fregfile_13_mantissa <= 23'h0; + fregfile_13_exponent <= 8'h0; + fregfile_13_sign <= 1'h0; + fregfile_14_mantissa <= 23'h0; + fregfile_14_exponent <= 8'h0; + fregfile_14_sign <= 1'h0; + fregfile_15_mantissa <= 23'h0; + fregfile_15_exponent <= 8'h0; + fregfile_15_sign <= 1'h0; + fregfile_16_mantissa <= 23'h0; + fregfile_16_exponent <= 8'h0; + fregfile_16_sign <= 1'h0; + fregfile_17_mantissa <= 23'h0; + fregfile_17_exponent <= 8'h0; + fregfile_17_sign <= 1'h0; + fregfile_18_mantissa <= 23'h0; + fregfile_18_exponent <= 8'h0; + fregfile_18_sign <= 1'h0; + fregfile_19_mantissa <= 23'h0; + fregfile_19_exponent <= 8'h0; + fregfile_19_sign <= 1'h0; + fregfile_20_mantissa <= 23'h0; + fregfile_20_exponent <= 8'h0; + fregfile_20_sign <= 1'h0; + fregfile_21_mantissa <= 23'h0; + fregfile_21_exponent <= 8'h0; + fregfile_21_sign <= 1'h0; + fregfile_22_mantissa <= 23'h0; + fregfile_22_exponent <= 8'h0; + fregfile_22_sign <= 1'h0; + fregfile_23_mantissa <= 23'h0; + fregfile_23_exponent <= 8'h0; + fregfile_23_sign <= 1'h0; + fregfile_24_mantissa <= 23'h0; + fregfile_24_exponent <= 8'h0; + fregfile_24_sign <= 1'h0; + fregfile_25_mantissa <= 23'h0; + fregfile_25_exponent <= 8'h0; + fregfile_25_sign <= 1'h0; + fregfile_26_mantissa <= 23'h0; + fregfile_26_exponent <= 8'h0; + fregfile_26_sign <= 1'h0; + fregfile_27_mantissa <= 23'h0; + fregfile_27_exponent <= 8'h0; + fregfile_27_sign <= 1'h0; + fregfile_28_mantissa <= 23'h0; + fregfile_28_exponent <= 8'h0; + fregfile_28_sign <= 1'h0; + fregfile_29_mantissa <= 23'h0; + fregfile_29_exponent <= 8'h0; + fregfile_29_sign <= 1'h0; + fregfile_30_mantissa <= 23'h0; + fregfile_30_exponent <= 8'h0; + fregfile_30_sign <= 1'h0; + fregfile_31_mantissa <= 23'h0; + fregfile_31_exponent <= 8'h0; + fregfile_31_sign <= 1'h0; + scoreboard <= 32'h0; + scoreboard_error <= 1'h0; + end + else begin + if (valid_0 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h0) begin + fregfile_0_mantissa <= + valid_0 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_0_exponent <= + valid_0 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_0_sign <= + valid_0 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_1 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1) begin + fregfile_1_mantissa <= + valid_0_1 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_1_exponent <= + valid_0_1 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_1_sign <= + valid_0_1 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_2 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h2) begin + fregfile_2_mantissa <= + valid_0_2 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_2_exponent <= + valid_0_2 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_2_sign <= + valid_0_2 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_3 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h3) begin + fregfile_3_mantissa <= + valid_0_3 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_3_exponent <= + valid_0_3 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_3_sign <= + valid_0_3 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_4 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h4) begin + fregfile_4_mantissa <= + valid_0_4 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_4_exponent <= + valid_0_4 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_4_sign <= + valid_0_4 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_5 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h5) begin + fregfile_5_mantissa <= + valid_0_5 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_5_exponent <= + valid_0_5 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_5_sign <= + valid_0_5 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_6 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h6) begin + fregfile_6_mantissa <= + valid_0_6 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_6_exponent <= + valid_0_6 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_6_sign <= + valid_0_6 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_7 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h7) begin + fregfile_7_mantissa <= + valid_0_7 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_7_exponent <= + valid_0_7 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_7_sign <= + valid_0_7 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_8 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h8) begin + fregfile_8_mantissa <= + valid_0_8 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_8_exponent <= + valid_0_8 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_8_sign <= + valid_0_8 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_9 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h9) begin + fregfile_9_mantissa <= + valid_0_9 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_9_exponent <= + valid_0_9 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_9_sign <= + valid_0_9 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_10 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hA) begin + fregfile_10_mantissa <= + valid_0_10 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_10_exponent <= + valid_0_10 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_10_sign <= + valid_0_10 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_11 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hB) begin + fregfile_11_mantissa <= + valid_0_11 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_11_exponent <= + valid_0_11 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_11_sign <= + valid_0_11 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_12 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hC) begin + fregfile_12_mantissa <= + valid_0_12 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_12_exponent <= + valid_0_12 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_12_sign <= + valid_0_12 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_13 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hD) begin + fregfile_13_mantissa <= + valid_0_13 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_13_exponent <= + valid_0_13 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_13_sign <= + valid_0_13 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_14 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hE) begin + fregfile_14_mantissa <= + valid_0_14 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_14_exponent <= + valid_0_14 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_14_sign <= + valid_0_14 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_15 | io_write_ports_1_valid & io_write_ports_1_addr == 5'hF) begin + fregfile_15_mantissa <= + valid_0_15 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_15_exponent <= + valid_0_15 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_15_sign <= + valid_0_15 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_16 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h10) begin + fregfile_16_mantissa <= + valid_0_16 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_16_exponent <= + valid_0_16 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_16_sign <= + valid_0_16 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_17 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h11) begin + fregfile_17_mantissa <= + valid_0_17 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_17_exponent <= + valid_0_17 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_17_sign <= + valid_0_17 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_18 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h12) begin + fregfile_18_mantissa <= + valid_0_18 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_18_exponent <= + valid_0_18 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_18_sign <= + valid_0_18 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_19 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h13) begin + fregfile_19_mantissa <= + valid_0_19 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_19_exponent <= + valid_0_19 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_19_sign <= + valid_0_19 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_20 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h14) begin + fregfile_20_mantissa <= + valid_0_20 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_20_exponent <= + valid_0_20 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_20_sign <= + valid_0_20 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_21 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h15) begin + fregfile_21_mantissa <= + valid_0_21 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_21_exponent <= + valid_0_21 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_21_sign <= + valid_0_21 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_22 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h16) begin + fregfile_22_mantissa <= + valid_0_22 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_22_exponent <= + valid_0_22 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_22_sign <= + valid_0_22 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_23 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h17) begin + fregfile_23_mantissa <= + valid_0_23 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_23_exponent <= + valid_0_23 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_23_sign <= + valid_0_23 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_24 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h18) begin + fregfile_24_mantissa <= + valid_0_24 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_24_exponent <= + valid_0_24 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_24_sign <= + valid_0_24 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_25 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h19) begin + fregfile_25_mantissa <= + valid_0_25 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_25_exponent <= + valid_0_25 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_25_sign <= + valid_0_25 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_26 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1A) begin + fregfile_26_mantissa <= + valid_0_26 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_26_exponent <= + valid_0_26 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_26_sign <= + valid_0_26 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_27 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1B) begin + fregfile_27_mantissa <= + valid_0_27 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_27_exponent <= + valid_0_27 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_27_sign <= + valid_0_27 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_28 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1C) begin + fregfile_28_mantissa <= + valid_0_28 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_28_exponent <= + valid_0_28 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_28_sign <= + valid_0_28 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_29 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1D) begin + fregfile_29_mantissa <= + valid_0_29 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_29_exponent <= + valid_0_29 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_29_sign <= + valid_0_29 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_30 | io_write_ports_1_valid & io_write_ports_1_addr == 5'h1E) begin + fregfile_30_mantissa <= + valid_0_30 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_30_exponent <= + valid_0_30 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_30_sign <= + valid_0_30 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + if (valid_0_31 | io_write_ports_1_valid & (&io_write_ports_1_addr)) begin + fregfile_31_mantissa <= + valid_0_31 ? io_write_ports_0_data_mantissa : io_write_ports_1_data_mantissa; + fregfile_31_exponent <= + valid_0_31 ? io_write_ports_0_data_exponent : io_write_ports_1_data_exponent; + fregfile_31_sign <= + valid_0_31 ? io_write_ports_0_data_sign : io_write_ports_1_data_sign; + end + scoreboard <= scoreboard & ~scoreboard_clr | io_scoreboard_set; + scoreboard_error <= (scoreboard & scoreboard_clr) != scoreboard_clr; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:33]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [5:0] i = 6'h0; i < 6'h22; i += 6'h1) begin + _RANDOM[i] = `RANDOM; + end + fregfile_0_mantissa = _RANDOM[6'h0][22:0]; + fregfile_0_exponent = _RANDOM[6'h0][30:23]; + fregfile_0_sign = _RANDOM[6'h0][31]; + fregfile_1_mantissa = _RANDOM[6'h1][22:0]; + fregfile_1_exponent = _RANDOM[6'h1][30:23]; + fregfile_1_sign = _RANDOM[6'h1][31]; + fregfile_2_mantissa = _RANDOM[6'h2][22:0]; + fregfile_2_exponent = _RANDOM[6'h2][30:23]; + fregfile_2_sign = _RANDOM[6'h2][31]; + fregfile_3_mantissa = _RANDOM[6'h3][22:0]; + fregfile_3_exponent = _RANDOM[6'h3][30:23]; + fregfile_3_sign = _RANDOM[6'h3][31]; + fregfile_4_mantissa = _RANDOM[6'h4][22:0]; + fregfile_4_exponent = _RANDOM[6'h4][30:23]; + fregfile_4_sign = _RANDOM[6'h4][31]; + fregfile_5_mantissa = _RANDOM[6'h5][22:0]; + fregfile_5_exponent = _RANDOM[6'h5][30:23]; + fregfile_5_sign = _RANDOM[6'h5][31]; + fregfile_6_mantissa = _RANDOM[6'h6][22:0]; + fregfile_6_exponent = _RANDOM[6'h6][30:23]; + fregfile_6_sign = _RANDOM[6'h6][31]; + fregfile_7_mantissa = _RANDOM[6'h7][22:0]; + fregfile_7_exponent = _RANDOM[6'h7][30:23]; + fregfile_7_sign = _RANDOM[6'h7][31]; + fregfile_8_mantissa = _RANDOM[6'h8][22:0]; + fregfile_8_exponent = _RANDOM[6'h8][30:23]; + fregfile_8_sign = _RANDOM[6'h8][31]; + fregfile_9_mantissa = _RANDOM[6'h9][22:0]; + fregfile_9_exponent = _RANDOM[6'h9][30:23]; + fregfile_9_sign = _RANDOM[6'h9][31]; + fregfile_10_mantissa = _RANDOM[6'hA][22:0]; + fregfile_10_exponent = _RANDOM[6'hA][30:23]; + fregfile_10_sign = _RANDOM[6'hA][31]; + fregfile_11_mantissa = _RANDOM[6'hB][22:0]; + fregfile_11_exponent = _RANDOM[6'hB][30:23]; + fregfile_11_sign = _RANDOM[6'hB][31]; + fregfile_12_mantissa = _RANDOM[6'hC][22:0]; + fregfile_12_exponent = _RANDOM[6'hC][30:23]; + fregfile_12_sign = _RANDOM[6'hC][31]; + fregfile_13_mantissa = _RANDOM[6'hD][22:0]; + fregfile_13_exponent = _RANDOM[6'hD][30:23]; + fregfile_13_sign = _RANDOM[6'hD][31]; + fregfile_14_mantissa = _RANDOM[6'hE][22:0]; + fregfile_14_exponent = _RANDOM[6'hE][30:23]; + fregfile_14_sign = _RANDOM[6'hE][31]; + fregfile_15_mantissa = _RANDOM[6'hF][22:0]; + fregfile_15_exponent = _RANDOM[6'hF][30:23]; + fregfile_15_sign = _RANDOM[6'hF][31]; + fregfile_16_mantissa = _RANDOM[6'h10][22:0]; + fregfile_16_exponent = _RANDOM[6'h10][30:23]; + fregfile_16_sign = _RANDOM[6'h10][31]; + fregfile_17_mantissa = _RANDOM[6'h11][22:0]; + fregfile_17_exponent = _RANDOM[6'h11][30:23]; + fregfile_17_sign = _RANDOM[6'h11][31]; + fregfile_18_mantissa = _RANDOM[6'h12][22:0]; + fregfile_18_exponent = _RANDOM[6'h12][30:23]; + fregfile_18_sign = _RANDOM[6'h12][31]; + fregfile_19_mantissa = _RANDOM[6'h13][22:0]; + fregfile_19_exponent = _RANDOM[6'h13][30:23]; + fregfile_19_sign = _RANDOM[6'h13][31]; + fregfile_20_mantissa = _RANDOM[6'h14][22:0]; + fregfile_20_exponent = _RANDOM[6'h14][30:23]; + fregfile_20_sign = _RANDOM[6'h14][31]; + fregfile_21_mantissa = _RANDOM[6'h15][22:0]; + fregfile_21_exponent = _RANDOM[6'h15][30:23]; + fregfile_21_sign = _RANDOM[6'h15][31]; + fregfile_22_mantissa = _RANDOM[6'h16][22:0]; + fregfile_22_exponent = _RANDOM[6'h16][30:23]; + fregfile_22_sign = _RANDOM[6'h16][31]; + fregfile_23_mantissa = _RANDOM[6'h17][22:0]; + fregfile_23_exponent = _RANDOM[6'h17][30:23]; + fregfile_23_sign = _RANDOM[6'h17][31]; + fregfile_24_mantissa = _RANDOM[6'h18][22:0]; + fregfile_24_exponent = _RANDOM[6'h18][30:23]; + fregfile_24_sign = _RANDOM[6'h18][31]; + fregfile_25_mantissa = _RANDOM[6'h19][22:0]; + fregfile_25_exponent = _RANDOM[6'h19][30:23]; + fregfile_25_sign = _RANDOM[6'h19][31]; + fregfile_26_mantissa = _RANDOM[6'h1A][22:0]; + fregfile_26_exponent = _RANDOM[6'h1A][30:23]; + fregfile_26_sign = _RANDOM[6'h1A][31]; + fregfile_27_mantissa = _RANDOM[6'h1B][22:0]; + fregfile_27_exponent = _RANDOM[6'h1B][30:23]; + fregfile_27_sign = _RANDOM[6'h1B][31]; + fregfile_28_mantissa = _RANDOM[6'h1C][22:0]; + fregfile_28_exponent = _RANDOM[6'h1C][30:23]; + fregfile_28_sign = _RANDOM[6'h1C][31]; + fregfile_29_mantissa = _RANDOM[6'h1D][22:0]; + fregfile_29_exponent = _RANDOM[6'h1D][30:23]; + fregfile_29_sign = _RANDOM[6'h1D][31]; + fregfile_30_mantissa = _RANDOM[6'h1E][22:0]; + fregfile_30_exponent = _RANDOM[6'h1E][30:23]; + fregfile_30_sign = _RANDOM[6'h1E][31]; + fregfile_31_mantissa = _RANDOM[6'h1F][22:0]; + fregfile_31_exponent = _RANDOM[6'h1F][30:23]; + fregfile_31_sign = _RANDOM[6'h1F][31]; + scoreboard = _RANDOM[6'h20]; + scoreboard_error = _RANDOM[6'h21][0]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + fregfile_0_mantissa = 23'h0; + fregfile_0_exponent = 8'h0; + fregfile_0_sign = 1'h0; + fregfile_1_mantissa = 23'h0; + fregfile_1_exponent = 8'h0; + fregfile_1_sign = 1'h0; + fregfile_2_mantissa = 23'h0; + fregfile_2_exponent = 8'h0; + fregfile_2_sign = 1'h0; + fregfile_3_mantissa = 23'h0; + fregfile_3_exponent = 8'h0; + fregfile_3_sign = 1'h0; + fregfile_4_mantissa = 23'h0; + fregfile_4_exponent = 8'h0; + fregfile_4_sign = 1'h0; + fregfile_5_mantissa = 23'h0; + fregfile_5_exponent = 8'h0; + fregfile_5_sign = 1'h0; + fregfile_6_mantissa = 23'h0; + fregfile_6_exponent = 8'h0; + fregfile_6_sign = 1'h0; + fregfile_7_mantissa = 23'h0; + fregfile_7_exponent = 8'h0; + fregfile_7_sign = 1'h0; + fregfile_8_mantissa = 23'h0; + fregfile_8_exponent = 8'h0; + fregfile_8_sign = 1'h0; + fregfile_9_mantissa = 23'h0; + fregfile_9_exponent = 8'h0; + fregfile_9_sign = 1'h0; + fregfile_10_mantissa = 23'h0; + fregfile_10_exponent = 8'h0; + fregfile_10_sign = 1'h0; + fregfile_11_mantissa = 23'h0; + fregfile_11_exponent = 8'h0; + fregfile_11_sign = 1'h0; + fregfile_12_mantissa = 23'h0; + fregfile_12_exponent = 8'h0; + fregfile_12_sign = 1'h0; + fregfile_13_mantissa = 23'h0; + fregfile_13_exponent = 8'h0; + fregfile_13_sign = 1'h0; + fregfile_14_mantissa = 23'h0; + fregfile_14_exponent = 8'h0; + fregfile_14_sign = 1'h0; + fregfile_15_mantissa = 23'h0; + fregfile_15_exponent = 8'h0; + fregfile_15_sign = 1'h0; + fregfile_16_mantissa = 23'h0; + fregfile_16_exponent = 8'h0; + fregfile_16_sign = 1'h0; + fregfile_17_mantissa = 23'h0; + fregfile_17_exponent = 8'h0; + fregfile_17_sign = 1'h0; + fregfile_18_mantissa = 23'h0; + fregfile_18_exponent = 8'h0; + fregfile_18_sign = 1'h0; + fregfile_19_mantissa = 23'h0; + fregfile_19_exponent = 8'h0; + fregfile_19_sign = 1'h0; + fregfile_20_mantissa = 23'h0; + fregfile_20_exponent = 8'h0; + fregfile_20_sign = 1'h0; + fregfile_21_mantissa = 23'h0; + fregfile_21_exponent = 8'h0; + fregfile_21_sign = 1'h0; + fregfile_22_mantissa = 23'h0; + fregfile_22_exponent = 8'h0; + fregfile_22_sign = 1'h0; + fregfile_23_mantissa = 23'h0; + fregfile_23_exponent = 8'h0; + fregfile_23_sign = 1'h0; + fregfile_24_mantissa = 23'h0; + fregfile_24_exponent = 8'h0; + fregfile_24_sign = 1'h0; + fregfile_25_mantissa = 23'h0; + fregfile_25_exponent = 8'h0; + fregfile_25_sign = 1'h0; + fregfile_26_mantissa = 23'h0; + fregfile_26_exponent = 8'h0; + fregfile_26_sign = 1'h0; + fregfile_27_mantissa = 23'h0; + fregfile_27_exponent = 8'h0; + fregfile_27_sign = 1'h0; + fregfile_28_mantissa = 23'h0; + fregfile_28_exponent = 8'h0; + fregfile_28_sign = 1'h0; + fregfile_29_mantissa = 23'h0; + fregfile_29_exponent = 8'h0; + fregfile_29_sign = 1'h0; + fregfile_30_mantissa = 23'h0; + fregfile_30_exponent = 8'h0; + fregfile_30_sign = 1'h0; + fregfile_31_mantissa = 23'h0; + fregfile_31_exponent = 8'h0; + fregfile_31_sign = 1'h0; + scoreboard = 32'h0; + scoreboard_error = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_read_ports_0_data_mantissa = + io_read_ports_0_valid ? _GEN[io_read_ports_0_addr] : 23'h0; + assign io_read_ports_0_data_exponent = + io_read_ports_0_valid ? _GEN_0[io_read_ports_0_addr] : 8'h0; + assign io_read_ports_0_data_sign = io_read_ports_0_valid & _GEN_1[io_read_ports_0_addr]; + assign io_read_ports_1_data_mantissa = + io_read_ports_1_valid ? _GEN[io_read_ports_1_addr] : 23'h0; + assign io_read_ports_1_data_exponent = + io_read_ports_1_valid ? _GEN_0[io_read_ports_1_addr] : 8'h0; + assign io_read_ports_1_data_sign = io_read_ports_1_valid & _GEN_1[io_read_ports_1_addr]; + assign io_read_ports_2_data_mantissa = + io_read_ports_2_valid ? _GEN[io_read_ports_2_addr] : 23'h0; + assign io_read_ports_2_data_exponent = + io_read_ports_2_valid ? _GEN_0[io_read_ports_2_addr] : 8'h0; + assign io_read_ports_2_data_sign = io_read_ports_2_valid & _GEN_1[io_read_ports_2_addr]; + assign io_scoreboard = scoreboard; + assign io_busPort_data_0 = + {_io_busPort_data_0_T_1 ? io_write_ports_0_data_sign : _GEN_1[io_busPortAddr], + _io_busPort_data_0_T_1 ? io_write_ports_0_data_exponent : _GEN_0[io_busPortAddr], + _io_busPort_data_0_T_1 ? io_write_ports_0_data_mantissa : _GEN[io_busPortAddr]}; +endmodule + +module Arbiter3_RegfileWriteDataIO( + input io_in_0_valid, + input [4:0] io_in_0_bits_addr, + input [31:0] io_in_0_bits_data, + output io_in_1_ready, + input io_in_1_valid, + input [4:0] io_in_1_bits_addr, + input [31:0] io_in_1_bits_data, + output io_in_2_ready, + input io_in_2_valid, + input [4:0] io_in_2_bits_addr, + input [31:0] io_in_2_bits_data, + output io_out_valid, + output [4:0] io_out_bits_addr, + output [31:0] io_out_bits_data +); + + wire _io_out_valid_T = io_in_0_valid | io_in_1_valid; + assign io_in_1_ready = ~io_in_0_valid; + assign io_in_2_ready = ~_io_out_valid_T; + assign io_out_valid = _io_out_valid_T | io_in_2_valid; + assign io_out_bits_addr = + io_in_0_valid + ? io_in_0_bits_addr + : io_in_1_valid ? io_in_1_bits_addr : io_in_2_bits_addr; + assign io_out_bits_data = + io_in_0_valid + ? io_in_0_bits_data + : io_in_1_valid ? io_in_1_bits_data : io_in_2_bits_data; +endmodule + +module SCore( + input clock, + reset, + input [31:0] io_csr_in_value_0, + output [31:0] io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + output io_halted, + io_fault, + io_wfi, + input io_irq, + output io_ibus_valid, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + input io_ibus_fault_valid, + input [31:0] io_ibus_fault_bits_epc, + output io_dbus_valid, + io_dbus_write, + output [31:0] io_dbus_addr, + output [127:0] io_dbus_wdata, + output [15:0] io_dbus_wmask, + input [127:0] io_dbus_rdata, + output io_ebus_dbus_valid, + input io_ebus_dbus_ready, + output io_ebus_dbus_write, + output [31:0] io_ebus_dbus_pc, + io_ebus_dbus_addr, + output [4:0] io_ebus_dbus_size, + output [127:0] io_ebus_dbus_wdata, + input [127:0] io_ebus_dbus_rdata, + input io_ebus_fault_valid, + io_ebus_fault_bits_write, + input [31:0] io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, + output io_slog_valid, + output [4:0] io_slog_addr, + output [31:0] io_slog_data, + output [3:0] io_debug_en, + output [31:0] io_debug_addr_0, + io_debug_addr_1, + io_debug_addr_2, + io_debug_addr_3, + io_debug_inst_0, + io_debug_inst_1, + io_debug_inst_2, + io_debug_inst_3, + io_debug_cycles, + output io_debug_dbus_valid, + output [31:0] io_debug_dbus_bits_addr, + output [127:0] io_debug_dbus_bits_wdata, + output io_debug_dbus_bits_write, + io_debug_dispatch_0_instFire, + output [31:0] io_debug_dispatch_0_instAddr, + io_debug_dispatch_0_instInst, + output io_debug_dispatch_1_instFire, + output [31:0] io_debug_dispatch_1_instAddr, + io_debug_dispatch_1_instInst, + output io_debug_dispatch_2_instFire, + output [31:0] io_debug_dispatch_2_instAddr, + io_debug_dispatch_2_instInst, + output io_debug_dispatch_3_instFire, + output [31:0] io_debug_dispatch_3_instAddr, + io_debug_dispatch_3_instInst, + output io_debug_regfile_writeAddr_0_valid, + output [4:0] io_debug_regfile_writeAddr_0_bits, + output io_debug_regfile_writeAddr_1_valid, + output [4:0] io_debug_regfile_writeAddr_1_bits, + output io_debug_regfile_writeAddr_2_valid, + output [4:0] io_debug_regfile_writeAddr_2_bits, + output io_debug_regfile_writeAddr_3_valid, + output [4:0] io_debug_regfile_writeAddr_3_bits, + output io_debug_regfile_writeData_0_valid, + output [4:0] io_debug_regfile_writeData_0_bits_addr, + output [31:0] io_debug_regfile_writeData_0_bits_data, + output io_debug_regfile_writeData_1_valid, + output [4:0] io_debug_regfile_writeData_1_bits_addr, + output [31:0] io_debug_regfile_writeData_1_bits_data, + output io_debug_regfile_writeData_2_valid, + output [4:0] io_debug_regfile_writeData_2_bits_addr, + output [31:0] io_debug_regfile_writeData_2_bits_data, + output io_debug_regfile_writeData_3_valid, + output [4:0] io_debug_regfile_writeData_3_bits_addr, + output [31:0] io_debug_regfile_writeData_3_bits_data, + output io_debug_regfile_writeData_4_valid, + output [4:0] io_debug_regfile_writeData_4_bits_addr, + output [31:0] io_debug_regfile_writeData_4_bits_data, + output io_debug_regfile_writeData_5_valid, + output [4:0] io_debug_regfile_writeData_5_bits_addr, + output [31:0] io_debug_regfile_writeData_5_bits_data, + output io_debug_float_writeAddr_valid, + output [4:0] io_debug_float_writeAddr_bits, + output io_debug_float_writeData_0_valid, + output [31:0] io_debug_float_writeData_0_bits_addr, + io_debug_float_writeData_0_bits_data, + output io_debug_float_writeData_1_valid, + output [31:0] io_debug_float_writeData_1_bits_addr, + io_debug_float_writeData_1_bits_data +); + + wire _arb_io_in_1_ready; + wire _arb_io_in_2_ready; + wire _arb_io_out_valid; + wire [4:0] _arb_io_out_bits_addr; + wire [31:0] _arb_io_out_bits_data; + wire [22:0] _fRegfile_io_read_ports_0_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_0_data_exponent; + wire _fRegfile_io_read_ports_0_data_sign; + wire [22:0] _fRegfile_io_read_ports_1_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_1_data_exponent; + wire _fRegfile_io_read_ports_1_data_sign; + wire [22:0] _fRegfile_io_read_ports_2_data_mantissa; + wire [7:0] _fRegfile_io_read_ports_2_data_exponent; + wire _fRegfile_io_read_ports_2_data_sign; + wire [31:0] _fRegfile_io_scoreboard; + wire [31:0] _fRegfile_io_busPort_data_0; + wire _floatCore_io_inst_ready; + wire _floatCore_io_read_ports_0_valid; + wire [4:0] _floatCore_io_read_ports_0_addr; + wire _floatCore_io_read_ports_1_valid; + wire [4:0] _floatCore_io_read_ports_1_addr; + wire _floatCore_io_read_ports_2_valid; + wire [4:0] _floatCore_io_read_ports_2_addr; + wire _floatCore_io_write_ports_0_valid; + wire [4:0] _floatCore_io_write_ports_0_addr; + wire [22:0] _floatCore_io_write_ports_0_data_mantissa; + wire [7:0] _floatCore_io_write_ports_0_data_exponent; + wire _floatCore_io_write_ports_0_data_sign; + wire _floatCore_io_write_ports_1_valid; + wire [4:0] _floatCore_io_write_ports_1_addr; + wire [22:0] _floatCore_io_write_ports_1_data_mantissa; + wire [7:0] _floatCore_io_write_ports_1_data_exponent; + wire _floatCore_io_write_ports_1_data_sign; + wire _floatCore_io_scalar_rd_valid; + wire [4:0] _floatCore_io_scalar_rd_bits_addr; + wire [31:0] _floatCore_io_scalar_rd_bits_data; + wire _floatCore_io_csr_in_fflags_valid; + wire [4:0] _floatCore_io_csr_in_fflags_bits; + wire _fault_manager_io_out_valid; + wire [31:0] _fault_manager_io_out_bits_mepc; + wire [31:0] _fault_manager_io_out_bits_mtval; + wire [31:0] _fault_manager_io_out_bits_mcause; + wire _dvu_io_req_ready; + wire _dvu_io_rd_valid; + wire [4:0] _dvu_io_rd_bits_addr; + wire [31:0] _dvu_io_rd_bits_data; + wire _mlu_io_rd_valid; + wire [4:0] _mlu_io_rd_bits_addr; + wire [31:0] _mlu_io_rd_bits_data; + wire _lsu_io_req_0_ready; + wire _lsu_io_req_1_ready; + wire _lsu_io_req_2_ready; + wire _lsu_io_req_3_ready; + wire _lsu_io_rd_valid; + wire [4:0] _lsu_io_rd_bits_addr; + wire [31:0] _lsu_io_rd_bits_data; + wire _lsu_io_rd_flt_valid; + wire [4:0] _lsu_io_rd_flt_bits_addr; + wire [31:0] _lsu_io_rd_flt_bits_data; + wire _lsu_io_ibus_valid; + wire [31:0] _lsu_io_ibus_addr; + wire _lsu_io_dbus_valid; + wire _lsu_io_dbus_write; + wire [31:0] _lsu_io_dbus_addr; + wire [127:0] _lsu_io_dbus_wdata; + wire _lsu_io_flush_valid; + wire _lsu_io_flush_fencei; + wire [31:0] _lsu_io_flush_pcNext; + wire _lsu_io_fault_valid; + wire _lsu_io_fault_bits_write; + wire [31:0] _lsu_io_fault_bits_addr; + wire [31:0] _lsu_io_fault_bits_epc; + wire [1:0] _lsu_io_storeCount; + wire _lsu_io_active; + wire _bru_3_io_rd_valid; + wire [4:0] _bru_3_io_rd_bits_addr; + wire [31:0] _bru_3_io_rd_bits_data; + wire _bru_3_io_taken_valid; + wire [31:0] _bru_3_io_taken_value; + wire _bru_2_io_rd_valid; + wire [4:0] _bru_2_io_rd_bits_addr; + wire [31:0] _bru_2_io_rd_bits_data; + wire _bru_2_io_taken_valid; + wire [31:0] _bru_2_io_taken_value; + wire _bru_1_io_rd_valid; + wire [4:0] _bru_1_io_rd_bits_addr; + wire [31:0] _bru_1_io_rd_bits_data; + wire _bru_1_io_taken_valid; + wire [31:0] _bru_1_io_taken_value; + wire _bru_0_io_csr_in_mode_valid; + wire [1:0] _bru_0_io_csr_in_mode_bits; + wire _bru_0_io_csr_in_mcause_valid; + wire [31:0] _bru_0_io_csr_in_mcause_bits; + wire _bru_0_io_csr_in_mepc_valid; + wire [31:0] _bru_0_io_csr_in_mepc_bits; + wire _bru_0_io_csr_in_mtval_valid; + wire [31:0] _bru_0_io_csr_in_mtval_bits; + wire _bru_0_io_csr_in_halt; + wire _bru_0_io_csr_in_fault; + wire _bru_0_io_csr_in_wfi; + wire _bru_0_io_rd_valid; + wire [4:0] _bru_0_io_rd_bits_addr; + wire [31:0] _bru_0_io_rd_bits_data; + wire _bru_0_io_taken_valid; + wire [31:0] _bru_0_io_taken_value; + wire _bru_0_io_interlock; + wire _alu_3_io_rd_valid; + wire [4:0] _alu_3_io_rd_bits_addr; + wire [31:0] _alu_3_io_rd_bits_data; + wire _alu_2_io_rd_valid; + wire [4:0] _alu_2_io_rd_bits_addr; + wire [31:0] _alu_2_io_rd_bits_data; + wire _alu_1_io_rd_valid; + wire [4:0] _alu_1_io_rd_bits_addr; + wire [31:0] _alu_1_io_rd_bits_data; + wire _alu_0_io_rd_valid; + wire [4:0] _alu_0_io_rd_bits_addr; + wire [31:0] _alu_0_io_rd_bits_data; + wire _dispatch_io_csrFault_0; + wire _dispatch_io_jalFault_0; + wire _dispatch_io_jalFault_1; + wire _dispatch_io_jalFault_2; + wire _dispatch_io_jalFault_3; + wire _dispatch_io_jalrFault_0; + wire _dispatch_io_jalrFault_1; + wire _dispatch_io_jalrFault_2; + wire _dispatch_io_jalrFault_3; + wire _dispatch_io_bxxFault_0; + wire _dispatch_io_bxxFault_1; + wire _dispatch_io_bxxFault_2; + wire _dispatch_io_bxxFault_3; + wire _dispatch_io_undefFault_0; + wire [31:0] _dispatch_io_bruTarget_0; + wire [31:0] _dispatch_io_bruTarget_1; + wire [31:0] _dispatch_io_bruTarget_2; + wire [31:0] _dispatch_io_bruTarget_3; + wire _dispatch_io_inst_0_ready; + wire _dispatch_io_inst_1_ready; + wire _dispatch_io_inst_2_ready; + wire _dispatch_io_inst_3_ready; + wire _dispatch_io_rs1Read_0_valid; + wire [4:0] _dispatch_io_rs1Read_0_addr; + wire _dispatch_io_rs1Read_1_valid; + wire [4:0] _dispatch_io_rs1Read_1_addr; + wire _dispatch_io_rs1Read_2_valid; + wire [4:0] _dispatch_io_rs1Read_2_addr; + wire _dispatch_io_rs1Read_3_valid; + wire [4:0] _dispatch_io_rs1Read_3_addr; + wire _dispatch_io_rs1Set_0_valid; + wire [31:0] _dispatch_io_rs1Set_0_value; + wire _dispatch_io_rs1Set_1_valid; + wire [31:0] _dispatch_io_rs1Set_1_value; + wire _dispatch_io_rs1Set_2_valid; + wire [31:0] _dispatch_io_rs1Set_2_value; + wire _dispatch_io_rs1Set_3_valid; + wire [31:0] _dispatch_io_rs1Set_3_value; + wire _dispatch_io_rs2Read_0_valid; + wire [4:0] _dispatch_io_rs2Read_0_addr; + wire _dispatch_io_rs2Read_1_valid; + wire [4:0] _dispatch_io_rs2Read_1_addr; + wire _dispatch_io_rs2Read_2_valid; + wire [4:0] _dispatch_io_rs2Read_2_addr; + wire _dispatch_io_rs2Read_3_valid; + wire [4:0] _dispatch_io_rs2Read_3_addr; + wire _dispatch_io_rs2Set_0_valid; + wire [31:0] _dispatch_io_rs2Set_0_value; + wire _dispatch_io_rs2Set_1_valid; + wire [31:0] _dispatch_io_rs2Set_1_value; + wire _dispatch_io_rs2Set_2_valid; + wire [31:0] _dispatch_io_rs2Set_2_value; + wire _dispatch_io_rs2Set_3_valid; + wire [31:0] _dispatch_io_rs2Set_3_value; + wire _dispatch_io_rdMark_0_valid; + wire [4:0] _dispatch_io_rdMark_0_addr; + wire _dispatch_io_rdMark_1_valid; + wire [4:0] _dispatch_io_rdMark_1_addr; + wire _dispatch_io_rdMark_2_valid; + wire [4:0] _dispatch_io_rdMark_2_addr; + wire _dispatch_io_rdMark_3_valid; + wire [4:0] _dispatch_io_rdMark_3_addr; + wire _dispatch_io_busRead_0_bypass; + wire _dispatch_io_busRead_0_immen; + wire [31:0] _dispatch_io_busRead_0_immed; + wire _dispatch_io_busRead_1_bypass; + wire [31:0] _dispatch_io_busRead_1_immed; + wire _dispatch_io_busRead_2_bypass; + wire [31:0] _dispatch_io_busRead_2_immed; + wire _dispatch_io_busRead_3_bypass; + wire [31:0] _dispatch_io_busRead_3_immed; + wire _dispatch_io_rdMark_flt_valid; + wire [4:0] _dispatch_io_rdMark_flt_addr; + wire _dispatch_io_alu_0_valid; + wire [4:0] _dispatch_io_alu_0_bits_addr; + wire [4:0] _dispatch_io_alu_0_bits_op; + wire _dispatch_io_alu_1_valid; + wire [4:0] _dispatch_io_alu_1_bits_addr; + wire [4:0] _dispatch_io_alu_1_bits_op; + wire _dispatch_io_alu_2_valid; + wire [4:0] _dispatch_io_alu_2_bits_addr; + wire [4:0] _dispatch_io_alu_2_bits_op; + wire _dispatch_io_alu_3_valid; + wire [4:0] _dispatch_io_alu_3_bits_addr; + wire [4:0] _dispatch_io_alu_3_bits_op; + wire _dispatch_io_bru_0_valid; + wire _dispatch_io_bru_0_bits_fwd; + wire [3:0] _dispatch_io_bru_0_bits_op; + wire [31:0] _dispatch_io_bru_0_bits_pc; + wire [31:0] _dispatch_io_bru_0_bits_target; + wire [4:0] _dispatch_io_bru_0_bits_link; + wire _dispatch_io_bru_1_valid; + wire _dispatch_io_bru_1_bits_fwd; + wire [3:0] _dispatch_io_bru_1_bits_op; + wire [31:0] _dispatch_io_bru_1_bits_pc; + wire [31:0] _dispatch_io_bru_1_bits_target; + wire [4:0] _dispatch_io_bru_1_bits_link; + wire _dispatch_io_bru_2_valid; + wire _dispatch_io_bru_2_bits_fwd; + wire [3:0] _dispatch_io_bru_2_bits_op; + wire [31:0] _dispatch_io_bru_2_bits_pc; + wire [31:0] _dispatch_io_bru_2_bits_target; + wire [4:0] _dispatch_io_bru_2_bits_link; + wire _dispatch_io_bru_3_valid; + wire _dispatch_io_bru_3_bits_fwd; + wire [3:0] _dispatch_io_bru_3_bits_op; + wire [31:0] _dispatch_io_bru_3_bits_pc; + wire [31:0] _dispatch_io_bru_3_bits_target; + wire [4:0] _dispatch_io_bru_3_bits_link; + wire _dispatch_io_csr_valid; + wire [4:0] _dispatch_io_csr_bits_addr; + wire [11:0] _dispatch_io_csr_bits_index; + wire [1:0] _dispatch_io_csr_bits_op; + wire _dispatch_io_lsu_0_valid; + wire _dispatch_io_lsu_0_bits_store; + wire [4:0] _dispatch_io_lsu_0_bits_addr; + wire [4:0] _dispatch_io_lsu_0_bits_op; + wire [31:0] _dispatch_io_lsu_0_bits_pc; + wire _dispatch_io_lsu_1_valid; + wire _dispatch_io_lsu_1_bits_store; + wire [4:0] _dispatch_io_lsu_1_bits_addr; + wire [4:0] _dispatch_io_lsu_1_bits_op; + wire [31:0] _dispatch_io_lsu_1_bits_pc; + wire _dispatch_io_lsu_2_valid; + wire _dispatch_io_lsu_2_bits_store; + wire [4:0] _dispatch_io_lsu_2_bits_addr; + wire [4:0] _dispatch_io_lsu_2_bits_op; + wire [31:0] _dispatch_io_lsu_2_bits_pc; + wire _dispatch_io_lsu_3_valid; + wire _dispatch_io_lsu_3_bits_store; + wire [4:0] _dispatch_io_lsu_3_bits_addr; + wire [4:0] _dispatch_io_lsu_3_bits_op; + wire [31:0] _dispatch_io_lsu_3_bits_pc; + wire _dispatch_io_mlu_0_valid; + wire [4:0] _dispatch_io_mlu_0_bits_addr; + wire [2:0] _dispatch_io_mlu_0_bits_op; + wire _dispatch_io_mlu_1_valid; + wire [4:0] _dispatch_io_mlu_1_bits_addr; + wire [2:0] _dispatch_io_mlu_1_bits_op; + wire _dispatch_io_mlu_2_valid; + wire [4:0] _dispatch_io_mlu_2_bits_addr; + wire [2:0] _dispatch_io_mlu_2_bits_op; + wire _dispatch_io_mlu_3_valid; + wire [4:0] _dispatch_io_mlu_3_bits_addr; + wire [2:0] _dispatch_io_mlu_3_bits_op; + wire _dispatch_io_dvu_0_valid; + wire [4:0] _dispatch_io_dvu_0_bits_addr; + wire [1:0] _dispatch_io_dvu_0_bits_op; + wire _dispatch_io_float_valid; + wire [2:0] _dispatch_io_float_bits_opcode; + wire [4:0] _dispatch_io_float_bits_funct5; + wire [4:0] _dispatch_io_float_bits_rs3; + wire [4:0] _dispatch_io_float_bits_rs2; + wire [4:0] _dispatch_io_float_bits_rs1; + wire [2:0] _dispatch_io_float_bits_rm; + wire [31:0] _dispatch_io_float_bits_inst; + wire [31:0] _dispatch_io_float_bits_pc; + wire _dispatch_io_float_bits_scalar_rd; + wire _dispatch_io_float_bits_scalar_rs1; + wire [4:0] _dispatch_io_float_bits_rd; + wire _dispatch_io_float_bits_uses_rs3; + wire _dispatch_io_float_bits_uses_rs2; + wire [4:0] _dispatch_io_fbusPortAddr; + wire _dispatch_io_slog; + wire [31:0] _csr_io_csr_out_value_4; + wire _csr_io_rd_valid; + wire [4:0] _csr_io_rd_bits_addr; + wire [31:0] _csr_io_rd_bits_data; + wire [1:0] _csr_io_bru_out_mode; + wire [31:0] _csr_io_bru_out_mepc; + wire [31:0] _csr_io_bru_out_mtvec; + wire [2:0] _csr_io_float_out_frm; + wire _csr_io_halted; + wire _csr_io_wfi; + wire _fetch_io_ibus_valid; + wire [31:0] _fetch_io_ibus_addr; + wire _fetch_io_inst_lanes_0_valid; + wire [31:0] _fetch_io_inst_lanes_0_bits_addr; + wire [31:0] _fetch_io_inst_lanes_0_bits_inst; + wire _fetch_io_inst_lanes_0_bits_brchFwd; + wire _fetch_io_inst_lanes_1_valid; + wire [31:0] _fetch_io_inst_lanes_1_bits_addr; + wire [31:0] _fetch_io_inst_lanes_1_bits_inst; + wire _fetch_io_inst_lanes_1_bits_brchFwd; + wire _fetch_io_inst_lanes_2_valid; + wire [31:0] _fetch_io_inst_lanes_2_bits_addr; + wire [31:0] _fetch_io_inst_lanes_2_bits_inst; + wire _fetch_io_inst_lanes_2_bits_brchFwd; + wire _fetch_io_inst_lanes_3_valid; + wire [31:0] _fetch_io_inst_lanes_3_bits_addr; + wire [31:0] _fetch_io_inst_lanes_3_bits_inst; + wire _fetch_io_inst_lanes_3_bits_brchFwd; + wire [31:0] _fetch_io_pc; + wire [31:0] _regfile_io_target_0_data; + wire [31:0] _regfile_io_target_1_data; + wire [31:0] _regfile_io_target_2_data; + wire [31:0] _regfile_io_target_3_data; + wire [31:0] _regfile_io_busPort_addr_0; + wire [31:0] _regfile_io_busPort_addr_1; + wire [31:0] _regfile_io_busPort_addr_2; + wire [31:0] _regfile_io_busPort_addr_3; + wire [31:0] _regfile_io_busPort_data_0; + wire [31:0] _regfile_io_busPort_data_1; + wire [31:0] _regfile_io_busPort_data_2; + wire [31:0] _regfile_io_busPort_data_3; + wire _regfile_io_readData_0_valid; + wire [31:0] _regfile_io_readData_0_data; + wire _regfile_io_readData_1_valid; + wire [31:0] _regfile_io_readData_1_data; + wire _regfile_io_readData_2_valid; + wire [31:0] _regfile_io_readData_2_data; + wire _regfile_io_readData_3_valid; + wire [31:0] _regfile_io_readData_3_data; + wire _regfile_io_readData_4_valid; + wire [31:0] _regfile_io_readData_4_data; + wire _regfile_io_readData_5_valid; + wire [31:0] _regfile_io_readData_5_data; + wire _regfile_io_readData_6_valid; + wire [31:0] _regfile_io_readData_6_data; + wire _regfile_io_readData_7_valid; + wire [31:0] _regfile_io_readData_7_data; + wire [31:0] _regfile_io_scoreboard_regd; + wire [31:0] _regfile_io_scoreboard_comb; + wire [5:0] _regfile_io_rfwriteCount; + wire branchTaken = + _bru_0_io_taken_valid | _bru_1_io_taken_valid | _bru_2_io_taken_valid + | _bru_3_io_taken_valid; + wire regfile_io_writeData_0_valid = + _csr_io_rd_valid | _alu_0_io_rd_valid | _bru_0_io_rd_valid; + wire [4:0] regfile_io_writeData_0_bits_addr = + (_csr_io_rd_valid ? _csr_io_rd_bits_addr : 5'h0) + | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_addr : 5'h0) + | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_addr : 5'h0); + wire [31:0] regfile_io_writeData_0_bits_data = + (_csr_io_rd_valid ? _csr_io_rd_bits_data : 32'h0) + | (_alu_0_io_rd_valid ? _alu_0_io_rd_bits_data : 32'h0) + | (_bru_0_io_rd_valid ? _bru_0_io_rd_bits_data : 32'h0); + wire regfile_io_writeData_1_valid = _alu_1_io_rd_valid | _bru_1_io_rd_valid; + wire [4:0] regfile_io_writeData_1_bits_addr = + (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_addr : 5'h0) + | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_addr : 5'h0); + wire [31:0] regfile_io_writeData_1_bits_data = + (_alu_1_io_rd_valid ? _alu_1_io_rd_bits_data : 32'h0) + | (_bru_1_io_rd_valid ? _bru_1_io_rd_bits_data : 32'h0); + wire regfile_io_writeData_2_valid = _alu_2_io_rd_valid | _bru_2_io_rd_valid; + wire [4:0] regfile_io_writeData_2_bits_addr = + (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_addr : 5'h0) + | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_addr : 5'h0); + wire [31:0] regfile_io_writeData_2_bits_data = + (_alu_2_io_rd_valid ? _alu_2_io_rd_bits_data : 32'h0) + | (_bru_2_io_rd_valid ? _bru_2_io_rd_bits_data : 32'h0); + wire regfile_io_writeData_3_valid = _alu_3_io_rd_valid | _bru_3_io_rd_valid; + wire [4:0] regfile_io_writeData_3_bits_addr = + (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_addr : 5'h0) + | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_addr : 5'h0); + wire [31:0] regfile_io_writeData_3_bits_data = + (_alu_3_io_rd_valid ? _alu_3_io_rd_bits_data : 32'h0) + | (_bru_3_io_rd_valid ? _bru_3_io_rd_bits_data : 32'h0); + wire writeMask_2 = _bru_0_io_taken_valid | _bru_1_io_taken_valid; + reg slogValid; + reg [1:0] slogAddr; + reg [3:0] debugEn; + reg [31:0] debugAddr_0; + reg [31:0] debugAddr_1; + reg [31:0] debugAddr_2; + reg [31:0] debugAddr_3; + reg [31:0] debugInst_0; + reg [31:0] debugInst_1; + reg [31:0] debugInst_2; + reg [31:0] debugInst_3; + wire _debugBrch_T_1 = _bru_2_io_taken_valid | _bru_3_io_taken_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + slogValid <= 1'h0; + slogAddr <= 2'h0; + debugEn <= 4'h0; + debugAddr_0 <= 32'h0; + debugAddr_1 <= 32'h0; + debugAddr_2 <= 32'h0; + debugAddr_3 <= 32'h0; + debugInst_0 <= 32'h0; + debugInst_1 <= 32'h0; + debugInst_2 <= 32'h0; + debugInst_3 <= 32'h0; + end + else begin + slogValid <= _dispatch_io_slog; + if (_dispatch_io_slog) + slogAddr <= _fetch_io_inst_lanes_0_bits_inst[13:12]; + debugEn <= + {_fetch_io_inst_lanes_0_valid & _dispatch_io_inst_0_ready & ~branchTaken, + _fetch_io_inst_lanes_1_valid & _dispatch_io_inst_1_ready & ~branchTaken, + _fetch_io_inst_lanes_2_valid & _dispatch_io_inst_2_ready & ~branchTaken, + _fetch_io_inst_lanes_3_valid & _dispatch_io_inst_3_ready & ~branchTaken}; + if (debugEn[0]) begin + debugAddr_0 <= _fetch_io_inst_lanes_0_bits_addr; + debugInst_0 <= _fetch_io_inst_lanes_0_bits_inst; + end + if (debugEn[1]) begin + debugAddr_1 <= _fetch_io_inst_lanes_1_bits_addr; + debugInst_1 <= _fetch_io_inst_lanes_1_bits_inst; + end + if (debugEn[2]) begin + debugAddr_2 <= _fetch_io_inst_lanes_2_bits_addr; + debugInst_2 <= _fetch_io_inst_lanes_2_bits_inst; + end + if (debugEn[3]) begin + debugAddr_3 <= _fetch_io_inst_lanes_3_bits_addr; + debugInst_3 <= _fetch_io_inst_lanes_3_bits_inst; + end + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:8]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [3:0] i = 4'h0; i < 4'h9; i += 4'h1) begin + _RANDOM[i] = `RANDOM; + end + slogValid = _RANDOM[4'h0][0]; + slogAddr = _RANDOM[4'h0][2:1]; + debugEn = _RANDOM[4'h0][6:3]; + debugAddr_0 = {_RANDOM[4'h0][31:7], _RANDOM[4'h1][6:0]}; + debugAddr_1 = {_RANDOM[4'h1][31:7], _RANDOM[4'h2][6:0]}; + debugAddr_2 = {_RANDOM[4'h2][31:7], _RANDOM[4'h3][6:0]}; + debugAddr_3 = {_RANDOM[4'h3][31:7], _RANDOM[4'h4][6:0]}; + debugInst_0 = {_RANDOM[4'h4][31:7], _RANDOM[4'h5][6:0]}; + debugInst_1 = {_RANDOM[4'h5][31:7], _RANDOM[4'h6][6:0]}; + debugInst_2 = {_RANDOM[4'h6][31:7], _RANDOM[4'h7][6:0]}; + debugInst_3 = {_RANDOM[4'h7][31:7], _RANDOM[4'h8][6:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + slogValid = 1'h0; + slogAddr = 2'h0; + debugEn = 4'h0; + debugAddr_0 = 32'h0; + debugAddr_1 = 32'h0; + debugAddr_2 = 32'h0; + debugAddr_3 = 32'h0; + debugInst_0 = 32'h0; + debugInst_1 = 32'h0; + debugInst_2 = 32'h0; + debugInst_3 = 32'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Regfile regfile ( + .clock (clock), + .reset (reset), + .io_readAddr_0_valid (_dispatch_io_rs1Read_0_valid), + .io_readAddr_0_addr (_dispatch_io_rs1Read_0_addr), + .io_readAddr_1_valid (_dispatch_io_rs2Read_0_valid), + .io_readAddr_1_addr (_dispatch_io_rs2Read_0_addr), + .io_readAddr_2_valid (_dispatch_io_rs1Read_1_valid), + .io_readAddr_2_addr (_dispatch_io_rs1Read_1_addr), + .io_readAddr_3_valid (_dispatch_io_rs2Read_1_valid), + .io_readAddr_3_addr (_dispatch_io_rs2Read_1_addr), + .io_readAddr_4_valid (_dispatch_io_rs1Read_2_valid), + .io_readAddr_4_addr (_dispatch_io_rs1Read_2_addr), + .io_readAddr_5_valid (_dispatch_io_rs2Read_2_valid), + .io_readAddr_5_addr (_dispatch_io_rs2Read_2_addr), + .io_readAddr_6_valid (_dispatch_io_rs1Read_3_valid), + .io_readAddr_6_addr (_dispatch_io_rs1Read_3_addr), + .io_readAddr_7_valid (_dispatch_io_rs2Read_3_valid), + .io_readAddr_7_addr (_dispatch_io_rs2Read_3_addr), + .io_readSet_0_valid (_dispatch_io_rs1Set_0_valid), + .io_readSet_0_value (_dispatch_io_rs1Set_0_value), + .io_readSet_1_valid (_dispatch_io_rs2Set_0_valid), + .io_readSet_1_value (_dispatch_io_rs2Set_0_value), + .io_readSet_2_valid (_dispatch_io_rs1Set_1_valid), + .io_readSet_2_value (_dispatch_io_rs1Set_1_value), + .io_readSet_3_valid (_dispatch_io_rs2Set_1_valid), + .io_readSet_3_value (_dispatch_io_rs2Set_1_value), + .io_readSet_4_valid (_dispatch_io_rs1Set_2_valid), + .io_readSet_4_value (_dispatch_io_rs1Set_2_value), + .io_readSet_5_valid (_dispatch_io_rs2Set_2_valid), + .io_readSet_5_value (_dispatch_io_rs2Set_2_value), + .io_readSet_6_valid (_dispatch_io_rs1Set_3_valid), + .io_readSet_6_value (_dispatch_io_rs1Set_3_value), + .io_readSet_7_valid (_dispatch_io_rs2Set_3_valid), + .io_readSet_7_value (_dispatch_io_rs2Set_3_value), + .io_writeAddr_0_valid (_dispatch_io_rdMark_0_valid), + .io_writeAddr_0_addr (_dispatch_io_rdMark_0_addr), + .io_writeAddr_1_valid (_dispatch_io_rdMark_1_valid), + .io_writeAddr_1_addr (_dispatch_io_rdMark_1_addr), + .io_writeAddr_2_valid (_dispatch_io_rdMark_2_valid), + .io_writeAddr_2_addr (_dispatch_io_rdMark_2_addr), + .io_writeAddr_3_valid (_dispatch_io_rdMark_3_valid), + .io_writeAddr_3_addr (_dispatch_io_rdMark_3_addr), + .io_busAddr_0_bypass (_dispatch_io_busRead_0_bypass), + .io_busAddr_0_immen (_dispatch_io_busRead_0_immen), + .io_busAddr_0_immed (_dispatch_io_busRead_0_immed), + .io_busAddr_1_bypass (_dispatch_io_busRead_1_bypass), + .io_busAddr_1_immed (_dispatch_io_busRead_1_immed), + .io_busAddr_2_bypass (_dispatch_io_busRead_2_bypass), + .io_busAddr_2_immed (_dispatch_io_busRead_2_immed), + .io_busAddr_3_bypass (_dispatch_io_busRead_3_bypass), + .io_busAddr_3_immed (_dispatch_io_busRead_3_immed), + .io_target_0_data (_regfile_io_target_0_data), + .io_target_1_data (_regfile_io_target_1_data), + .io_target_2_data (_regfile_io_target_2_data), + .io_target_3_data (_regfile_io_target_3_data), + .io_busPort_addr_0 (_regfile_io_busPort_addr_0), + .io_busPort_addr_1 (_regfile_io_busPort_addr_1), + .io_busPort_addr_2 (_regfile_io_busPort_addr_2), + .io_busPort_addr_3 (_regfile_io_busPort_addr_3), + .io_busPort_data_0 (_regfile_io_busPort_data_0), + .io_busPort_data_1 (_regfile_io_busPort_data_1), + .io_busPort_data_2 (_regfile_io_busPort_data_2), + .io_busPort_data_3 (_regfile_io_busPort_data_3), + .io_readData_0_valid (_regfile_io_readData_0_valid), + .io_readData_0_data (_regfile_io_readData_0_data), + .io_readData_1_valid (_regfile_io_readData_1_valid), + .io_readData_1_data (_regfile_io_readData_1_data), + .io_readData_2_valid (_regfile_io_readData_2_valid), + .io_readData_2_data (_regfile_io_readData_2_data), + .io_readData_3_valid (_regfile_io_readData_3_valid), + .io_readData_3_data (_regfile_io_readData_3_data), + .io_readData_4_valid (_regfile_io_readData_4_valid), + .io_readData_4_data (_regfile_io_readData_4_data), + .io_readData_5_valid (_regfile_io_readData_5_valid), + .io_readData_5_data (_regfile_io_readData_5_data), + .io_readData_6_valid (_regfile_io_readData_6_valid), + .io_readData_6_data (_regfile_io_readData_6_data), + .io_readData_7_valid (_regfile_io_readData_7_valid), + .io_readData_7_data (_regfile_io_readData_7_data), + .io_writeData_0_valid (regfile_io_writeData_0_valid), + .io_writeData_0_bits_addr (regfile_io_writeData_0_bits_addr), + .io_writeData_0_bits_data (regfile_io_writeData_0_bits_data), + .io_writeData_1_valid (regfile_io_writeData_1_valid), + .io_writeData_1_bits_addr (regfile_io_writeData_1_bits_addr), + .io_writeData_1_bits_data (regfile_io_writeData_1_bits_data), + .io_writeData_2_valid (regfile_io_writeData_2_valid), + .io_writeData_2_bits_addr (regfile_io_writeData_2_bits_addr), + .io_writeData_2_bits_data (regfile_io_writeData_2_bits_data), + .io_writeData_3_valid (regfile_io_writeData_3_valid), + .io_writeData_3_bits_addr (regfile_io_writeData_3_bits_addr), + .io_writeData_3_bits_data (regfile_io_writeData_3_bits_data), + .io_writeData_4_valid (_arb_io_out_valid), + .io_writeData_4_bits_addr (_arb_io_out_bits_addr), + .io_writeData_4_bits_data (_arb_io_out_bits_data), + .io_writeData_5_valid (_lsu_io_rd_valid), + .io_writeData_5_bits_addr (_lsu_io_rd_bits_addr), + .io_writeData_5_bits_data (_lsu_io_rd_bits_data), + .io_writeMask_1_valid (_bru_0_io_taken_valid), + .io_writeMask_2_valid (writeMask_2), + .io_writeMask_3_valid (writeMask_2 | _bru_2_io_taken_valid), + .io_scoreboard_regd (_regfile_io_scoreboard_regd), + .io_scoreboard_comb (_regfile_io_scoreboard_comb), + .io_rfwriteCount (_regfile_io_rfwriteCount) + ); + UncachedFetch fetch ( + .clock (clock), + .reset (reset), + .io_csr_value_0 (io_csr_in_value_0), + .io_ibus_valid (_fetch_io_ibus_valid), + .io_ibus_ready (~_lsu_io_ibus_valid), + .io_ibus_addr (_fetch_io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_inst_lanes_0_ready (_dispatch_io_inst_0_ready), + .io_inst_lanes_0_valid (_fetch_io_inst_lanes_0_valid), + .io_inst_lanes_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), + .io_inst_lanes_0_bits_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_inst_lanes_0_bits_brchFwd (_fetch_io_inst_lanes_0_bits_brchFwd), + .io_inst_lanes_1_ready (_dispatch_io_inst_1_ready), + .io_inst_lanes_1_valid (_fetch_io_inst_lanes_1_valid), + .io_inst_lanes_1_bits_addr (_fetch_io_inst_lanes_1_bits_addr), + .io_inst_lanes_1_bits_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_inst_lanes_1_bits_brchFwd (_fetch_io_inst_lanes_1_bits_brchFwd), + .io_inst_lanes_2_ready (_dispatch_io_inst_2_ready), + .io_inst_lanes_2_valid (_fetch_io_inst_lanes_2_valid), + .io_inst_lanes_2_bits_addr (_fetch_io_inst_lanes_2_bits_addr), + .io_inst_lanes_2_bits_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_inst_lanes_2_bits_brchFwd (_fetch_io_inst_lanes_2_bits_brchFwd), + .io_inst_lanes_3_ready (_dispatch_io_inst_3_ready), + .io_inst_lanes_3_valid (_fetch_io_inst_lanes_3_valid), + .io_inst_lanes_3_bits_addr (_fetch_io_inst_lanes_3_bits_addr), + .io_inst_lanes_3_bits_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_inst_lanes_3_bits_brchFwd (_fetch_io_inst_lanes_3_bits_brchFwd), + .io_branch_0_valid (_bru_0_io_taken_valid), + .io_branch_0_value (_bru_0_io_taken_value), + .io_branch_1_valid (_bru_1_io_taken_valid), + .io_branch_1_value (_bru_1_io_taken_value), + .io_branch_2_valid (_bru_2_io_taken_valid), + .io_branch_2_value (_bru_2_io_taken_value), + .io_branch_3_valid (_bru_3_io_taken_valid), + .io_branch_3_value (_bru_3_io_taken_value), + .io_iflush_valid (_lsu_io_flush_valid & _lsu_io_flush_fencei), + .io_iflush_pcNext (_lsu_io_flush_pcNext), + .io_pc (_fetch_io_pc) + ); + Csr csr ( + .clock (clock), + .reset (reset), + .io_csr_in_value_12 (_fetch_io_pc), + .io_csr_out_value_0 (io_csr_out_value_0), + .io_csr_out_value_1 (io_csr_out_value_1), + .io_csr_out_value_2 (io_csr_out_value_2), + .io_csr_out_value_3 (io_csr_out_value_3), + .io_csr_out_value_4 (_csr_io_csr_out_value_4), + .io_csr_out_value_5 (io_csr_out_value_5), + .io_csr_out_value_6 (io_csr_out_value_6), + .io_csr_out_value_7 (io_csr_out_value_7), + .io_req_valid (_dispatch_io_csr_valid), + .io_req_bits_addr (_dispatch_io_csr_bits_addr), + .io_req_bits_index (_dispatch_io_csr_bits_index), + .io_req_bits_op (_dispatch_io_csr_bits_op), + .io_rs1_valid (_regfile_io_readData_0_valid), + .io_rs1_data (_regfile_io_readData_0_data), + .io_rd_valid (_csr_io_rd_valid), + .io_rd_bits_addr (_csr_io_rd_bits_addr), + .io_rd_bits_data (_csr_io_rd_bits_data), + .io_bru_in_mode_valid (_bru_0_io_csr_in_mode_valid), + .io_bru_in_mode_bits (_bru_0_io_csr_in_mode_bits), + .io_bru_in_mcause_valid (_bru_0_io_csr_in_mcause_valid), + .io_bru_in_mcause_bits (_bru_0_io_csr_in_mcause_bits), + .io_bru_in_mepc_valid (_bru_0_io_csr_in_mepc_valid), + .io_bru_in_mepc_bits (_bru_0_io_csr_in_mepc_bits), + .io_bru_in_mtval_valid (_bru_0_io_csr_in_mtval_valid), + .io_bru_in_mtval_bits (_bru_0_io_csr_in_mtval_bits), + .io_bru_in_halt (_bru_0_io_csr_in_halt), + .io_bru_in_fault (_bru_0_io_csr_in_fault), + .io_bru_in_wfi (_bru_0_io_csr_in_wfi), + .io_bru_out_mode (_csr_io_bru_out_mode), + .io_bru_out_mepc (_csr_io_bru_out_mepc), + .io_bru_out_mtvec (_csr_io_bru_out_mtvec), + .io_float_in_fflags_valid (_floatCore_io_csr_in_fflags_valid), + .io_float_in_fflags_bits (_floatCore_io_csr_in_fflags_bits), + .io_float_out_frm (_csr_io_float_out_frm), + .io_counters_rfwriteCount (_regfile_io_rfwriteCount[2:0]), + .io_counters_storeCount (_lsu_io_storeCount), + .io_counters_branchCount (_bru_0_io_taken_valid), + .io_halted (_csr_io_halted), + .io_fault (io_fault), + .io_wfi (_csr_io_wfi), + .io_irq (io_irq) + ); + DispatchV1 dispatch ( + .io_halted (_csr_io_halted | _csr_io_wfi), + .io_lsuActive (_lsu_io_active), + .io_scoreboard_regd (_regfile_io_scoreboard_regd), + .io_scoreboard_comb (_regfile_io_scoreboard_comb), + .io_fscoreboard (_fRegfile_io_scoreboard), + .io_branchTaken (branchTaken), + .io_csrFault_0 (_dispatch_io_csrFault_0), + .io_jalFault_0 (_dispatch_io_jalFault_0), + .io_jalFault_1 (_dispatch_io_jalFault_1), + .io_jalFault_2 (_dispatch_io_jalFault_2), + .io_jalFault_3 (_dispatch_io_jalFault_3), + .io_jalrFault_0 (_dispatch_io_jalrFault_0), + .io_jalrFault_1 (_dispatch_io_jalrFault_1), + .io_jalrFault_2 (_dispatch_io_jalrFault_2), + .io_jalrFault_3 (_dispatch_io_jalrFault_3), + .io_bxxFault_0 (_dispatch_io_bxxFault_0), + .io_bxxFault_1 (_dispatch_io_bxxFault_1), + .io_bxxFault_2 (_dispatch_io_bxxFault_2), + .io_bxxFault_3 (_dispatch_io_bxxFault_3), + .io_undefFault_0 (_dispatch_io_undefFault_0), + .io_bruTarget_0 (_dispatch_io_bruTarget_0), + .io_bruTarget_1 (_dispatch_io_bruTarget_1), + .io_bruTarget_2 (_dispatch_io_bruTarget_2), + .io_bruTarget_3 (_dispatch_io_bruTarget_3), + .io_jalrTarget_0_data (_regfile_io_target_0_data), + .io_jalrTarget_1_data (_regfile_io_target_1_data), + .io_jalrTarget_2_data (_regfile_io_target_2_data), + .io_jalrTarget_3_data (_regfile_io_target_3_data), + .io_interlock (_bru_0_io_interlock | _lsu_io_flush_valid), + .io_inst_0_ready (_dispatch_io_inst_0_ready), + .io_inst_0_valid (_fetch_io_inst_lanes_0_valid), + .io_inst_0_bits_addr (_fetch_io_inst_lanes_0_bits_addr), + .io_inst_0_bits_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_inst_0_bits_brchFwd (_fetch_io_inst_lanes_0_bits_brchFwd), + .io_inst_1_ready (_dispatch_io_inst_1_ready), + .io_inst_1_valid (_fetch_io_inst_lanes_1_valid), + .io_inst_1_bits_addr (_fetch_io_inst_lanes_1_bits_addr), + .io_inst_1_bits_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_inst_1_bits_brchFwd (_fetch_io_inst_lanes_1_bits_brchFwd), + .io_inst_2_ready (_dispatch_io_inst_2_ready), + .io_inst_2_valid (_fetch_io_inst_lanes_2_valid), + .io_inst_2_bits_addr (_fetch_io_inst_lanes_2_bits_addr), + .io_inst_2_bits_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_inst_2_bits_brchFwd (_fetch_io_inst_lanes_2_bits_brchFwd), + .io_inst_3_ready (_dispatch_io_inst_3_ready), + .io_inst_3_valid (_fetch_io_inst_lanes_3_valid), + .io_inst_3_bits_addr (_fetch_io_inst_lanes_3_bits_addr), + .io_inst_3_bits_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_inst_3_bits_brchFwd (_fetch_io_inst_lanes_3_bits_brchFwd), + .io_rs1Read_0_valid (_dispatch_io_rs1Read_0_valid), + .io_rs1Read_0_addr (_dispatch_io_rs1Read_0_addr), + .io_rs1Read_1_valid (_dispatch_io_rs1Read_1_valid), + .io_rs1Read_1_addr (_dispatch_io_rs1Read_1_addr), + .io_rs1Read_2_valid (_dispatch_io_rs1Read_2_valid), + .io_rs1Read_2_addr (_dispatch_io_rs1Read_2_addr), + .io_rs1Read_3_valid (_dispatch_io_rs1Read_3_valid), + .io_rs1Read_3_addr (_dispatch_io_rs1Read_3_addr), + .io_rs1Set_0_valid (_dispatch_io_rs1Set_0_valid), + .io_rs1Set_0_value (_dispatch_io_rs1Set_0_value), + .io_rs1Set_1_valid (_dispatch_io_rs1Set_1_valid), + .io_rs1Set_1_value (_dispatch_io_rs1Set_1_value), + .io_rs1Set_2_valid (_dispatch_io_rs1Set_2_valid), + .io_rs1Set_2_value (_dispatch_io_rs1Set_2_value), + .io_rs1Set_3_valid (_dispatch_io_rs1Set_3_valid), + .io_rs1Set_3_value (_dispatch_io_rs1Set_3_value), + .io_rs2Read_0_valid (_dispatch_io_rs2Read_0_valid), + .io_rs2Read_0_addr (_dispatch_io_rs2Read_0_addr), + .io_rs2Read_1_valid (_dispatch_io_rs2Read_1_valid), + .io_rs2Read_1_addr (_dispatch_io_rs2Read_1_addr), + .io_rs2Read_2_valid (_dispatch_io_rs2Read_2_valid), + .io_rs2Read_2_addr (_dispatch_io_rs2Read_2_addr), + .io_rs2Read_3_valid (_dispatch_io_rs2Read_3_valid), + .io_rs2Read_3_addr (_dispatch_io_rs2Read_3_addr), + .io_rs2Set_0_valid (_dispatch_io_rs2Set_0_valid), + .io_rs2Set_0_value (_dispatch_io_rs2Set_0_value), + .io_rs2Set_1_valid (_dispatch_io_rs2Set_1_valid), + .io_rs2Set_1_value (_dispatch_io_rs2Set_1_value), + .io_rs2Set_2_valid (_dispatch_io_rs2Set_2_valid), + .io_rs2Set_2_value (_dispatch_io_rs2Set_2_value), + .io_rs2Set_3_valid (_dispatch_io_rs2Set_3_valid), + .io_rs2Set_3_value (_dispatch_io_rs2Set_3_value), + .io_rdMark_0_valid (_dispatch_io_rdMark_0_valid), + .io_rdMark_0_addr (_dispatch_io_rdMark_0_addr), + .io_rdMark_1_valid (_dispatch_io_rdMark_1_valid), + .io_rdMark_1_addr (_dispatch_io_rdMark_1_addr), + .io_rdMark_2_valid (_dispatch_io_rdMark_2_valid), + .io_rdMark_2_addr (_dispatch_io_rdMark_2_addr), + .io_rdMark_3_valid (_dispatch_io_rdMark_3_valid), + .io_rdMark_3_addr (_dispatch_io_rdMark_3_addr), + .io_busRead_0_bypass (_dispatch_io_busRead_0_bypass), + .io_busRead_0_immen (_dispatch_io_busRead_0_immen), + .io_busRead_0_immed (_dispatch_io_busRead_0_immed), + .io_busRead_1_bypass (_dispatch_io_busRead_1_bypass), + .io_busRead_1_immed (_dispatch_io_busRead_1_immed), + .io_busRead_2_bypass (_dispatch_io_busRead_2_bypass), + .io_busRead_2_immed (_dispatch_io_busRead_2_immed), + .io_busRead_3_bypass (_dispatch_io_busRead_3_bypass), + .io_busRead_3_immed (_dispatch_io_busRead_3_immed), + .io_rdMark_flt_valid (_dispatch_io_rdMark_flt_valid), + .io_rdMark_flt_addr (_dispatch_io_rdMark_flt_addr), + .io_alu_0_valid (_dispatch_io_alu_0_valid), + .io_alu_0_bits_addr (_dispatch_io_alu_0_bits_addr), + .io_alu_0_bits_op (_dispatch_io_alu_0_bits_op), + .io_alu_1_valid (_dispatch_io_alu_1_valid), + .io_alu_1_bits_addr (_dispatch_io_alu_1_bits_addr), + .io_alu_1_bits_op (_dispatch_io_alu_1_bits_op), + .io_alu_2_valid (_dispatch_io_alu_2_valid), + .io_alu_2_bits_addr (_dispatch_io_alu_2_bits_addr), + .io_alu_2_bits_op (_dispatch_io_alu_2_bits_op), + .io_alu_3_valid (_dispatch_io_alu_3_valid), + .io_alu_3_bits_addr (_dispatch_io_alu_3_bits_addr), + .io_alu_3_bits_op (_dispatch_io_alu_3_bits_op), + .io_bru_0_valid (_dispatch_io_bru_0_valid), + .io_bru_0_bits_fwd (_dispatch_io_bru_0_bits_fwd), + .io_bru_0_bits_op (_dispatch_io_bru_0_bits_op), + .io_bru_0_bits_pc (_dispatch_io_bru_0_bits_pc), + .io_bru_0_bits_target (_dispatch_io_bru_0_bits_target), + .io_bru_0_bits_link (_dispatch_io_bru_0_bits_link), + .io_bru_1_valid (_dispatch_io_bru_1_valid), + .io_bru_1_bits_fwd (_dispatch_io_bru_1_bits_fwd), + .io_bru_1_bits_op (_dispatch_io_bru_1_bits_op), + .io_bru_1_bits_pc (_dispatch_io_bru_1_bits_pc), + .io_bru_1_bits_target (_dispatch_io_bru_1_bits_target), + .io_bru_1_bits_link (_dispatch_io_bru_1_bits_link), + .io_bru_2_valid (_dispatch_io_bru_2_valid), + .io_bru_2_bits_fwd (_dispatch_io_bru_2_bits_fwd), + .io_bru_2_bits_op (_dispatch_io_bru_2_bits_op), + .io_bru_2_bits_pc (_dispatch_io_bru_2_bits_pc), + .io_bru_2_bits_target (_dispatch_io_bru_2_bits_target), + .io_bru_2_bits_link (_dispatch_io_bru_2_bits_link), + .io_bru_3_valid (_dispatch_io_bru_3_valid), + .io_bru_3_bits_fwd (_dispatch_io_bru_3_bits_fwd), + .io_bru_3_bits_op (_dispatch_io_bru_3_bits_op), + .io_bru_3_bits_pc (_dispatch_io_bru_3_bits_pc), + .io_bru_3_bits_target (_dispatch_io_bru_3_bits_target), + .io_bru_3_bits_link (_dispatch_io_bru_3_bits_link), + .io_csr_valid (_dispatch_io_csr_valid), + .io_csr_bits_addr (_dispatch_io_csr_bits_addr), + .io_csr_bits_index (_dispatch_io_csr_bits_index), + .io_csr_bits_op (_dispatch_io_csr_bits_op), + .io_lsu_0_ready (_lsu_io_req_0_ready), + .io_lsu_0_valid (_dispatch_io_lsu_0_valid), + .io_lsu_0_bits_store (_dispatch_io_lsu_0_bits_store), + .io_lsu_0_bits_addr (_dispatch_io_lsu_0_bits_addr), + .io_lsu_0_bits_op (_dispatch_io_lsu_0_bits_op), + .io_lsu_0_bits_pc (_dispatch_io_lsu_0_bits_pc), + .io_lsu_1_ready (_lsu_io_req_1_ready), + .io_lsu_1_valid (_dispatch_io_lsu_1_valid), + .io_lsu_1_bits_store (_dispatch_io_lsu_1_bits_store), + .io_lsu_1_bits_addr (_dispatch_io_lsu_1_bits_addr), + .io_lsu_1_bits_op (_dispatch_io_lsu_1_bits_op), + .io_lsu_1_bits_pc (_dispatch_io_lsu_1_bits_pc), + .io_lsu_2_ready (_lsu_io_req_2_ready), + .io_lsu_2_valid (_dispatch_io_lsu_2_valid), + .io_lsu_2_bits_store (_dispatch_io_lsu_2_bits_store), + .io_lsu_2_bits_addr (_dispatch_io_lsu_2_bits_addr), + .io_lsu_2_bits_op (_dispatch_io_lsu_2_bits_op), + .io_lsu_2_bits_pc (_dispatch_io_lsu_2_bits_pc), + .io_lsu_3_ready (_lsu_io_req_3_ready), + .io_lsu_3_valid (_dispatch_io_lsu_3_valid), + .io_lsu_3_bits_store (_dispatch_io_lsu_3_bits_store), + .io_lsu_3_bits_addr (_dispatch_io_lsu_3_bits_addr), + .io_lsu_3_bits_op (_dispatch_io_lsu_3_bits_op), + .io_lsu_3_bits_pc (_dispatch_io_lsu_3_bits_pc), + .io_mlu_0_valid (_dispatch_io_mlu_0_valid), + .io_mlu_0_bits_addr (_dispatch_io_mlu_0_bits_addr), + .io_mlu_0_bits_op (_dispatch_io_mlu_0_bits_op), + .io_mlu_1_valid (_dispatch_io_mlu_1_valid), + .io_mlu_1_bits_addr (_dispatch_io_mlu_1_bits_addr), + .io_mlu_1_bits_op (_dispatch_io_mlu_1_bits_op), + .io_mlu_2_valid (_dispatch_io_mlu_2_valid), + .io_mlu_2_bits_addr (_dispatch_io_mlu_2_bits_addr), + .io_mlu_2_bits_op (_dispatch_io_mlu_2_bits_op), + .io_mlu_3_valid (_dispatch_io_mlu_3_valid), + .io_mlu_3_bits_addr (_dispatch_io_mlu_3_bits_addr), + .io_mlu_3_bits_op (_dispatch_io_mlu_3_bits_op), + .io_dvu_0_ready (_dvu_io_req_ready), + .io_dvu_0_valid (_dispatch_io_dvu_0_valid), + .io_dvu_0_bits_addr (_dispatch_io_dvu_0_bits_addr), + .io_dvu_0_bits_op (_dispatch_io_dvu_0_bits_op), + .io_float_ready (_floatCore_io_inst_ready), + .io_float_valid (_dispatch_io_float_valid), + .io_float_bits_opcode (_dispatch_io_float_bits_opcode), + .io_float_bits_funct5 (_dispatch_io_float_bits_funct5), + .io_float_bits_rs3 (_dispatch_io_float_bits_rs3), + .io_float_bits_rs2 (_dispatch_io_float_bits_rs2), + .io_float_bits_rs1 (_dispatch_io_float_bits_rs1), + .io_float_bits_rm (_dispatch_io_float_bits_rm), + .io_float_bits_inst (_dispatch_io_float_bits_inst), + .io_float_bits_pc (_dispatch_io_float_bits_pc), + .io_float_bits_scalar_rd (_dispatch_io_float_bits_scalar_rd), + .io_float_bits_scalar_rs1 (_dispatch_io_float_bits_scalar_rs1), + .io_float_bits_rd (_dispatch_io_float_bits_rd), + .io_float_bits_uses_rs3 (_dispatch_io_float_bits_uses_rs3), + .io_float_bits_uses_rs2 (_dispatch_io_float_bits_uses_rs2), + .io_fbusPortAddr (_dispatch_io_fbusPortAddr), + .io_slog (_dispatch_io_slog) + ); + Alu alu_0 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_alu_0_valid), + .io_req_bits_addr (_dispatch_io_alu_0_bits_addr), + .io_req_bits_op (_dispatch_io_alu_0_bits_op), + .io_rs1_valid (_regfile_io_readData_0_valid), + .io_rs1_data (_regfile_io_readData_0_data), + .io_rs2_valid (_regfile_io_readData_1_valid), + .io_rs2_data (_regfile_io_readData_1_data), + .io_rd_valid (_alu_0_io_rd_valid), + .io_rd_bits_addr (_alu_0_io_rd_bits_addr), + .io_rd_bits_data (_alu_0_io_rd_bits_data) + ); + Alu alu_1 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_alu_1_valid), + .io_req_bits_addr (_dispatch_io_alu_1_bits_addr), + .io_req_bits_op (_dispatch_io_alu_1_bits_op), + .io_rs1_valid (_regfile_io_readData_2_valid), + .io_rs1_data (_regfile_io_readData_2_data), + .io_rs2_valid (_regfile_io_readData_3_valid), + .io_rs2_data (_regfile_io_readData_3_data), + .io_rd_valid (_alu_1_io_rd_valid), + .io_rd_bits_addr (_alu_1_io_rd_bits_addr), + .io_rd_bits_data (_alu_1_io_rd_bits_data) + ); + Alu alu_2 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_alu_2_valid), + .io_req_bits_addr (_dispatch_io_alu_2_bits_addr), + .io_req_bits_op (_dispatch_io_alu_2_bits_op), + .io_rs1_valid (_regfile_io_readData_4_valid), + .io_rs1_data (_regfile_io_readData_4_data), + .io_rs2_valid (_regfile_io_readData_5_valid), + .io_rs2_data (_regfile_io_readData_5_data), + .io_rd_valid (_alu_2_io_rd_valid), + .io_rd_bits_addr (_alu_2_io_rd_bits_addr), + .io_rd_bits_data (_alu_2_io_rd_bits_data) + ); + Alu alu_3 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_alu_3_valid), + .io_req_bits_addr (_dispatch_io_alu_3_bits_addr), + .io_req_bits_op (_dispatch_io_alu_3_bits_op), + .io_rs1_valid (_regfile_io_readData_6_valid), + .io_rs1_data (_regfile_io_readData_6_data), + .io_rs2_valid (_regfile_io_readData_7_valid), + .io_rs2_data (_regfile_io_readData_7_data), + .io_rd_valid (_alu_3_io_rd_valid), + .io_rd_bits_addr (_alu_3_io_rd_bits_addr), + .io_rd_bits_data (_alu_3_io_rd_bits_data) + ); + Bru bru_0 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_bru_0_valid), + .io_req_bits_fwd (_dispatch_io_bru_0_bits_fwd), + .io_req_bits_op (_dispatch_io_bru_0_bits_op), + .io_req_bits_pc (_dispatch_io_bru_0_bits_pc), + .io_req_bits_target (_dispatch_io_bru_0_bits_target), + .io_req_bits_link (_dispatch_io_bru_0_bits_link), + .io_csr_in_mode_valid (_bru_0_io_csr_in_mode_valid), + .io_csr_in_mode_bits (_bru_0_io_csr_in_mode_bits), + .io_csr_in_mcause_valid (_bru_0_io_csr_in_mcause_valid), + .io_csr_in_mcause_bits (_bru_0_io_csr_in_mcause_bits), + .io_csr_in_mepc_valid (_bru_0_io_csr_in_mepc_valid), + .io_csr_in_mepc_bits (_bru_0_io_csr_in_mepc_bits), + .io_csr_in_mtval_valid (_bru_0_io_csr_in_mtval_valid), + .io_csr_in_mtval_bits (_bru_0_io_csr_in_mtval_bits), + .io_csr_in_halt (_bru_0_io_csr_in_halt), + .io_csr_in_fault (_bru_0_io_csr_in_fault), + .io_csr_in_wfi (_bru_0_io_csr_in_wfi), + .io_csr_out_mode (_csr_io_bru_out_mode), + .io_csr_out_mepc (_csr_io_bru_out_mepc), + .io_csr_out_mtvec (_csr_io_bru_out_mtvec), + .io_rs1_valid (_regfile_io_readData_0_valid), + .io_rs1_data (_regfile_io_readData_0_data), + .io_rs2_valid (_regfile_io_readData_1_valid), + .io_rs2_data (_regfile_io_readData_1_data), + .io_rd_valid (_bru_0_io_rd_valid), + .io_rd_bits_addr (_bru_0_io_rd_bits_addr), + .io_rd_bits_data (_bru_0_io_rd_bits_data), + .io_taken_valid (_bru_0_io_taken_valid), + .io_taken_value (_bru_0_io_taken_value), + .io_target_data (_regfile_io_target_0_data), + .io_interlock (_bru_0_io_interlock), + .io_fault_manager_valid (_fault_manager_io_out_valid), + .io_fault_manager_bits_mepc (_fault_manager_io_out_bits_mepc), + .io_fault_manager_bits_mtval (_fault_manager_io_out_bits_mtval), + .io_fault_manager_bits_mcause (_fault_manager_io_out_bits_mcause) + ); + Bru_1 bru_1 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_bru_1_valid), + .io_req_bits_fwd (_dispatch_io_bru_1_bits_fwd), + .io_req_bits_op (_dispatch_io_bru_1_bits_op), + .io_req_bits_pc (_dispatch_io_bru_1_bits_pc), + .io_req_bits_target (_dispatch_io_bru_1_bits_target), + .io_req_bits_link (_dispatch_io_bru_1_bits_link), + .io_rs1_valid (_regfile_io_readData_2_valid), + .io_rs1_data (_regfile_io_readData_2_data), + .io_rs2_valid (_regfile_io_readData_3_valid), + .io_rs2_data (_regfile_io_readData_3_data), + .io_rd_valid (_bru_1_io_rd_valid), + .io_rd_bits_addr (_bru_1_io_rd_bits_addr), + .io_rd_bits_data (_bru_1_io_rd_bits_data), + .io_taken_valid (_bru_1_io_taken_valid), + .io_taken_value (_bru_1_io_taken_value), + .io_target_data (_regfile_io_target_1_data) + ); + Bru_1 bru_2 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_bru_2_valid), + .io_req_bits_fwd (_dispatch_io_bru_2_bits_fwd), + .io_req_bits_op (_dispatch_io_bru_2_bits_op), + .io_req_bits_pc (_dispatch_io_bru_2_bits_pc), + .io_req_bits_target (_dispatch_io_bru_2_bits_target), + .io_req_bits_link (_dispatch_io_bru_2_bits_link), + .io_rs1_valid (_regfile_io_readData_4_valid), + .io_rs1_data (_regfile_io_readData_4_data), + .io_rs2_valid (_regfile_io_readData_5_valid), + .io_rs2_data (_regfile_io_readData_5_data), + .io_rd_valid (_bru_2_io_rd_valid), + .io_rd_bits_addr (_bru_2_io_rd_bits_addr), + .io_rd_bits_data (_bru_2_io_rd_bits_data), + .io_taken_valid (_bru_2_io_taken_valid), + .io_taken_value (_bru_2_io_taken_value), + .io_target_data (_regfile_io_target_2_data) + ); + Bru_1 bru_3 ( + .clock (clock), + .reset (reset), + .io_req_valid (_dispatch_io_bru_3_valid), + .io_req_bits_fwd (_dispatch_io_bru_3_bits_fwd), + .io_req_bits_op (_dispatch_io_bru_3_bits_op), + .io_req_bits_pc (_dispatch_io_bru_3_bits_pc), + .io_req_bits_target (_dispatch_io_bru_3_bits_target), + .io_req_bits_link (_dispatch_io_bru_3_bits_link), + .io_rs1_valid (_regfile_io_readData_6_valid), + .io_rs1_data (_regfile_io_readData_6_data), + .io_rs2_valid (_regfile_io_readData_7_valid), + .io_rs2_data (_regfile_io_readData_7_data), + .io_rd_valid (_bru_3_io_rd_valid), + .io_rd_bits_addr (_bru_3_io_rd_bits_addr), + .io_rd_bits_data (_bru_3_io_rd_bits_data), + .io_taken_valid (_bru_3_io_taken_valid), + .io_taken_value (_bru_3_io_taken_value), + .io_target_data (_regfile_io_target_3_data) + ); + LsuV1 lsu ( + .clock (clock), + .reset (reset), + .io_req_0_ready (_lsu_io_req_0_ready), + .io_req_0_valid (_dispatch_io_lsu_0_valid), + .io_req_0_bits_store (_dispatch_io_lsu_0_bits_store), + .io_req_0_bits_addr (_dispatch_io_lsu_0_bits_addr), + .io_req_0_bits_op (_dispatch_io_lsu_0_bits_op), + .io_req_0_bits_pc (_dispatch_io_lsu_0_bits_pc), + .io_req_1_ready (_lsu_io_req_1_ready), + .io_req_1_valid (_dispatch_io_lsu_1_valid), + .io_req_1_bits_store (_dispatch_io_lsu_1_bits_store), + .io_req_1_bits_addr (_dispatch_io_lsu_1_bits_addr), + .io_req_1_bits_op (_dispatch_io_lsu_1_bits_op), + .io_req_1_bits_pc (_dispatch_io_lsu_1_bits_pc), + .io_req_2_ready (_lsu_io_req_2_ready), + .io_req_2_valid (_dispatch_io_lsu_2_valid), + .io_req_2_bits_store (_dispatch_io_lsu_2_bits_store), + .io_req_2_bits_addr (_dispatch_io_lsu_2_bits_addr), + .io_req_2_bits_op (_dispatch_io_lsu_2_bits_op), + .io_req_2_bits_pc (_dispatch_io_lsu_2_bits_pc), + .io_req_3_ready (_lsu_io_req_3_ready), + .io_req_3_valid (_dispatch_io_lsu_3_valid), + .io_req_3_bits_store (_dispatch_io_lsu_3_bits_store), + .io_req_3_bits_addr (_dispatch_io_lsu_3_bits_addr), + .io_req_3_bits_op (_dispatch_io_lsu_3_bits_op), + .io_req_3_bits_pc (_dispatch_io_lsu_3_bits_pc), + .io_busPort_addr_0 (_regfile_io_busPort_addr_0), + .io_busPort_addr_1 (_regfile_io_busPort_addr_1), + .io_busPort_addr_2 (_regfile_io_busPort_addr_2), + .io_busPort_addr_3 (_regfile_io_busPort_addr_3), + .io_busPort_data_0 (_regfile_io_busPort_data_0), + .io_busPort_data_1 (_regfile_io_busPort_data_1), + .io_busPort_data_2 (_regfile_io_busPort_data_2), + .io_busPort_data_3 (_regfile_io_busPort_data_3), + .io_busPort_flt_data_0 (_fRegfile_io_busPort_data_0), + .io_rd_valid (_lsu_io_rd_valid), + .io_rd_bits_addr (_lsu_io_rd_bits_addr), + .io_rd_bits_data (_lsu_io_rd_bits_data), + .io_rd_flt_valid (_lsu_io_rd_flt_valid), + .io_rd_flt_bits_addr (_lsu_io_rd_flt_bits_addr), + .io_rd_flt_bits_data (_lsu_io_rd_flt_bits_data), + .io_ibus_valid (_lsu_io_ibus_valid), + .io_ibus_ready (_lsu_io_ibus_valid), + .io_ibus_addr (_lsu_io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_dbus_valid (_lsu_io_dbus_valid), + .io_dbus_write (_lsu_io_dbus_write), + .io_dbus_addr (_lsu_io_dbus_addr), + .io_dbus_wdata (_lsu_io_dbus_wdata), + .io_dbus_wmask (io_dbus_wmask), + .io_dbus_rdata (io_dbus_rdata), + .io_flush_valid (_lsu_io_flush_valid), + .io_flush_ready (_lsu_io_flush_valid), + .io_flush_fencei (_lsu_io_flush_fencei), + .io_flush_pcNext (_lsu_io_flush_pcNext), + .io_fault_valid (_lsu_io_fault_valid), + .io_fault_bits_write (_lsu_io_fault_bits_write), + .io_fault_bits_addr (_lsu_io_fault_bits_addr), + .io_fault_bits_epc (_lsu_io_fault_bits_epc), + .io_ebus_dbus_valid (io_ebus_dbus_valid), + .io_ebus_dbus_ready (io_ebus_dbus_ready), + .io_ebus_dbus_write (io_ebus_dbus_write), + .io_ebus_dbus_pc (io_ebus_dbus_pc), + .io_ebus_dbus_addr (io_ebus_dbus_addr), + .io_ebus_dbus_size (io_ebus_dbus_size), + .io_ebus_dbus_wdata (io_ebus_dbus_wdata), + .io_ebus_dbus_rdata (io_ebus_dbus_rdata), + .io_ebus_fault_valid (io_ebus_fault_valid), + .io_ebus_fault_bits_write (io_ebus_fault_bits_write), + .io_ebus_fault_bits_addr (io_ebus_fault_bits_addr), + .io_ebus_fault_bits_epc (io_ebus_fault_bits_epc), + .io_storeCount (_lsu_io_storeCount), + .io_active (_lsu_io_active) + ); + Mlu mlu ( + .clock (clock), + .reset (reset), + .io_req_0_valid (_dispatch_io_mlu_0_valid), + .io_req_0_bits_addr (_dispatch_io_mlu_0_bits_addr), + .io_req_0_bits_op (_dispatch_io_mlu_0_bits_op), + .io_req_1_valid (_dispatch_io_mlu_1_valid), + .io_req_1_bits_addr (_dispatch_io_mlu_1_bits_addr), + .io_req_1_bits_op (_dispatch_io_mlu_1_bits_op), + .io_req_2_valid (_dispatch_io_mlu_2_valid), + .io_req_2_bits_addr (_dispatch_io_mlu_2_bits_addr), + .io_req_2_bits_op (_dispatch_io_mlu_2_bits_op), + .io_req_3_valid (_dispatch_io_mlu_3_valid), + .io_req_3_bits_addr (_dispatch_io_mlu_3_bits_addr), + .io_req_3_bits_op (_dispatch_io_mlu_3_bits_op), + .io_rs1_0_valid (_regfile_io_readData_0_valid), + .io_rs1_0_data (_regfile_io_readData_0_data), + .io_rs1_1_valid (_regfile_io_readData_2_valid), + .io_rs1_1_data (_regfile_io_readData_2_data), + .io_rs1_2_valid (_regfile_io_readData_4_valid), + .io_rs1_2_data (_regfile_io_readData_4_data), + .io_rs1_3_valid (_regfile_io_readData_6_valid), + .io_rs1_3_data (_regfile_io_readData_6_data), + .io_rs2_0_valid (_regfile_io_readData_1_valid), + .io_rs2_0_data (_regfile_io_readData_1_data), + .io_rs2_1_valid (_regfile_io_readData_3_valid), + .io_rs2_1_data (_regfile_io_readData_3_data), + .io_rs2_2_valid (_regfile_io_readData_5_valid), + .io_rs2_2_data (_regfile_io_readData_5_data), + .io_rs2_3_valid (_regfile_io_readData_7_valid), + .io_rs2_3_data (_regfile_io_readData_7_data), + .io_rd_valid (_mlu_io_rd_valid), + .io_rd_bits_addr (_mlu_io_rd_bits_addr), + .io_rd_bits_data (_mlu_io_rd_bits_data) + ); + Dvu dvu ( + .clock (clock), + .reset (reset), + .io_req_ready (_dvu_io_req_ready), + .io_req_valid (_dispatch_io_dvu_0_valid), + .io_req_bits_addr (_dispatch_io_dvu_0_bits_addr), + .io_req_bits_op (_dispatch_io_dvu_0_bits_op), + .io_rs1_data (_regfile_io_readData_0_data), + .io_rs2_data (_regfile_io_readData_1_data), + .io_rd_ready (_arb_io_in_1_ready), + .io_rd_valid (_dvu_io_rd_valid), + .io_rd_bits_addr (_dvu_io_rd_bits_addr), + .io_rd_bits_data (_dvu_io_rd_bits_data) + ); + FaultManager fault_manager ( + .io_in_fault_0_csr (_dispatch_io_csrFault_0), + .io_in_fault_0_jal (_dispatch_io_jalFault_0), + .io_in_fault_0_jalr (_dispatch_io_jalrFault_0), + .io_in_fault_0_bxx (_dispatch_io_bxxFault_0), + .io_in_fault_0_undef (_dispatch_io_undefFault_0), + .io_in_fault_1_jal (_dispatch_io_jalFault_1), + .io_in_fault_1_jalr (_dispatch_io_jalrFault_1), + .io_in_fault_1_bxx (_dispatch_io_bxxFault_1), + .io_in_fault_2_jal (_dispatch_io_jalFault_2), + .io_in_fault_2_jalr (_dispatch_io_jalrFault_2), + .io_in_fault_2_bxx (_dispatch_io_bxxFault_2), + .io_in_fault_3_jal (_dispatch_io_jalFault_3), + .io_in_fault_3_jalr (_dispatch_io_jalrFault_3), + .io_in_fault_3_bxx (_dispatch_io_bxxFault_3), + .io_in_pc_0_pc (_fetch_io_inst_lanes_0_bits_addr), + .io_in_pc_1_pc (_fetch_io_inst_lanes_1_bits_addr), + .io_in_pc_2_pc (_fetch_io_inst_lanes_2_bits_addr), + .io_in_pc_3_pc (_fetch_io_inst_lanes_3_bits_addr), + .io_in_memory_fault_valid + (io_ibus_fault_valid ? io_ibus_fault_valid : _lsu_io_fault_valid), + .io_in_memory_fault_bits_write + (~io_ibus_fault_valid & _lsu_io_fault_valid & _lsu_io_fault_bits_write), + .io_in_memory_fault_bits_addr + (io_ibus_fault_valid | ~_lsu_io_fault_valid ? 32'h0 : _lsu_io_fault_bits_addr), + .io_in_memory_fault_bits_epc + (io_ibus_fault_valid + ? io_ibus_fault_bits_epc + : _lsu_io_fault_valid ? _lsu_io_fault_bits_epc : 32'h0), + .io_in_ibus_fault (io_ibus_fault_valid), + .io_in_undef_0_inst (_fetch_io_inst_lanes_0_bits_inst), + .io_in_undef_1_inst (_fetch_io_inst_lanes_1_bits_inst), + .io_in_undef_2_inst (_fetch_io_inst_lanes_2_bits_inst), + .io_in_undef_3_inst (_fetch_io_inst_lanes_3_bits_inst), + .io_in_jal_0_target (_dispatch_io_bruTarget_0), + .io_in_jal_1_target (_dispatch_io_bruTarget_1), + .io_in_jal_2_target (_dispatch_io_bruTarget_2), + .io_in_jal_3_target (_dispatch_io_bruTarget_3), + .io_in_jalr_0_target (_regfile_io_target_0_data), + .io_in_jalr_1_target (_regfile_io_target_1_data), + .io_in_jalr_2_target (_regfile_io_target_2_data), + .io_in_jalr_3_target (_regfile_io_target_3_data), + .io_out_valid (_fault_manager_io_out_valid), + .io_out_bits_mepc (_fault_manager_io_out_bits_mepc), + .io_out_bits_mtval (_fault_manager_io_out_bits_mtval), + .io_out_bits_mcause (_fault_manager_io_out_bits_mcause) + ); + FloatCore floatCore ( + .clock (clock), + .reset (reset), + .io_inst_ready (_floatCore_io_inst_ready), + .io_inst_valid (_dispatch_io_float_valid), + .io_inst_bits_opcode (_dispatch_io_float_bits_opcode), + .io_inst_bits_funct5 (_dispatch_io_float_bits_funct5), + .io_inst_bits_rs3 (_dispatch_io_float_bits_rs3), + .io_inst_bits_rs2 (_dispatch_io_float_bits_rs2), + .io_inst_bits_rs1 (_dispatch_io_float_bits_rs1), + .io_inst_bits_rm (_dispatch_io_float_bits_rm), + .io_inst_bits_inst (_dispatch_io_float_bits_inst), + .io_inst_bits_pc (_dispatch_io_float_bits_pc), + .io_inst_bits_scalar_rd (_dispatch_io_float_bits_scalar_rd), + .io_inst_bits_scalar_rs1 (_dispatch_io_float_bits_scalar_rs1), + .io_inst_bits_rd (_dispatch_io_float_bits_rd), + .io_inst_bits_uses_rs3 (_dispatch_io_float_bits_uses_rs3), + .io_inst_bits_uses_rs2 (_dispatch_io_float_bits_uses_rs2), + .io_read_ports_0_valid (_floatCore_io_read_ports_0_valid), + .io_read_ports_0_addr (_floatCore_io_read_ports_0_addr), + .io_read_ports_0_data_mantissa (_fRegfile_io_read_ports_0_data_mantissa), + .io_read_ports_0_data_exponent (_fRegfile_io_read_ports_0_data_exponent), + .io_read_ports_0_data_sign (_fRegfile_io_read_ports_0_data_sign), + .io_read_ports_1_valid (_floatCore_io_read_ports_1_valid), + .io_read_ports_1_addr (_floatCore_io_read_ports_1_addr), + .io_read_ports_1_data_mantissa (_fRegfile_io_read_ports_1_data_mantissa), + .io_read_ports_1_data_exponent (_fRegfile_io_read_ports_1_data_exponent), + .io_read_ports_1_data_sign (_fRegfile_io_read_ports_1_data_sign), + .io_read_ports_2_valid (_floatCore_io_read_ports_2_valid), + .io_read_ports_2_addr (_floatCore_io_read_ports_2_addr), + .io_read_ports_2_data_mantissa (_fRegfile_io_read_ports_2_data_mantissa), + .io_read_ports_2_data_exponent (_fRegfile_io_read_ports_2_data_exponent), + .io_read_ports_2_data_sign (_fRegfile_io_read_ports_2_data_sign), + .io_write_ports_0_valid (_floatCore_io_write_ports_0_valid), + .io_write_ports_0_addr (_floatCore_io_write_ports_0_addr), + .io_write_ports_0_data_mantissa (_floatCore_io_write_ports_0_data_mantissa), + .io_write_ports_0_data_exponent (_floatCore_io_write_ports_0_data_exponent), + .io_write_ports_0_data_sign (_floatCore_io_write_ports_0_data_sign), + .io_write_ports_1_valid (_floatCore_io_write_ports_1_valid), + .io_write_ports_1_addr (_floatCore_io_write_ports_1_addr), + .io_write_ports_1_data_mantissa (_floatCore_io_write_ports_1_data_mantissa), + .io_write_ports_1_data_exponent (_floatCore_io_write_ports_1_data_exponent), + .io_write_ports_1_data_sign (_floatCore_io_write_ports_1_data_sign), + .io_rs1_data (_regfile_io_readData_0_data), + .io_scalar_rd_ready (_arb_io_in_2_ready), + .io_scalar_rd_valid (_floatCore_io_scalar_rd_valid), + .io_scalar_rd_bits_addr (_floatCore_io_scalar_rd_bits_addr), + .io_scalar_rd_bits_data (_floatCore_io_scalar_rd_bits_data), + .io_csr_in_fflags_valid (_floatCore_io_csr_in_fflags_valid), + .io_csr_in_fflags_bits (_floatCore_io_csr_in_fflags_bits), + .io_csr_out_frm (_csr_io_float_out_frm), + .io_lsu_rd_valid (_lsu_io_rd_flt_valid), + .io_lsu_rd_bits_addr (_lsu_io_rd_flt_bits_addr), + .io_lsu_rd_bits_data (_lsu_io_rd_flt_bits_data) + ); + FRegfile fRegfile ( + .clock (clock), + .reset (reset), + .io_read_ports_0_valid (_floatCore_io_read_ports_0_valid), + .io_read_ports_0_addr (_floatCore_io_read_ports_0_addr), + .io_read_ports_0_data_mantissa (_fRegfile_io_read_ports_0_data_mantissa), + .io_read_ports_0_data_exponent (_fRegfile_io_read_ports_0_data_exponent), + .io_read_ports_0_data_sign (_fRegfile_io_read_ports_0_data_sign), + .io_read_ports_1_valid (_floatCore_io_read_ports_1_valid), + .io_read_ports_1_addr (_floatCore_io_read_ports_1_addr), + .io_read_ports_1_data_mantissa (_fRegfile_io_read_ports_1_data_mantissa), + .io_read_ports_1_data_exponent (_fRegfile_io_read_ports_1_data_exponent), + .io_read_ports_1_data_sign (_fRegfile_io_read_ports_1_data_sign), + .io_read_ports_2_valid (_floatCore_io_read_ports_2_valid), + .io_read_ports_2_addr (_floatCore_io_read_ports_2_addr), + .io_read_ports_2_data_mantissa (_fRegfile_io_read_ports_2_data_mantissa), + .io_read_ports_2_data_exponent (_fRegfile_io_read_ports_2_data_exponent), + .io_read_ports_2_data_sign (_fRegfile_io_read_ports_2_data_sign), + .io_write_ports_0_valid (_floatCore_io_write_ports_0_valid), + .io_write_ports_0_addr (_floatCore_io_write_ports_0_addr), + .io_write_ports_0_data_mantissa (_floatCore_io_write_ports_0_data_mantissa), + .io_write_ports_0_data_exponent (_floatCore_io_write_ports_0_data_exponent), + .io_write_ports_0_data_sign (_floatCore_io_write_ports_0_data_sign), + .io_write_ports_1_valid (_floatCore_io_write_ports_1_valid), + .io_write_ports_1_addr (_floatCore_io_write_ports_1_addr), + .io_write_ports_1_data_mantissa (_floatCore_io_write_ports_1_data_mantissa), + .io_write_ports_1_data_exponent (_floatCore_io_write_ports_1_data_exponent), + .io_write_ports_1_data_sign (_floatCore_io_write_ports_1_data_sign), + .io_scoreboard_set + (_dispatch_io_rdMark_flt_valid ? 32'h1 << _dispatch_io_rdMark_flt_addr : 32'h0), + .io_scoreboard (_fRegfile_io_scoreboard), + .io_busPort_data_0 (_fRegfile_io_busPort_data_0), + .io_busPortAddr (_dispatch_io_fbusPortAddr) + ); + Arbiter3_RegfileWriteDataIO arb ( + .io_in_0_valid (_mlu_io_rd_valid), + .io_in_0_bits_addr (_mlu_io_rd_bits_addr), + .io_in_0_bits_data (_mlu_io_rd_bits_data), + .io_in_1_ready (_arb_io_in_1_ready), + .io_in_1_valid (_dvu_io_rd_valid), + .io_in_1_bits_addr (_dvu_io_rd_bits_addr), + .io_in_1_bits_data (_dvu_io_rd_bits_data), + .io_in_2_ready (_arb_io_in_2_ready), + .io_in_2_valid (_floatCore_io_scalar_rd_valid), + .io_in_2_bits_addr (_floatCore_io_scalar_rd_bits_addr), + .io_in_2_bits_data (_floatCore_io_scalar_rd_bits_data), + .io_out_valid (_arb_io_out_valid), + .io_out_bits_addr (_arb_io_out_bits_addr), + .io_out_bits_data (_arb_io_out_bits_data) + ); + assign io_csr_out_value_4 = _csr_io_csr_out_value_4; + assign io_halted = _csr_io_halted; + assign io_wfi = _csr_io_wfi; + assign io_ibus_valid = _lsu_io_ibus_valid ? _lsu_io_ibus_valid : _fetch_io_ibus_valid; + assign io_ibus_addr = _lsu_io_ibus_valid ? _lsu_io_ibus_addr : _fetch_io_ibus_addr; + assign io_dbus_valid = _lsu_io_dbus_valid; + assign io_dbus_write = _lsu_io_dbus_write; + assign io_dbus_addr = _lsu_io_dbus_addr; + assign io_dbus_wdata = _lsu_io_dbus_wdata; + assign io_slog_valid = slogValid; + assign io_slog_addr = {3'h0, slogValid ? slogAddr : 2'h0}; + assign io_slog_data = slogValid ? _regfile_io_readData_0_data : 32'h0; + assign io_debug_en = + {~(_bru_1_io_taken_valid | _debugBrch_T_1), + ~_debugBrch_T_1, + ~_bru_3_io_taken_valid, + 1'h1} & debugEn; + assign io_debug_addr_0 = debugAddr_0; + assign io_debug_addr_1 = debugAddr_1; + assign io_debug_addr_2 = debugAddr_2; + assign io_debug_addr_3 = debugAddr_3; + assign io_debug_inst_0 = debugInst_0; + assign io_debug_inst_1 = debugInst_1; + assign io_debug_inst_2 = debugInst_2; + assign io_debug_inst_3 = debugInst_3; + assign io_debug_cycles = _csr_io_csr_out_value_4; + assign io_debug_dbus_valid = _lsu_io_dbus_valid; + assign io_debug_dbus_bits_addr = _lsu_io_dbus_addr; + assign io_debug_dbus_bits_wdata = _lsu_io_dbus_wdata; + assign io_debug_dbus_bits_write = _lsu_io_dbus_write; + assign io_debug_dispatch_0_instFire = + _dispatch_io_inst_0_ready & _fetch_io_inst_lanes_0_valid; + assign io_debug_dispatch_0_instAddr = _fetch_io_inst_lanes_0_bits_addr; + assign io_debug_dispatch_0_instInst = _fetch_io_inst_lanes_0_bits_inst; + assign io_debug_dispatch_1_instFire = + _dispatch_io_inst_1_ready & _fetch_io_inst_lanes_1_valid; + assign io_debug_dispatch_1_instAddr = _fetch_io_inst_lanes_1_bits_addr; + assign io_debug_dispatch_1_instInst = _fetch_io_inst_lanes_1_bits_inst; + assign io_debug_dispatch_2_instFire = + _dispatch_io_inst_2_ready & _fetch_io_inst_lanes_2_valid; + assign io_debug_dispatch_2_instAddr = _fetch_io_inst_lanes_2_bits_addr; + assign io_debug_dispatch_2_instInst = _fetch_io_inst_lanes_2_bits_inst; + assign io_debug_dispatch_3_instFire = + _dispatch_io_inst_3_ready & _fetch_io_inst_lanes_3_valid; + assign io_debug_dispatch_3_instAddr = _fetch_io_inst_lanes_3_bits_addr; + assign io_debug_dispatch_3_instInst = _fetch_io_inst_lanes_3_bits_inst; + assign io_debug_regfile_writeAddr_0_valid = _dispatch_io_rdMark_0_valid; + assign io_debug_regfile_writeAddr_0_bits = _dispatch_io_rdMark_0_addr; + assign io_debug_regfile_writeAddr_1_valid = _dispatch_io_rdMark_1_valid; + assign io_debug_regfile_writeAddr_1_bits = _dispatch_io_rdMark_1_addr; + assign io_debug_regfile_writeAddr_2_valid = _dispatch_io_rdMark_2_valid; + assign io_debug_regfile_writeAddr_2_bits = _dispatch_io_rdMark_2_addr; + assign io_debug_regfile_writeAddr_3_valid = _dispatch_io_rdMark_3_valid; + assign io_debug_regfile_writeAddr_3_bits = _dispatch_io_rdMark_3_addr; + assign io_debug_regfile_writeData_0_valid = regfile_io_writeData_0_valid; + assign io_debug_regfile_writeData_0_bits_addr = regfile_io_writeData_0_bits_addr; + assign io_debug_regfile_writeData_0_bits_data = regfile_io_writeData_0_bits_data; + assign io_debug_regfile_writeData_1_valid = regfile_io_writeData_1_valid; + assign io_debug_regfile_writeData_1_bits_addr = regfile_io_writeData_1_bits_addr; + assign io_debug_regfile_writeData_1_bits_data = regfile_io_writeData_1_bits_data; + assign io_debug_regfile_writeData_2_valid = regfile_io_writeData_2_valid; + assign io_debug_regfile_writeData_2_bits_addr = regfile_io_writeData_2_bits_addr; + assign io_debug_regfile_writeData_2_bits_data = regfile_io_writeData_2_bits_data; + assign io_debug_regfile_writeData_3_valid = regfile_io_writeData_3_valid; + assign io_debug_regfile_writeData_3_bits_addr = regfile_io_writeData_3_bits_addr; + assign io_debug_regfile_writeData_3_bits_data = regfile_io_writeData_3_bits_data; + assign io_debug_regfile_writeData_4_valid = _arb_io_out_valid; + assign io_debug_regfile_writeData_4_bits_addr = _arb_io_out_bits_addr; + assign io_debug_regfile_writeData_4_bits_data = _arb_io_out_bits_data; + assign io_debug_regfile_writeData_5_valid = _lsu_io_rd_valid; + assign io_debug_regfile_writeData_5_bits_addr = _lsu_io_rd_bits_addr; + assign io_debug_regfile_writeData_5_bits_data = _lsu_io_rd_bits_data; + assign io_debug_float_writeAddr_valid = _dispatch_io_rdMark_flt_valid; + assign io_debug_float_writeAddr_bits = _dispatch_io_rdMark_flt_addr; + assign io_debug_float_writeData_0_valid = _floatCore_io_write_ports_0_valid; + assign io_debug_float_writeData_0_bits_addr = {27'h0, _floatCore_io_write_ports_0_addr}; + assign io_debug_float_writeData_0_bits_data = + {_floatCore_io_write_ports_0_data_sign, + _floatCore_io_write_ports_0_data_exponent, + _floatCore_io_write_ports_0_data_mantissa}; + assign io_debug_float_writeData_1_valid = _floatCore_io_write_ports_1_valid; + assign io_debug_float_writeData_1_bits_addr = {27'h0, _floatCore_io_write_ports_1_addr}; + assign io_debug_float_writeData_1_bits_data = + {_floatCore_io_write_ports_1_data_sign, + _floatCore_io_write_ports_1_data_exponent, + _floatCore_io_write_ports_1_data_mantissa}; +endmodule + +module CoreMini( + input clock, + reset, + input [31:0] io_csr_in_value_0, + output [31:0] io_csr_out_value_0, + io_csr_out_value_1, + io_csr_out_value_2, + io_csr_out_value_3, + io_csr_out_value_4, + io_csr_out_value_5, + io_csr_out_value_6, + io_csr_out_value_7, + output io_halted, + io_fault, + io_wfi, + input io_irq, + output io_ibus_valid, + output [31:0] io_ibus_addr, + input [127:0] io_ibus_rdata, + input io_ibus_fault_valid, + input [31:0] io_ibus_fault_bits_epc, + output io_dbus_valid, + io_dbus_write, + output [31:0] io_dbus_addr, + output [127:0] io_dbus_wdata, + output [15:0] io_dbus_wmask, + input [127:0] io_dbus_rdata, + output io_ebus_dbus_valid, + input io_ebus_dbus_ready, + output io_ebus_dbus_write, + output [31:0] io_ebus_dbus_pc, + io_ebus_dbus_addr, + output [4:0] io_ebus_dbus_size, + output [127:0] io_ebus_dbus_wdata, + input [127:0] io_ebus_dbus_rdata, + input io_ebus_fault_valid, + io_ebus_fault_bits_write, + input [31:0] io_ebus_fault_bits_addr, + io_ebus_fault_bits_epc, + output io_slog_valid, + output [4:0] io_slog_addr, + output [31:0] io_slog_data, + output [3:0] io_debug_en, + output [31:0] io_debug_addr_0, + io_debug_addr_1, + io_debug_addr_2, + io_debug_addr_3, + io_debug_inst_0, + io_debug_inst_1, + io_debug_inst_2, + io_debug_inst_3, + io_debug_cycles, + output io_debug_dbus_valid, + output [31:0] io_debug_dbus_bits_addr, + output [127:0] io_debug_dbus_bits_wdata, + output io_debug_dbus_bits_write, + io_debug_dispatch_0_instFire, + output [31:0] io_debug_dispatch_0_instAddr, + io_debug_dispatch_0_instInst, + output io_debug_dispatch_1_instFire, + output [31:0] io_debug_dispatch_1_instAddr, + io_debug_dispatch_1_instInst, + output io_debug_dispatch_2_instFire, + output [31:0] io_debug_dispatch_2_instAddr, + io_debug_dispatch_2_instInst, + output io_debug_dispatch_3_instFire, + output [31:0] io_debug_dispatch_3_instAddr, + io_debug_dispatch_3_instInst, + output io_debug_regfile_writeAddr_0_valid, + output [4:0] io_debug_regfile_writeAddr_0_bits, + output io_debug_regfile_writeAddr_1_valid, + output [4:0] io_debug_regfile_writeAddr_1_bits, + output io_debug_regfile_writeAddr_2_valid, + output [4:0] io_debug_regfile_writeAddr_2_bits, + output io_debug_regfile_writeAddr_3_valid, + output [4:0] io_debug_regfile_writeAddr_3_bits, + output io_debug_regfile_writeData_0_valid, + output [4:0] io_debug_regfile_writeData_0_bits_addr, + output [31:0] io_debug_regfile_writeData_0_bits_data, + output io_debug_regfile_writeData_1_valid, + output [4:0] io_debug_regfile_writeData_1_bits_addr, + output [31:0] io_debug_regfile_writeData_1_bits_data, + output io_debug_regfile_writeData_2_valid, + output [4:0] io_debug_regfile_writeData_2_bits_addr, + output [31:0] io_debug_regfile_writeData_2_bits_data, + output io_debug_regfile_writeData_3_valid, + output [4:0] io_debug_regfile_writeData_3_bits_addr, + output [31:0] io_debug_regfile_writeData_3_bits_data, + output io_debug_regfile_writeData_4_valid, + output [4:0] io_debug_regfile_writeData_4_bits_addr, + output [31:0] io_debug_regfile_writeData_4_bits_data, + output io_debug_regfile_writeData_5_valid, + output [4:0] io_debug_regfile_writeData_5_bits_addr, + output [31:0] io_debug_regfile_writeData_5_bits_data, + output io_debug_float_writeAddr_valid, + output [4:0] io_debug_float_writeAddr_bits, + output io_debug_float_writeData_0_valid, + output [31:0] io_debug_float_writeData_0_bits_addr, + io_debug_float_writeData_0_bits_data, + output io_debug_float_writeData_1_valid, + output [31:0] io_debug_float_writeData_1_bits_addr, + io_debug_float_writeData_1_bits_data +); + + SCore score ( + .clock (clock), + .reset (reset), + .io_csr_in_value_0 (io_csr_in_value_0), + .io_csr_out_value_0 (io_csr_out_value_0), + .io_csr_out_value_1 (io_csr_out_value_1), + .io_csr_out_value_2 (io_csr_out_value_2), + .io_csr_out_value_3 (io_csr_out_value_3), + .io_csr_out_value_4 (io_csr_out_value_4), + .io_csr_out_value_5 (io_csr_out_value_5), + .io_csr_out_value_6 (io_csr_out_value_6), + .io_csr_out_value_7 (io_csr_out_value_7), + .io_halted (io_halted), + .io_fault (io_fault), + .io_wfi (io_wfi), + .io_irq (io_irq), + .io_ibus_valid (io_ibus_valid), + .io_ibus_addr (io_ibus_addr), + .io_ibus_rdata (io_ibus_rdata), + .io_ibus_fault_valid (io_ibus_fault_valid), + .io_ibus_fault_bits_epc (io_ibus_fault_bits_epc), + .io_dbus_valid (io_dbus_valid), + .io_dbus_write (io_dbus_write), + .io_dbus_addr (io_dbus_addr), + .io_dbus_wdata (io_dbus_wdata), + .io_dbus_wmask (io_dbus_wmask), + .io_dbus_rdata (io_dbus_rdata), + .io_ebus_dbus_valid (io_ebus_dbus_valid), + .io_ebus_dbus_ready (io_ebus_dbus_ready), + .io_ebus_dbus_write (io_ebus_dbus_write), + .io_ebus_dbus_pc (io_ebus_dbus_pc), + .io_ebus_dbus_addr (io_ebus_dbus_addr), + .io_ebus_dbus_size (io_ebus_dbus_size), + .io_ebus_dbus_wdata (io_ebus_dbus_wdata), + .io_ebus_dbus_rdata (io_ebus_dbus_rdata), + .io_ebus_fault_valid (io_ebus_fault_valid), + .io_ebus_fault_bits_write (io_ebus_fault_bits_write), + .io_ebus_fault_bits_addr (io_ebus_fault_bits_addr), + .io_ebus_fault_bits_epc (io_ebus_fault_bits_epc), + .io_slog_valid (io_slog_valid), + .io_slog_addr (io_slog_addr), + .io_slog_data (io_slog_data), + .io_debug_en (io_debug_en), + .io_debug_addr_0 (io_debug_addr_0), + .io_debug_addr_1 (io_debug_addr_1), + .io_debug_addr_2 (io_debug_addr_2), + .io_debug_addr_3 (io_debug_addr_3), + .io_debug_inst_0 (io_debug_inst_0), + .io_debug_inst_1 (io_debug_inst_1), + .io_debug_inst_2 (io_debug_inst_2), + .io_debug_inst_3 (io_debug_inst_3), + .io_debug_cycles (io_debug_cycles), + .io_debug_dbus_valid (io_debug_dbus_valid), + .io_debug_dbus_bits_addr (io_debug_dbus_bits_addr), + .io_debug_dbus_bits_wdata (io_debug_dbus_bits_wdata), + .io_debug_dbus_bits_write (io_debug_dbus_bits_write), + .io_debug_dispatch_0_instFire (io_debug_dispatch_0_instFire), + .io_debug_dispatch_0_instAddr (io_debug_dispatch_0_instAddr), + .io_debug_dispatch_0_instInst (io_debug_dispatch_0_instInst), + .io_debug_dispatch_1_instFire (io_debug_dispatch_1_instFire), + .io_debug_dispatch_1_instAddr (io_debug_dispatch_1_instAddr), + .io_debug_dispatch_1_instInst (io_debug_dispatch_1_instInst), + .io_debug_dispatch_2_instFire (io_debug_dispatch_2_instFire), + .io_debug_dispatch_2_instAddr (io_debug_dispatch_2_instAddr), + .io_debug_dispatch_2_instInst (io_debug_dispatch_2_instInst), + .io_debug_dispatch_3_instFire (io_debug_dispatch_3_instFire), + .io_debug_dispatch_3_instAddr (io_debug_dispatch_3_instAddr), + .io_debug_dispatch_3_instInst (io_debug_dispatch_3_instInst), + .io_debug_regfile_writeAddr_0_valid (io_debug_regfile_writeAddr_0_valid), + .io_debug_regfile_writeAddr_0_bits (io_debug_regfile_writeAddr_0_bits), + .io_debug_regfile_writeAddr_1_valid (io_debug_regfile_writeAddr_1_valid), + .io_debug_regfile_writeAddr_1_bits (io_debug_regfile_writeAddr_1_bits), + .io_debug_regfile_writeAddr_2_valid (io_debug_regfile_writeAddr_2_valid), + .io_debug_regfile_writeAddr_2_bits (io_debug_regfile_writeAddr_2_bits), + .io_debug_regfile_writeAddr_3_valid (io_debug_regfile_writeAddr_3_valid), + .io_debug_regfile_writeAddr_3_bits (io_debug_regfile_writeAddr_3_bits), + .io_debug_regfile_writeData_0_valid (io_debug_regfile_writeData_0_valid), + .io_debug_regfile_writeData_0_bits_addr (io_debug_regfile_writeData_0_bits_addr), + .io_debug_regfile_writeData_0_bits_data (io_debug_regfile_writeData_0_bits_data), + .io_debug_regfile_writeData_1_valid (io_debug_regfile_writeData_1_valid), + .io_debug_regfile_writeData_1_bits_addr (io_debug_regfile_writeData_1_bits_addr), + .io_debug_regfile_writeData_1_bits_data (io_debug_regfile_writeData_1_bits_data), + .io_debug_regfile_writeData_2_valid (io_debug_regfile_writeData_2_valid), + .io_debug_regfile_writeData_2_bits_addr (io_debug_regfile_writeData_2_bits_addr), + .io_debug_regfile_writeData_2_bits_data (io_debug_regfile_writeData_2_bits_data), + .io_debug_regfile_writeData_3_valid (io_debug_regfile_writeData_3_valid), + .io_debug_regfile_writeData_3_bits_addr (io_debug_regfile_writeData_3_bits_addr), + .io_debug_regfile_writeData_3_bits_data (io_debug_regfile_writeData_3_bits_data), + .io_debug_regfile_writeData_4_valid (io_debug_regfile_writeData_4_valid), + .io_debug_regfile_writeData_4_bits_addr (io_debug_regfile_writeData_4_bits_addr), + .io_debug_regfile_writeData_4_bits_data (io_debug_regfile_writeData_4_bits_data), + .io_debug_regfile_writeData_5_valid (io_debug_regfile_writeData_5_valid), + .io_debug_regfile_writeData_5_bits_addr (io_debug_regfile_writeData_5_bits_addr), + .io_debug_regfile_writeData_5_bits_data (io_debug_regfile_writeData_5_bits_data), + .io_debug_float_writeAddr_valid (io_debug_float_writeAddr_valid), + .io_debug_float_writeAddr_bits (io_debug_float_writeAddr_bits), + .io_debug_float_writeData_0_valid (io_debug_float_writeData_0_valid), + .io_debug_float_writeData_0_bits_addr (io_debug_float_writeData_0_bits_addr), + .io_debug_float_writeData_0_bits_data (io_debug_float_writeData_0_bits_data), + .io_debug_float_writeData_1_valid (io_debug_float_writeData_1_valid), + .io_debug_float_writeData_1_bits_addr (io_debug_float_writeData_1_bits_addr), + .io_debug_float_writeData_1_bits_data (io_debug_float_writeData_1_bits_data) + ); +endmodule + +module SRAM_512x128( + input clock, + input [8:0] io_addr, + input io_enable, + io_write, + input [127:0] io_wdata, + input [15:0] io_wmask, + output [127:0] io_rdata +); + + Sram_512x128 sramModules_0 ( + .clock (clock), + .enable (io_enable), + .write (io_write), + .addr (io_addr), + .wdata (io_wdata), + .wmask (io_wmask), + .rdata (io_rdata) + ); +endmodule + +module TCM128( + input clock, + input [8:0] io_addr, + input io_enable, + io_write, + input [7:0] io_wdata_0, + io_wdata_1, + io_wdata_2, + io_wdata_3, + io_wdata_4, + io_wdata_5, + io_wdata_6, + io_wdata_7, + io_wdata_8, + io_wdata_9, + io_wdata_10, + io_wdata_11, + io_wdata_12, + io_wdata_13, + io_wdata_14, + io_wdata_15, + input io_wmask_0, + io_wmask_1, + io_wmask_2, + io_wmask_3, + io_wmask_4, + io_wmask_5, + io_wmask_6, + io_wmask_7, + io_wmask_8, + io_wmask_9, + io_wmask_10, + io_wmask_11, + io_wmask_12, + io_wmask_13, + io_wmask_14, + io_wmask_15, + output [7:0] io_rdata_0, + io_rdata_1, + io_rdata_2, + io_rdata_3, + io_rdata_4, + io_rdata_5, + io_rdata_6, + io_rdata_7, + io_rdata_8, + io_rdata_9, + io_rdata_10, + io_rdata_11, + io_rdata_12, + io_rdata_13, + io_rdata_14, + io_rdata_15 +); + + wire [127:0] _sram_io_rdata; + SRAM_512x128 sram ( + .clock (clock), + .io_addr (io_addr), + .io_enable (io_enable), + .io_write (io_write), + .io_wdata + ({io_wdata_15, + io_wdata_14, + io_wdata_13, + io_wdata_12, + io_wdata_11, + io_wdata_10, + io_wdata_9, + io_wdata_8, + io_wdata_7, + io_wdata_6, + io_wdata_5, + io_wdata_4, + io_wdata_3, + io_wdata_2, + io_wdata_1, + io_wdata_0}), + .io_wmask + ({io_wmask_15, + io_wmask_14, + io_wmask_13, + io_wmask_12, + io_wmask_11, + io_wmask_10, + io_wmask_9, + io_wmask_8, + io_wmask_7, + io_wmask_6, + io_wmask_5, + io_wmask_4, + io_wmask_3, + io_wmask_2, + io_wmask_1, + io_wmask_0}), + .io_rdata (_sram_io_rdata) + ); + assign io_rdata_0 = _sram_io_rdata[127:120]; + assign io_rdata_1 = _sram_io_rdata[119:112]; + assign io_rdata_2 = _sram_io_rdata[111:104]; + assign io_rdata_3 = _sram_io_rdata[103:96]; + assign io_rdata_4 = _sram_io_rdata[95:88]; + assign io_rdata_5 = _sram_io_rdata[87:80]; + assign io_rdata_6 = _sram_io_rdata[79:72]; + assign io_rdata_7 = _sram_io_rdata[71:64]; + assign io_rdata_8 = _sram_io_rdata[63:56]; + assign io_rdata_9 = _sram_io_rdata[55:48]; + assign io_rdata_10 = _sram_io_rdata[47:40]; + assign io_rdata_11 = _sram_io_rdata[39:32]; + assign io_rdata_12 = _sram_io_rdata[31:24]; + assign io_rdata_13 = _sram_io_rdata[23:16]; + assign io_rdata_14 = _sram_io_rdata[15:8]; + assign io_rdata_15 = _sram_io_rdata[7:0]; +endmodule + +module SRAM( + input clock, + reset, + io_fabric_readDataAddr_valid, + input [31:0] io_fabric_readDataAddr_bits, + output io_fabric_readData_valid, + output [127:0] io_fabric_readData_bits, + input io_fabric_writeDataAddr_valid, + input [31:0] io_fabric_writeDataAddr_bits, + input [127:0] io_fabric_writeDataBits, + input [15:0] io_fabric_writeDataStrb, + output [8:0] io_sram_address, + output io_sram_enable, + io_sram_isWrite, + input [7:0] io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15, + output [7:0] io_sram_writeData_0, + io_sram_writeData_1, + io_sram_writeData_2, + io_sram_writeData_3, + io_sram_writeData_4, + io_sram_writeData_5, + io_sram_writeData_6, + io_sram_writeData_7, + io_sram_writeData_8, + io_sram_writeData_9, + io_sram_writeData_10, + io_sram_writeData_11, + io_sram_writeData_12, + io_sram_writeData_13, + io_sram_writeData_14, + io_sram_writeData_15, + output io_sram_mask_0, + io_sram_mask_1, + io_sram_mask_2, + io_sram_mask_3, + io_sram_mask_4, + io_sram_mask_5, + io_sram_mask_6, + io_sram_mask_7, + io_sram_mask_8, + io_sram_mask_9, + io_sram_mask_10, + io_sram_mask_11, + io_sram_mask_12, + io_sram_mask_13, + io_sram_mask_14, + io_sram_mask_15 +); + + reg readIssued; + always @(posedge clock or posedge reset) begin + if (reset) + readIssued <= 1'h0; + else + readIssued <= io_fabric_readDataAddr_valid & ~io_fabric_writeDataAddr_valid; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + readIssued = _RANDOM[/*Zero width*/ 1'b0][0]; + `endif // RANDOMIZE_REG_INIT + if (reset) + readIssued = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_fabric_readData_valid = readIssued; + assign io_fabric_readData_bits = + readIssued + ? {io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15} + : 128'h0; + assign io_sram_address = + io_fabric_writeDataAddr_valid + ? io_fabric_writeDataAddr_bits[12:4] + : io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[12:4] : 9'h0; + assign io_sram_enable = io_fabric_readDataAddr_valid | io_fabric_writeDataAddr_valid; + assign io_sram_isWrite = io_fabric_writeDataAddr_valid; + assign io_sram_writeData_0 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h0; + assign io_sram_writeData_1 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[15:8] : 8'h0; + assign io_sram_writeData_2 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[23:16] : 8'h0; + assign io_sram_writeData_3 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[31:24] : 8'h0; + assign io_sram_writeData_4 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[39:32] : 8'h0; + assign io_sram_writeData_5 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[47:40] : 8'h0; + assign io_sram_writeData_6 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[55:48] : 8'h0; + assign io_sram_writeData_7 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[63:56] : 8'h0; + assign io_sram_writeData_8 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[71:64] : 8'h0; + assign io_sram_writeData_9 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[79:72] : 8'h0; + assign io_sram_writeData_10 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[87:80] : 8'h0; + assign io_sram_writeData_11 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[95:88] : 8'h0; + assign io_sram_writeData_12 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[103:96] : 8'h0; + assign io_sram_writeData_13 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[111:104] : 8'h0; + assign io_sram_writeData_14 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[119:112] : 8'h0; + assign io_sram_writeData_15 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[127:120] : 8'h0; + assign io_sram_mask_0 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[0]; + assign io_sram_mask_1 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[1]; + assign io_sram_mask_2 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[2]; + assign io_sram_mask_3 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[3]; + assign io_sram_mask_4 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[4]; + assign io_sram_mask_5 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[5]; + assign io_sram_mask_6 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[6]; + assign io_sram_mask_7 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[7]; + assign io_sram_mask_8 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[8]; + assign io_sram_mask_9 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[9]; + assign io_sram_mask_10 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[10]; + assign io_sram_mask_11 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[11]; + assign io_sram_mask_12 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[12]; + assign io_sram_mask_13 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[13]; + assign io_sram_mask_14 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[14]; + assign io_sram_mask_15 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[15]; +endmodule + +module FabricArbiter( + input clock, + reset, + io_source_0_readDataAddr_valid, + input [31:0] io_source_0_readDataAddr_bits, + output [127:0] io_source_0_readData_bits, + input io_source_0_writeDataAddr_valid, + input [31:0] io_source_0_writeDataAddr_bits, + input [127:0] io_source_0_writeDataBits, + input [15:0] io_source_0_writeDataStrb, + input io_source_1_readDataAddr_valid, + input [31:0] io_source_1_readDataAddr_bits, + output io_source_1_readData_valid, + output [127:0] io_source_1_readData_bits, + input io_source_1_writeDataAddr_valid, + input [31:0] io_source_1_writeDataAddr_bits, + input [127:0] io_source_1_writeDataBits, + input [15:0] io_source_1_writeDataStrb, + output io_fabricBusy, + io_port_readDataAddr_valid, + output [31:0] io_port_readDataAddr_bits, + input io_port_readData_valid, + input [127:0] io_port_readData_bits, + output io_port_writeDataAddr_valid, + output [31:0] io_port_writeDataAddr_bits, + output [127:0] io_port_writeDataBits, + output [15:0] io_port_writeDataStrb +); + + wire source0Valid = io_source_0_readDataAddr_valid | io_source_0_writeDataAddr_valid; + assign io_source_0_readData_bits = io_port_readData_bits; + assign io_source_1_readData_valid = io_port_readData_valid; + assign io_source_1_readData_bits = io_port_readData_bits; + assign io_fabricBusy = source0Valid; + assign io_port_readDataAddr_valid = + source0Valid ? io_source_0_readDataAddr_valid : io_source_1_readDataAddr_valid; + assign io_port_readDataAddr_bits = + source0Valid ? io_source_0_readDataAddr_bits : io_source_1_readDataAddr_bits; + assign io_port_writeDataAddr_valid = + source0Valid ? io_source_0_writeDataAddr_valid : io_source_1_writeDataAddr_valid; + assign io_port_writeDataAddr_bits = + source0Valid ? io_source_0_writeDataAddr_bits : io_source_1_writeDataAddr_bits; + assign io_port_writeDataBits = + source0Valid ? io_source_0_writeDataBits : io_source_1_writeDataBits; + assign io_port_writeDataStrb = + source0Valid ? io_source_0_writeDataStrb : io_source_1_writeDataStrb; +endmodule + +module SRAM_2048x128( + input clock, + input [10:0] io_addr, + input io_enable, + io_write, + input [127:0] io_wdata, + input [15:0] io_wmask, + output [127:0] io_rdata +); + + Sram_2048x128 sramModules_0 ( + .clock (clock), + .enable (io_enable), + .write (io_write), + .addr (io_addr), + .wdata (io_wdata), + .wmask (io_wmask), + .rdata (io_rdata) + ); +endmodule + +module TCM128_1( + input clock, + input [10:0] io_addr, + input io_enable, + io_write, + input [7:0] io_wdata_0, + io_wdata_1, + io_wdata_2, + io_wdata_3, + io_wdata_4, + io_wdata_5, + io_wdata_6, + io_wdata_7, + io_wdata_8, + io_wdata_9, + io_wdata_10, + io_wdata_11, + io_wdata_12, + io_wdata_13, + io_wdata_14, + io_wdata_15, + input io_wmask_0, + io_wmask_1, + io_wmask_2, + io_wmask_3, + io_wmask_4, + io_wmask_5, + io_wmask_6, + io_wmask_7, + io_wmask_8, + io_wmask_9, + io_wmask_10, + io_wmask_11, + io_wmask_12, + io_wmask_13, + io_wmask_14, + io_wmask_15, + output [7:0] io_rdata_0, + io_rdata_1, + io_rdata_2, + io_rdata_3, + io_rdata_4, + io_rdata_5, + io_rdata_6, + io_rdata_7, + io_rdata_8, + io_rdata_9, + io_rdata_10, + io_rdata_11, + io_rdata_12, + io_rdata_13, + io_rdata_14, + io_rdata_15 +); + + wire [127:0] _sram_io_rdata; + SRAM_2048x128 sram ( + .clock (clock), + .io_addr (io_addr), + .io_enable (io_enable), + .io_write (io_write), + .io_wdata + ({io_wdata_15, + io_wdata_14, + io_wdata_13, + io_wdata_12, + io_wdata_11, + io_wdata_10, + io_wdata_9, + io_wdata_8, + io_wdata_7, + io_wdata_6, + io_wdata_5, + io_wdata_4, + io_wdata_3, + io_wdata_2, + io_wdata_1, + io_wdata_0}), + .io_wmask + ({io_wmask_15, + io_wmask_14, + io_wmask_13, + io_wmask_12, + io_wmask_11, + io_wmask_10, + io_wmask_9, + io_wmask_8, + io_wmask_7, + io_wmask_6, + io_wmask_5, + io_wmask_4, + io_wmask_3, + io_wmask_2, + io_wmask_1, + io_wmask_0}), + .io_rdata (_sram_io_rdata) + ); + assign io_rdata_0 = _sram_io_rdata[127:120]; + assign io_rdata_1 = _sram_io_rdata[119:112]; + assign io_rdata_2 = _sram_io_rdata[111:104]; + assign io_rdata_3 = _sram_io_rdata[103:96]; + assign io_rdata_4 = _sram_io_rdata[95:88]; + assign io_rdata_5 = _sram_io_rdata[87:80]; + assign io_rdata_6 = _sram_io_rdata[79:72]; + assign io_rdata_7 = _sram_io_rdata[71:64]; + assign io_rdata_8 = _sram_io_rdata[63:56]; + assign io_rdata_9 = _sram_io_rdata[55:48]; + assign io_rdata_10 = _sram_io_rdata[47:40]; + assign io_rdata_11 = _sram_io_rdata[39:32]; + assign io_rdata_12 = _sram_io_rdata[31:24]; + assign io_rdata_13 = _sram_io_rdata[23:16]; + assign io_rdata_14 = _sram_io_rdata[15:8]; + assign io_rdata_15 = _sram_io_rdata[7:0]; +endmodule + +module SRAM_1( + input clock, + reset, + io_fabric_readDataAddr_valid, + input [31:0] io_fabric_readDataAddr_bits, + output io_fabric_readData_valid, + output [127:0] io_fabric_readData_bits, + input io_fabric_writeDataAddr_valid, + input [31:0] io_fabric_writeDataAddr_bits, + input [127:0] io_fabric_writeDataBits, + input [15:0] io_fabric_writeDataStrb, + output [10:0] io_sram_address, + output io_sram_enable, + io_sram_isWrite, + input [7:0] io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15, + output [7:0] io_sram_writeData_0, + io_sram_writeData_1, + io_sram_writeData_2, + io_sram_writeData_3, + io_sram_writeData_4, + io_sram_writeData_5, + io_sram_writeData_6, + io_sram_writeData_7, + io_sram_writeData_8, + io_sram_writeData_9, + io_sram_writeData_10, + io_sram_writeData_11, + io_sram_writeData_12, + io_sram_writeData_13, + io_sram_writeData_14, + io_sram_writeData_15, + output io_sram_mask_0, + io_sram_mask_1, + io_sram_mask_2, + io_sram_mask_3, + io_sram_mask_4, + io_sram_mask_5, + io_sram_mask_6, + io_sram_mask_7, + io_sram_mask_8, + io_sram_mask_9, + io_sram_mask_10, + io_sram_mask_11, + io_sram_mask_12, + io_sram_mask_13, + io_sram_mask_14, + io_sram_mask_15 +); + + reg readIssued; + always @(posedge clock or posedge reset) begin + if (reset) + readIssued <= 1'h0; + else + readIssued <= io_fabric_readDataAddr_valid & ~io_fabric_writeDataAddr_valid; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + readIssued = _RANDOM[/*Zero width*/ 1'b0][0]; + `endif // RANDOMIZE_REG_INIT + if (reset) + readIssued = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_fabric_readData_valid = readIssued; + assign io_fabric_readData_bits = + readIssued + ? {io_sram_readData_0, + io_sram_readData_1, + io_sram_readData_2, + io_sram_readData_3, + io_sram_readData_4, + io_sram_readData_5, + io_sram_readData_6, + io_sram_readData_7, + io_sram_readData_8, + io_sram_readData_9, + io_sram_readData_10, + io_sram_readData_11, + io_sram_readData_12, + io_sram_readData_13, + io_sram_readData_14, + io_sram_readData_15} + : 128'h0; + assign io_sram_address = + io_fabric_writeDataAddr_valid + ? io_fabric_writeDataAddr_bits[14:4] + : io_fabric_readDataAddr_valid ? io_fabric_readDataAddr_bits[14:4] : 11'h0; + assign io_sram_enable = io_fabric_readDataAddr_valid | io_fabric_writeDataAddr_valid; + assign io_sram_isWrite = io_fabric_writeDataAddr_valid; + assign io_sram_writeData_0 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[7:0] : 8'h0; + assign io_sram_writeData_1 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[15:8] : 8'h0; + assign io_sram_writeData_2 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[23:16] : 8'h0; + assign io_sram_writeData_3 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[31:24] : 8'h0; + assign io_sram_writeData_4 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[39:32] : 8'h0; + assign io_sram_writeData_5 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[47:40] : 8'h0; + assign io_sram_writeData_6 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[55:48] : 8'h0; + assign io_sram_writeData_7 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[63:56] : 8'h0; + assign io_sram_writeData_8 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[71:64] : 8'h0; + assign io_sram_writeData_9 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[79:72] : 8'h0; + assign io_sram_writeData_10 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[87:80] : 8'h0; + assign io_sram_writeData_11 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[95:88] : 8'h0; + assign io_sram_writeData_12 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[103:96] : 8'h0; + assign io_sram_writeData_13 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[111:104] : 8'h0; + assign io_sram_writeData_14 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[119:112] : 8'h0; + assign io_sram_writeData_15 = + io_fabric_writeDataAddr_valid ? io_fabric_writeDataBits[127:120] : 8'h0; + assign io_sram_mask_0 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[0]; + assign io_sram_mask_1 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[1]; + assign io_sram_mask_2 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[2]; + assign io_sram_mask_3 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[3]; + assign io_sram_mask_4 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[4]; + assign io_sram_mask_5 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[5]; + assign io_sram_mask_6 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[6]; + assign io_sram_mask_7 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[7]; + assign io_sram_mask_8 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[8]; + assign io_sram_mask_9 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[9]; + assign io_sram_mask_10 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[10]; + assign io_sram_mask_11 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[11]; + assign io_sram_mask_12 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[12]; + assign io_sram_mask_13 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[13]; + assign io_sram_mask_14 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[14]; + assign io_sram_mask_15 = ~io_fabric_writeDataAddr_valid | io_fabric_writeDataStrb[15]; +endmodule + +module FabricMux( + input clock, + reset, + io_source_readDataAddr_valid, + input [31:0] io_source_readDataAddr_bits, + output io_source_readData_valid, + output [127:0] io_source_readData_bits, + input io_source_writeDataAddr_valid, + input [31:0] io_source_writeDataAddr_bits, + input [127:0] io_source_writeDataBits, + input [15:0] io_source_writeDataStrb, + output io_source_writeResp, + io_fabricBusy, + io_ports_0_readDataAddr_valid, + output [31:0] io_ports_0_readDataAddr_bits, + input io_ports_0_readData_valid, + input [127:0] io_ports_0_readData_bits, + output io_ports_0_writeDataAddr_valid, + output [31:0] io_ports_0_writeDataAddr_bits, + output [127:0] io_ports_0_writeDataBits, + output [15:0] io_ports_0_writeDataStrb, + output io_ports_1_readDataAddr_valid, + output [31:0] io_ports_1_readDataAddr_bits, + input io_ports_1_readData_valid, + input [127:0] io_ports_1_readData_bits, + output io_ports_1_writeDataAddr_valid, + output [31:0] io_ports_1_writeDataAddr_bits, + output [127:0] io_ports_1_writeDataBits, + output [15:0] io_ports_1_writeDataStrb, + output [31:0] io_ports_2_readDataAddr_bits, + input io_ports_2_readData_valid, + input [127:0] io_ports_2_readData_bits, + output io_ports_2_writeDataAddr_valid, + output [31:0] io_ports_2_writeDataAddr_bits, + output [127:0] io_ports_2_writeDataBits, + input io_ports_2_writeResp, + io_periBusy_0, + io_periBusy_1 +); + + wire sourceValid = io_source_readDataAddr_valid | io_source_writeDataAddr_valid; + wire [31:0] addr = + io_source_readDataAddr_valid + ? io_source_readDataAddr_bits + : io_source_writeDataAddr_valid ? io_source_writeDataAddr_bits : 32'h0; + wire _selected_T_5 = sourceValid & addr < 32'h2000; + wire _selected_T_11 = sourceValid & (|(addr[31:16])) & addr < 32'h18000; + wire _selected_T_18_valid = sourceValid & addr > 32'h2FFFF & addr < 32'h32000; + wire selected_valid = _selected_T_5 | _selected_T_11 | _selected_T_18_valid; + wire [1:0] selected_bits = + _selected_T_5 ? 2'h0 : _selected_T_11 ? 2'h1 : {_selected_T_18_valid, 1'h0}; + wire _io_fabricBusy_T = selected_bits == 2'h0; + wire portSelected_0 = selected_valid & _io_fabricBusy_T & ~io_periBusy_0; + wire _io_fabricBusy_T_2 = selected_bits == 2'h1; + wire portSelected_1 = selected_valid & _io_fabricBusy_T_2 & ~io_periBusy_1; + wire _portSelected_T_7 = selected_valid & selected_bits == 2'h2; + wire io_ports_0_readDataAddr_valid_0 = + portSelected_0 & io_source_readDataAddr_valid; + wire io_ports_1_readDataAddr_valid_0 = + portSelected_1 & io_source_readDataAddr_valid; + reg lastReadSelected_valid; + reg [1:0] lastReadSelected_bits; + wire _io_source_readData_T_1 = + lastReadSelected_valid & lastReadSelected_bits == 2'h0; + wire _io_source_readData_T_3 = + lastReadSelected_valid & lastReadSelected_bits == 2'h1; + wire _io_source_readData_T_5 = + lastReadSelected_valid & lastReadSelected_bits == 2'h2; + wire _lastReadSelected_T_3_valid = + _portSelected_T_7 & io_source_readDataAddr_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + lastReadSelected_valid <= 1'h0; + lastReadSelected_bits <= 2'h0; + end + else begin + lastReadSelected_valid <= + io_ports_0_readDataAddr_valid_0 | io_ports_1_readDataAddr_valid_0 + | _lastReadSelected_T_3_valid; + lastReadSelected_bits <= + io_ports_0_readDataAddr_valid_0 + ? 2'h0 + : io_ports_1_readDataAddr_valid_0 ? 2'h1 : {_lastReadSelected_T_3_valid, 1'h0}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + lastReadSelected_valid = _RANDOM[/*Zero width*/ 1'b0][0]; + lastReadSelected_bits = _RANDOM[/*Zero width*/ 1'b0][2:1]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + lastReadSelected_valid = 1'h0; + lastReadSelected_bits = 2'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_source_readData_valid = + _io_source_readData_T_1 + ? io_ports_0_readData_valid + : _io_source_readData_T_3 + ? io_ports_1_readData_valid + : _io_source_readData_T_5 & io_ports_2_readData_valid; + assign io_source_readData_bits = + _io_source_readData_T_1 + ? io_ports_0_readData_bits + : _io_source_readData_T_3 + ? io_ports_1_readData_bits + : _io_source_readData_T_5 ? io_ports_2_readData_bits : 128'h0; + assign io_source_writeResp = + portSelected_0 | portSelected_1 | _portSelected_T_7 & io_ports_2_writeResp; + assign io_fabricBusy = + selected_valid & _io_fabricBusy_T + ? io_periBusy_0 + : selected_valid & _io_fabricBusy_T_2 & io_periBusy_1; + assign io_ports_0_readDataAddr_valid = io_ports_0_readDataAddr_valid_0; + assign io_ports_0_readDataAddr_bits = + portSelected_0 ? io_source_readDataAddr_bits : 32'h0; + assign io_ports_0_writeDataAddr_valid = portSelected_0 & io_source_writeDataAddr_valid; + assign io_ports_0_writeDataAddr_bits = + portSelected_0 ? io_source_writeDataAddr_bits : 32'h0; + assign io_ports_0_writeDataBits = portSelected_0 ? io_source_writeDataBits : 128'h0; + assign io_ports_0_writeDataStrb = portSelected_0 ? io_source_writeDataStrb : 16'h0; + assign io_ports_1_readDataAddr_valid = io_ports_1_readDataAddr_valid_0; + assign io_ports_1_readDataAddr_bits = + portSelected_1 ? io_source_readDataAddr_bits & 32'hFFFEFFFF : 32'h0; + assign io_ports_1_writeDataAddr_valid = portSelected_1 & io_source_writeDataAddr_valid; + assign io_ports_1_writeDataAddr_bits = + portSelected_1 ? io_source_writeDataAddr_bits & 32'hFFFEFFFF : 32'h0; + assign io_ports_1_writeDataBits = portSelected_1 ? io_source_writeDataBits : 128'h0; + assign io_ports_1_writeDataStrb = portSelected_1 ? io_source_writeDataStrb : 16'h0; + assign io_ports_2_readDataAddr_bits = + _portSelected_T_7 ? io_source_readDataAddr_bits & 32'hFFFCFFFF : 32'h0; + assign io_ports_2_writeDataAddr_valid = + _portSelected_T_7 & io_source_writeDataAddr_valid; + assign io_ports_2_writeDataAddr_bits = + _portSelected_T_7 ? io_source_writeDataAddr_bits & 32'hFFFCFFFF : 32'h0; + assign io_ports_2_writeDataBits = _portSelected_T_7 ? io_source_writeDataBits : 128'h0; +endmodule + +module CoralNPURRArbiter( + input clock, + reset, + output io_in_0_ready, + input io_in_0_valid, + input [31:0] io_in_0_bits_addr, + input [2:0] io_in_0_bits_prot, + input [5:0] io_in_0_bits_id, + input [7:0] io_in_0_bits_len, + input [2:0] io_in_0_bits_size, + input [1:0] io_in_0_bits_burst, + input io_in_0_bits_lock, + input [3:0] io_in_0_bits_cache, + io_in_0_bits_qos, + io_in_0_bits_region, + output io_in_1_ready, + input io_in_1_valid, + input [31:0] io_in_1_bits_addr, + input [2:0] io_in_1_bits_prot, + input [5:0] io_in_1_bits_id, + input [7:0] io_in_1_bits_len, + input [2:0] io_in_1_bits_size, + input [1:0] io_in_1_bits_burst, + input io_in_1_bits_lock, + input [3:0] io_in_1_bits_cache, + io_in_1_bits_qos, + io_in_1_bits_region, + input io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_addr, + output [2:0] io_out_bits_prot, + output [5:0] io_out_bits_id, + output [7:0] io_out_bits_len, + output [2:0] io_out_bits_size, + output [1:0] io_out_bits_burst, + output io_out_bits_lock, + output [3:0] io_out_bits_cache, + io_out_bits_qos, + io_out_bits_region, + output io_chosen +); + + wire io_chosen_choice; + wire io_out_valid_0 = io_chosen_choice ? io_in_1_valid : io_in_0_valid; + reg ctrl_validMask_grantMask_lastGrant; + wire ctrl_validMask_1 = io_in_1_valid & ~ctrl_validMask_grantMask_lastGrant; + assign io_chosen_choice = ctrl_validMask_1 | ~io_in_0_valid; + always @(posedge clock or posedge reset) begin + if (reset) + ctrl_validMask_grantMask_lastGrant <= 1'h0; + else if (io_out_ready & io_out_valid_0) + ctrl_validMask_grantMask_lastGrant <= io_chosen_choice; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + ctrl_validMask_grantMask_lastGrant = _RANDOM[/*Zero width*/ 1'b0][0]; + `endif // RANDOMIZE_REG_INIT + if (reset) + ctrl_validMask_grantMask_lastGrant = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_in_0_ready = ~ctrl_validMask_1 & io_out_ready; + assign io_in_1_ready = + (~ctrl_validMask_grantMask_lastGrant | ~(ctrl_validMask_1 | io_in_0_valid)) + & io_out_ready; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_addr = io_chosen_choice ? io_in_1_bits_addr : io_in_0_bits_addr; + assign io_out_bits_prot = io_chosen_choice ? io_in_1_bits_prot : io_in_0_bits_prot; + assign io_out_bits_id = io_chosen_choice ? io_in_1_bits_id : io_in_0_bits_id; + assign io_out_bits_len = io_chosen_choice ? io_in_1_bits_len : io_in_0_bits_len; + assign io_out_bits_size = io_chosen_choice ? io_in_1_bits_size : io_in_0_bits_size; + assign io_out_bits_burst = io_chosen_choice ? io_in_1_bits_burst : io_in_0_bits_burst; + assign io_out_bits_lock = io_chosen_choice ? io_in_1_bits_lock : io_in_0_bits_lock; + assign io_out_bits_cache = io_chosen_choice ? io_in_1_bits_cache : io_in_0_bits_cache; + assign io_out_bits_qos = io_chosen_choice ? io_in_1_bits_qos : io_in_0_bits_qos; + assign io_out_bits_region = + io_chosen_choice ? io_in_1_bits_region : io_in_0_bits_region; + assign io_chosen = io_chosen_choice; +endmodule + +// VCS coverage exclude_module +module ram_2x67( + input R0_addr, + R0_en, + R0_clk, + output [66:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [66:0] W0_data +); + + reg [66:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [95:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + for (logic [6:0] j = 7'h0; j < 7'h60; j += 7'h20) begin + _RANDOM_MEM[j +: 32] = `RANDOM; + end + Memory[i[0]] = _RANDOM_MEM[66:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 67'bx; +endmodule + +module Queue2_AxiAddress( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [31:0] io_enq_bits_addr, + input [2:0] io_enq_bits_prot, + input [5:0] io_enq_bits_id, + input [7:0] io_enq_bits_len, + input [2:0] io_enq_bits_size, + input [1:0] io_enq_bits_burst, + input io_enq_bits_lock, + input [3:0] io_enq_bits_cache, + io_enq_bits_qos, + io_enq_bits_region, + input io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits_addr, + output [2:0] io_deq_bits_prot, + output [5:0] io_deq_bits_id, + output [7:0] io_deq_bits_len, + output [2:0] io_deq_bits_size, + output [1:0] io_deq_bits_burst, + output io_deq_bits_lock, + output [3:0] io_deq_bits_cache, + io_deq_bits_qos, + io_deq_bits_region +); + + wire [66:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + wrap = _RANDOM[/*Zero width*/ 1'b0][0]; + wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + wrap = 1'h0; + wrap_1 = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x67 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data + ({io_enq_bits_addr, + io_enq_bits_prot, + io_enq_bits_id, + io_enq_bits_len, + io_enq_bits_size, + io_enq_bits_burst, + io_enq_bits_lock, + io_enq_bits_cache, + io_enq_bits_qos, + io_enq_bits_region}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_addr = _ram_ext_R0_data[66:35]; + assign io_deq_bits_prot = _ram_ext_R0_data[34:32]; + assign io_deq_bits_id = _ram_ext_R0_data[31:26]; + assign io_deq_bits_len = _ram_ext_R0_data[25:18]; + assign io_deq_bits_size = _ram_ext_R0_data[17:15]; + assign io_deq_bits_burst = _ram_ext_R0_data[14:13]; + assign io_deq_bits_lock = _ram_ext_R0_data[12]; + assign io_deq_bits_cache = _ram_ext_R0_data[11:8]; + assign io_deq_bits_qos = _ram_ext_R0_data[7:4]; + assign io_deq_bits_region = _ram_ext_R0_data[3:0]; +endmodule + +module Queue1_RWAxiAddress( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [31:0] io_enq_bits_addr_addr, + input [2:0] io_enq_bits_addr_prot, + input [5:0] io_enq_bits_addr_id, + input [7:0] io_enq_bits_addr_len, + input [2:0] io_enq_bits_addr_size, + input [1:0] io_enq_bits_addr_burst, + input io_enq_bits_addr_lock, + input [3:0] io_enq_bits_addr_cache, + io_enq_bits_addr_qos, + io_enq_bits_addr_region, + input io_enq_bits_write, + io_deq_ready, + output io_deq_valid, + output [31:0] io_deq_bits_addr_addr, + output [5:0] io_deq_bits_addr_id, + output [7:0] io_deq_bits_addr_len, + output [2:0] io_deq_bits_addr_size, + output [1:0] io_deq_bits_addr_burst, + output io_deq_bits_write +); + + reg [67:0] ram; + reg full; + wire do_enq = ~full & io_enq_valid; + always @(posedge clock or posedge reset) begin + if (reset) + full <= 1'h0; + else if (~(do_enq == (io_deq_ready & full))) + full <= do_enq; + end // always @(posedge, posedge) + always @(posedge clock) begin + if (do_enq) + ram <= + {io_enq_bits_addr_addr, + io_enq_bits_addr_prot, + io_enq_bits_addr_id, + io_enq_bits_addr_len, + io_enq_bits_addr_size, + io_enq_bits_addr_burst, + io_enq_bits_addr_lock, + io_enq_bits_addr_cache, + io_enq_bits_addr_qos, + io_enq_bits_addr_region, + io_enq_bits_write}; + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + full = _RANDOM[2'h0][0]; + ram = {_RANDOM[2'h0][31:1], _RANDOM[2'h1], _RANDOM[2'h2][4:0]}; + `endif // RANDOMIZE_REG_INIT + if (reset) + full = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_enq_ready = ~full; + assign io_deq_valid = full; + assign io_deq_bits_addr_addr = ram[67:36]; + assign io_deq_bits_addr_id = ram[32:27]; + assign io_deq_bits_addr_len = ram[26:19]; + assign io_deq_bits_addr_size = ram[18:16]; + assign io_deq_bits_addr_burst = ram[15:14]; + assign io_deq_bits_write = ram[0]; +endmodule + +// VCS coverage exclude_module +module ram_2x145( + input R0_addr, + R0_en, + R0_clk, + output [144:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [144:0] W0_data +); + + reg [144:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [159:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + for (logic [7:0] j = 8'h0; j < 8'hA0; j += 8'h20) begin + _RANDOM_MEM[j +: 32] = `RANDOM; + end + Memory[i[0]] = _RANDOM_MEM[144:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 145'bx; +endmodule + +module Queue2_AxiWriteData( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [127:0] io_enq_bits_data, + input io_enq_bits_last, + input [15:0] io_enq_bits_strb, + input io_deq_ready, + output io_deq_valid, + output [127:0] io_deq_bits_data, + output io_deq_bits_last, + output [15:0] io_deq_bits_strb +); + + wire [144:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + wrap = _RANDOM[/*Zero width*/ 1'b0][0]; + wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + wrap = 1'h0; + wrap_1 = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x145 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_data, io_enq_bits_last, io_enq_bits_strb}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[144:17]; + assign io_deq_bits_last = _ram_ext_R0_data[16]; + assign io_deq_bits_strb = _ram_ext_R0_data[15:0]; +endmodule + +// VCS coverage exclude_module +module ram_2x8( + input R0_addr, + R0_en, + R0_clk, + output [7:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [7:0] W0_data +); + + reg [7:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [31:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM_MEM = `RANDOM; + Memory[i[0]] = _RANDOM_MEM[7:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 8'bx; +endmodule + +module Queue2_AxiWriteResponse( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [5:0] io_enq_bits_id, + input [1:0] io_enq_bits_resp, + input io_deq_ready, + output io_deq_valid, + output [5:0] io_deq_bits_id, + output [1:0] io_deq_bits_resp +); + + wire [7:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + wrap = _RANDOM[/*Zero width*/ 1'b0][0]; + wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + wrap = 1'h0; + wrap_1 = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x8 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_id, io_enq_bits_resp}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_id = _ram_ext_R0_data[7:2]; + assign io_deq_bits_resp = _ram_ext_R0_data[1:0]; +endmodule + +// VCS coverage exclude_module +module ram_2x137( + input R0_addr, + R0_en, + R0_clk, + output [136:0] R0_data, + input W0_addr, + W0_en, + W0_clk, + input [136:0] W0_data +); + + reg [136:0] Memory[0:1]; + always @(posedge W0_clk) begin + if (W0_en & 1'h1) + Memory[W0_addr] <= W0_data; + end // always @(posedge) + `ifdef ENABLE_INITIAL_MEM_ + reg [159:0] _RANDOM_MEM; + initial begin + `INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_MEM_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + for (logic [7:0] j = 8'h0; j < 8'hA0; j += 8'h20) begin + _RANDOM_MEM[j +: 32] = `RANDOM; + end + Memory[i[0]] = _RANDOM_MEM[136:0]; + end + `endif // RANDOMIZE_MEM_INIT + end // initial + `endif // ENABLE_INITIAL_MEM_ + assign R0_data = R0_en ? Memory[R0_addr] : 137'bx; +endmodule + +module Queue2_AxiReadData( + input clock, + reset, + output io_enq_ready, + input io_enq_valid, + input [127:0] io_enq_bits_data, + input [5:0] io_enq_bits_id, + input [1:0] io_enq_bits_resp, + input io_enq_bits_last, + io_deq_ready, + output io_deq_valid, + output [127:0] io_deq_bits_data, + output [5:0] io_deq_bits_id, + output [1:0] io_deq_bits_resp, + output io_deq_bits_last, + output [1:0] io_count +); + + wire [136:0] _ram_ext_R0_data; + reg wrap; + reg wrap_1; + reg maybe_full; + wire ptr_match = wrap == wrap_1; + wire empty = ptr_match & ~maybe_full; + wire full = ptr_match & maybe_full; + wire do_enq = ~full & io_enq_valid; + wire do_deq = io_deq_ready & ~empty; + always @(posedge clock or posedge reset) begin + if (reset) begin + wrap <= 1'h0; + wrap_1 <= 1'h0; + maybe_full <= 1'h0; + end + else begin + if (do_enq) + wrap <= wrap - 1'h1; + if (do_deq) + wrap_1 <= wrap_1 - 1'h1; + if (~(do_enq == do_deq)) + maybe_full <= do_enq; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + wrap = _RANDOM[/*Zero width*/ 1'b0][0]; + wrap_1 = _RANDOM[/*Zero width*/ 1'b0][1]; + maybe_full = _RANDOM[/*Zero width*/ 1'b0][2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + wrap = 1'h0; + wrap_1 = 1'h0; + maybe_full = 1'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + ram_2x137 ram_ext ( + .R0_addr (wrap_1), + .R0_en (1'h1), + .R0_clk (clock), + .R0_data (_ram_ext_R0_data), + .W0_addr (wrap), + .W0_en (do_enq), + .W0_clk (clock), + .W0_data ({io_enq_bits_data, io_enq_bits_id, io_enq_bits_resp, io_enq_bits_last}) + ); + assign io_enq_ready = ~full; + assign io_deq_valid = ~empty; + assign io_deq_bits_data = _ram_ext_R0_data[136:9]; + assign io_deq_bits_id = _ram_ext_R0_data[8:3]; + assign io_deq_bits_resp = _ram_ext_R0_data[2:1]; + assign io_deq_bits_last = _ram_ext_R0_data[0]; + assign io_count = {full, wrap - wrap_1}; +endmodule + +module AxiSlave( + input clock, + reset, + output io_axi_write_addr_ready, + input io_axi_write_addr_valid, + input [31:0] io_axi_write_addr_bits_addr, + input [2:0] io_axi_write_addr_bits_prot, + input [5:0] io_axi_write_addr_bits_id, + input [7:0] io_axi_write_addr_bits_len, + input [2:0] io_axi_write_addr_bits_size, + input [1:0] io_axi_write_addr_bits_burst, + input io_axi_write_addr_bits_lock, + input [3:0] io_axi_write_addr_bits_cache, + io_axi_write_addr_bits_qos, + io_axi_write_addr_bits_region, + output io_axi_write_data_ready, + input io_axi_write_data_valid, + input [127:0] io_axi_write_data_bits_data, + input io_axi_write_data_bits_last, + input [15:0] io_axi_write_data_bits_strb, + input io_axi_write_resp_ready, + output io_axi_write_resp_valid, + output [5:0] io_axi_write_resp_bits_id, + output [1:0] io_axi_write_resp_bits_resp, + output io_axi_read_addr_ready, + input io_axi_read_addr_valid, + input [31:0] io_axi_read_addr_bits_addr, + input [2:0] io_axi_read_addr_bits_prot, + input [5:0] io_axi_read_addr_bits_id, + input [7:0] io_axi_read_addr_bits_len, + input [2:0] io_axi_read_addr_bits_size, + input [1:0] io_axi_read_addr_bits_burst, + input io_axi_read_addr_bits_lock, + input [3:0] io_axi_read_addr_bits_cache, + io_axi_read_addr_bits_qos, + io_axi_read_addr_bits_region, + input io_axi_read_data_ready, + output io_axi_read_data_valid, + output [127:0] io_axi_read_data_bits_data, + output [5:0] io_axi_read_data_bits_id, + output [1:0] io_axi_read_data_bits_resp, + output io_axi_read_data_bits_last, + io_fabric_readDataAddr_valid, + output [31:0] io_fabric_readDataAddr_bits, + input io_fabric_readData_valid, + input [127:0] io_fabric_readData_bits, + output io_fabric_writeDataAddr_valid, + output [31:0] io_fabric_writeDataAddr_bits, + output [127:0] io_fabric_writeDataBits, + output [15:0] io_fabric_writeDataStrb, + input io_fabric_writeResp, + io_periBusy +); + + wire _readDataQueue_io_enq_ready; + wire _readDataQueue_io_deq_valid; + wire [1:0] _readDataQueue_io_count; + wire _io_axi_write_resp_q_io_enq_ready; + wire _writeData_q_io_deq_valid; + wire _writeData_q_io_deq_bits_last; + wire _axiAddrCmd_q_io_enq_ready; + wire _axiAddrCmd_q_io_deq_valid; + wire [31:0] _axiAddrCmd_q_io_deq_bits_addr_addr; + wire [5:0] _axiAddrCmd_q_io_deq_bits_addr_id; + wire [7:0] _axiAddrCmd_q_io_deq_bits_addr_len; + wire [2:0] _axiAddrCmd_q_io_deq_bits_addr_size; + wire [1:0] _axiAddrCmd_q_io_deq_bits_addr_burst; + wire _axiAddrCmd_q_io_deq_bits_write; + wire _addrArbiter_io_in_1_q_io_deq_valid; + wire [31:0] _addrArbiter_io_in_1_q_io_deq_bits_addr; + wire [2:0] _addrArbiter_io_in_1_q_io_deq_bits_prot; + wire [5:0] _addrArbiter_io_in_1_q_io_deq_bits_id; + wire [7:0] _addrArbiter_io_in_1_q_io_deq_bits_len; + wire [2:0] _addrArbiter_io_in_1_q_io_deq_bits_size; + wire [1:0] _addrArbiter_io_in_1_q_io_deq_bits_burst; + wire _addrArbiter_io_in_1_q_io_deq_bits_lock; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_cache; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_qos; + wire [3:0] _addrArbiter_io_in_1_q_io_deq_bits_region; + wire _addrArbiter_io_in_0_q_io_deq_valid; + wire [31:0] _addrArbiter_io_in_0_q_io_deq_bits_addr; + wire [2:0] _addrArbiter_io_in_0_q_io_deq_bits_prot; + wire [5:0] _addrArbiter_io_in_0_q_io_deq_bits_id; + wire [7:0] _addrArbiter_io_in_0_q_io_deq_bits_len; + wire [2:0] _addrArbiter_io_in_0_q_io_deq_bits_size; + wire [1:0] _addrArbiter_io_in_0_q_io_deq_bits_burst; + wire _addrArbiter_io_in_0_q_io_deq_bits_lock; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_cache; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_qos; + wire [3:0] _addrArbiter_io_in_0_q_io_deq_bits_region; + wire _addrArbiter_io_in_0_ready; + wire _addrArbiter_io_in_1_ready; + wire _addrArbiter_io_out_valid; + wire [31:0] _addrArbiter_io_out_bits_addr; + wire [2:0] _addrArbiter_io_out_bits_prot; + wire [5:0] _addrArbiter_io_out_bits_id; + wire [7:0] _addrArbiter_io_out_bits_len; + wire [2:0] _addrArbiter_io_out_bits_size; + wire [1:0] _addrArbiter_io_out_bits_burst; + wire _addrArbiter_io_out_bits_lock; + wire [3:0] _addrArbiter_io_out_bits_cache; + wire [3:0] _addrArbiter_io_out_bits_qos; + wire [3:0] _addrArbiter_io_out_bits_region; + wire _addrArbiter_io_chosen; + wire writeActive = _axiAddrCmd_q_io_deq_valid & _axiAddrCmd_q_io_deq_bits_write; + wire readActive = _axiAddrCmd_q_io_deq_valid & ~_axiAddrCmd_q_io_deq_bits_write; + reg [31:0] cmdAddr; + wire maybeWriteData = + writeActive & _writeData_q_io_deq_valid & _io_axi_write_resp_q_io_enq_ready; + wire writeData_q_io_deq_ready = maybeWriteData & ~io_periBusy; + wire writeResponse_valid = + writeData_q_io_deq_ready & _writeData_q_io_deq_bits_last; + reg readIssued; + reg [8:0] readsIssued; + wire [8:0] _GEN = {1'h0, _axiAddrCmd_q_io_deq_bits_addr_len}; + wire maybeIssueRead = + readActive + & (|(4'h2 + - ({1'h0, {1'h0, _readDataQueue_io_count} + {2'h0, readIssued}} + - {3'h0, io_axi_read_data_ready & _readDataQueue_io_deq_valid}))) + & readsIssued <= _GEN; + wire readDataQueue_io_enq_bits_last = readsIssued == _GEN + 9'h1; + wire [31:0] cmdAddrBase = + _axiAddrCmd_q_io_deq_bits_addr_addr + & {25'h1FFFFFF, + _axiAddrCmd_q_io_deq_bits_addr_size != 3'h7, + _axiAddrCmd_q_io_deq_bits_addr_size[2:1] != 2'h3, + _axiAddrCmd_q_io_deq_bits_addr_size < 3'h5, + ~(_axiAddrCmd_q_io_deq_bits_addr_size[2]), + _axiAddrCmd_q_io_deq_bits_addr_size < 3'h3, + _axiAddrCmd_q_io_deq_bits_addr_size < 3'h2, + _axiAddrCmd_q_io_deq_bits_addr_size == 3'h0}; + wire [31:0] _GEN_0 = {24'h0, 8'h1 << _axiAddrCmd_q_io_deq_bits_addr_size}; + wire [31:0] _addrNext_newAddr_T_1 = cmdAddr + _GEN_0; + wire _addrNext_T = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h0; + wire _addrNext_T_2 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h1; + wire _addrNext_T_7 = _axiAddrCmd_q_io_deq_bits_addr_burst == 2'h2; + wire validBurst = + _axiAddrCmd_q_io_deq_valid & (_addrNext_T | _addrNext_T_2 | _addrNext_T_7); + wire issueRead = maybeIssueRead & ~io_periBusy; + wire _cmdAddr_T = _axiAddrCmd_q_io_enq_ready & _addrArbiter_io_out_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + cmdAddr <= 32'h0; + readIssued <= 1'h0; + readsIssued <= 9'h0; + end + else begin + if (_cmdAddr_T) + cmdAddr <= _addrArbiter_io_out_bits_addr; + else if (~(maybeWriteData & ~io_periBusy | maybeIssueRead & ~io_periBusy) + | validBurst & _addrNext_T) begin + end + else if (validBurst & _addrNext_T_2) + cmdAddr <= cmdAddr + _GEN_0; + else if (validBurst & _addrNext_T_7) + cmdAddr <= + _addrNext_newAddr_T_1 >= cmdAddrBase + 32'h10 + ? cmdAddrBase + : _addrNext_newAddr_T_1; + readIssued <= issueRead; + readsIssued <= _cmdAddr_T ? 9'h0 : readsIssued + {8'h0, issueRead}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:1]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin + _RANDOM[i[0]] = `RANDOM; + end + cmdAddr = _RANDOM[1'h0]; + readIssued = _RANDOM[1'h1][0]; + readsIssued = _RANDOM[1'h1][9:1]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + cmdAddr = 32'h0; + readIssued = 1'h0; + readsIssued = 9'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + CoralNPURRArbiter addrArbiter ( + .clock (clock), + .reset (reset), + .io_in_0_ready (_addrArbiter_io_in_0_ready), + .io_in_0_valid (_addrArbiter_io_in_0_q_io_deq_valid), + .io_in_0_bits_addr (_addrArbiter_io_in_0_q_io_deq_bits_addr), + .io_in_0_bits_prot (_addrArbiter_io_in_0_q_io_deq_bits_prot), + .io_in_0_bits_id (_addrArbiter_io_in_0_q_io_deq_bits_id), + .io_in_0_bits_len (_addrArbiter_io_in_0_q_io_deq_bits_len), + .io_in_0_bits_size (_addrArbiter_io_in_0_q_io_deq_bits_size), + .io_in_0_bits_burst (_addrArbiter_io_in_0_q_io_deq_bits_burst), + .io_in_0_bits_lock (_addrArbiter_io_in_0_q_io_deq_bits_lock), + .io_in_0_bits_cache (_addrArbiter_io_in_0_q_io_deq_bits_cache), + .io_in_0_bits_qos (_addrArbiter_io_in_0_q_io_deq_bits_qos), + .io_in_0_bits_region (_addrArbiter_io_in_0_q_io_deq_bits_region), + .io_in_1_ready (_addrArbiter_io_in_1_ready), + .io_in_1_valid (_addrArbiter_io_in_1_q_io_deq_valid), + .io_in_1_bits_addr (_addrArbiter_io_in_1_q_io_deq_bits_addr), + .io_in_1_bits_prot (_addrArbiter_io_in_1_q_io_deq_bits_prot), + .io_in_1_bits_id (_addrArbiter_io_in_1_q_io_deq_bits_id), + .io_in_1_bits_len (_addrArbiter_io_in_1_q_io_deq_bits_len), + .io_in_1_bits_size (_addrArbiter_io_in_1_q_io_deq_bits_size), + .io_in_1_bits_burst (_addrArbiter_io_in_1_q_io_deq_bits_burst), + .io_in_1_bits_lock (_addrArbiter_io_in_1_q_io_deq_bits_lock), + .io_in_1_bits_cache (_addrArbiter_io_in_1_q_io_deq_bits_cache), + .io_in_1_bits_qos (_addrArbiter_io_in_1_q_io_deq_bits_qos), + .io_in_1_bits_region (_addrArbiter_io_in_1_q_io_deq_bits_region), + .io_out_ready (_axiAddrCmd_q_io_enq_ready), + .io_out_valid (_addrArbiter_io_out_valid), + .io_out_bits_addr (_addrArbiter_io_out_bits_addr), + .io_out_bits_prot (_addrArbiter_io_out_bits_prot), + .io_out_bits_id (_addrArbiter_io_out_bits_id), + .io_out_bits_len (_addrArbiter_io_out_bits_len), + .io_out_bits_size (_addrArbiter_io_out_bits_size), + .io_out_bits_burst (_addrArbiter_io_out_bits_burst), + .io_out_bits_lock (_addrArbiter_io_out_bits_lock), + .io_out_bits_cache (_addrArbiter_io_out_bits_cache), + .io_out_bits_qos (_addrArbiter_io_out_bits_qos), + .io_out_bits_region (_addrArbiter_io_out_bits_region), + .io_chosen (_addrArbiter_io_chosen) + ); + Queue2_AxiAddress addrArbiter_io_in_0_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (io_axi_read_addr_ready), + .io_enq_valid (io_axi_read_addr_valid), + .io_enq_bits_addr (io_axi_read_addr_bits_addr), + .io_enq_bits_prot (io_axi_read_addr_bits_prot), + .io_enq_bits_id (io_axi_read_addr_bits_id), + .io_enq_bits_len (io_axi_read_addr_bits_len), + .io_enq_bits_size (io_axi_read_addr_bits_size), + .io_enq_bits_burst (io_axi_read_addr_bits_burst), + .io_enq_bits_lock (io_axi_read_addr_bits_lock), + .io_enq_bits_cache (io_axi_read_addr_bits_cache), + .io_enq_bits_qos (io_axi_read_addr_bits_qos), + .io_enq_bits_region (io_axi_read_addr_bits_region), + .io_deq_ready (_addrArbiter_io_in_0_ready), + .io_deq_valid (_addrArbiter_io_in_0_q_io_deq_valid), + .io_deq_bits_addr (_addrArbiter_io_in_0_q_io_deq_bits_addr), + .io_deq_bits_prot (_addrArbiter_io_in_0_q_io_deq_bits_prot), + .io_deq_bits_id (_addrArbiter_io_in_0_q_io_deq_bits_id), + .io_deq_bits_len (_addrArbiter_io_in_0_q_io_deq_bits_len), + .io_deq_bits_size (_addrArbiter_io_in_0_q_io_deq_bits_size), + .io_deq_bits_burst (_addrArbiter_io_in_0_q_io_deq_bits_burst), + .io_deq_bits_lock (_addrArbiter_io_in_0_q_io_deq_bits_lock), + .io_deq_bits_cache (_addrArbiter_io_in_0_q_io_deq_bits_cache), + .io_deq_bits_qos (_addrArbiter_io_in_0_q_io_deq_bits_qos), + .io_deq_bits_region (_addrArbiter_io_in_0_q_io_deq_bits_region) + ); + Queue2_AxiAddress addrArbiter_io_in_1_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (io_axi_write_addr_ready), + .io_enq_valid (io_axi_write_addr_valid), + .io_enq_bits_addr (io_axi_write_addr_bits_addr), + .io_enq_bits_prot (io_axi_write_addr_bits_prot), + .io_enq_bits_id (io_axi_write_addr_bits_id), + .io_enq_bits_len (io_axi_write_addr_bits_len), + .io_enq_bits_size (io_axi_write_addr_bits_size), + .io_enq_bits_burst (io_axi_write_addr_bits_burst), + .io_enq_bits_lock (io_axi_write_addr_bits_lock), + .io_enq_bits_cache (io_axi_write_addr_bits_cache), + .io_enq_bits_qos (io_axi_write_addr_bits_qos), + .io_enq_bits_region (io_axi_write_addr_bits_region), + .io_deq_ready (_addrArbiter_io_in_1_ready), + .io_deq_valid (_addrArbiter_io_in_1_q_io_deq_valid), + .io_deq_bits_addr (_addrArbiter_io_in_1_q_io_deq_bits_addr), + .io_deq_bits_prot (_addrArbiter_io_in_1_q_io_deq_bits_prot), + .io_deq_bits_id (_addrArbiter_io_in_1_q_io_deq_bits_id), + .io_deq_bits_len (_addrArbiter_io_in_1_q_io_deq_bits_len), + .io_deq_bits_size (_addrArbiter_io_in_1_q_io_deq_bits_size), + .io_deq_bits_burst (_addrArbiter_io_in_1_q_io_deq_bits_burst), + .io_deq_bits_lock (_addrArbiter_io_in_1_q_io_deq_bits_lock), + .io_deq_bits_cache (_addrArbiter_io_in_1_q_io_deq_bits_cache), + .io_deq_bits_qos (_addrArbiter_io_in_1_q_io_deq_bits_qos), + .io_deq_bits_region (_addrArbiter_io_in_1_q_io_deq_bits_region) + ); + Queue1_RWAxiAddress axiAddrCmd_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (_axiAddrCmd_q_io_enq_ready), + .io_enq_valid (_addrArbiter_io_out_valid), + .io_enq_bits_addr_addr (_addrArbiter_io_out_bits_addr), + .io_enq_bits_addr_prot (_addrArbiter_io_out_bits_prot), + .io_enq_bits_addr_id (_addrArbiter_io_out_bits_id), + .io_enq_bits_addr_len (_addrArbiter_io_out_bits_len), + .io_enq_bits_addr_size (_addrArbiter_io_out_bits_size), + .io_enq_bits_addr_burst (_addrArbiter_io_out_bits_burst), + .io_enq_bits_addr_lock (_addrArbiter_io_out_bits_lock), + .io_enq_bits_addr_cache (_addrArbiter_io_out_bits_cache), + .io_enq_bits_addr_qos (_addrArbiter_io_out_bits_qos), + .io_enq_bits_addr_region (_addrArbiter_io_out_bits_region), + .io_enq_bits_write (_addrArbiter_io_chosen), + .io_deq_ready + (writeActive + ? writeResponse_valid + : readActive & _readDataQueue_io_enq_ready & readIssued + & readDataQueue_io_enq_bits_last), + .io_deq_valid (_axiAddrCmd_q_io_deq_valid), + .io_deq_bits_addr_addr (_axiAddrCmd_q_io_deq_bits_addr_addr), + .io_deq_bits_addr_id (_axiAddrCmd_q_io_deq_bits_addr_id), + .io_deq_bits_addr_len (_axiAddrCmd_q_io_deq_bits_addr_len), + .io_deq_bits_addr_size (_axiAddrCmd_q_io_deq_bits_addr_size), + .io_deq_bits_addr_burst (_axiAddrCmd_q_io_deq_bits_addr_burst), + .io_deq_bits_write (_axiAddrCmd_q_io_deq_bits_write) + ); + Queue2_AxiWriteData writeData_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (io_axi_write_data_ready), + .io_enq_valid (io_axi_write_data_valid), + .io_enq_bits_data (io_axi_write_data_bits_data), + .io_enq_bits_last (io_axi_write_data_bits_last), + .io_enq_bits_strb (io_axi_write_data_bits_strb), + .io_deq_ready (writeData_q_io_deq_ready), + .io_deq_valid (_writeData_q_io_deq_valid), + .io_deq_bits_data (io_fabric_writeDataBits), + .io_deq_bits_last (_writeData_q_io_deq_bits_last), + .io_deq_bits_strb (io_fabric_writeDataStrb) + ); + Queue2_AxiWriteResponse io_axi_write_resp_q ( + .clock (clock), + .reset (reset), + .io_enq_ready (_io_axi_write_resp_q_io_enq_ready), + .io_enq_valid (writeResponse_valid), + .io_enq_bits_id (_axiAddrCmd_q_io_deq_bits_addr_id), + .io_enq_bits_resp ({~io_fabric_writeResp, 1'h0}), + .io_deq_ready (io_axi_write_resp_ready), + .io_deq_valid (io_axi_write_resp_valid), + .io_deq_bits_id (io_axi_write_resp_bits_id), + .io_deq_bits_resp (io_axi_write_resp_bits_resp) + ); + Queue2_AxiReadData readDataQueue ( + .clock (clock), + .reset (reset), + .io_enq_ready (_readDataQueue_io_enq_ready), + .io_enq_valid (readIssued), + .io_enq_bits_data (io_fabric_readData_bits), + .io_enq_bits_id (_axiAddrCmd_q_io_deq_bits_addr_id), + .io_enq_bits_resp ({~io_fabric_readData_valid, 1'h0}), + .io_enq_bits_last (readDataQueue_io_enq_bits_last), + .io_deq_ready (io_axi_read_data_ready), + .io_deq_valid (_readDataQueue_io_deq_valid), + .io_deq_bits_data (io_axi_read_data_bits_data), + .io_deq_bits_id (io_axi_read_data_bits_id), + .io_deq_bits_resp (io_axi_read_data_bits_resp), + .io_deq_bits_last (io_axi_read_data_bits_last), + .io_count (_readDataQueue_io_count) + ); + assign io_axi_read_data_valid = _readDataQueue_io_deq_valid; + assign io_fabric_readDataAddr_valid = maybeIssueRead; + assign io_fabric_readDataAddr_bits = cmdAddr; + assign io_fabric_writeDataAddr_valid = maybeWriteData; + assign io_fabric_writeDataAddr_bits = cmdAddr; +endmodule + +module Slice_2( + input clock, + reset, + output io_in_ready, + input io_in_valid, + input [31:0] io_in_bits_addr, + input [2:0] io_in_bits_prot, + input [5:0] io_in_bits_id, + input [7:0] io_in_bits_len, + input [2:0] io_in_bits_size, + input [1:0] io_in_bits_burst, + input io_in_bits_lock, + input [3:0] io_in_bits_cache, + io_in_bits_qos, + io_in_bits_region, + input io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_addr, + output [2:0] io_out_bits_prot, + output [5:0] io_out_bits_id, + output [7:0] io_out_bits_len, + output [2:0] io_out_bits_size, + output [1:0] io_out_bits_burst, + output io_out_bits_lock, + output [3:0] io_out_bits_cache, + io_out_bits_qos, + io_out_bits_region +); + + reg ipos; + reg opos; + reg [31:0] mem_0_addr; + reg [2:0] mem_0_prot; + reg [5:0] mem_0_id; + reg [7:0] mem_0_len; + reg [2:0] mem_0_size; + reg [1:0] mem_0_burst; + reg mem_0_lock; + reg [3:0] mem_0_cache; + reg [3:0] mem_0_qos; + reg [3:0] mem_0_region; + wire io_in_ready_0 = ipos == opos | io_out_ready; + wire io_out_valid_0 = ipos != opos; + always @(posedge clock or posedge reset) begin + if (reset) begin + ipos <= 1'h0; + opos <= 1'h0; + mem_0_addr <= 32'h0; + mem_0_prot <= 3'h0; + mem_0_id <= 6'h0; + mem_0_len <= 8'h0; + mem_0_size <= 3'h0; + mem_0_burst <= 2'h0; + mem_0_lock <= 1'h0; + mem_0_cache <= 4'h0; + mem_0_qos <= 4'h0; + mem_0_region <= 4'h0; + end + else begin + if (io_in_valid & io_in_ready_0) begin + ipos <= ipos - 1'h1; + mem_0_addr <= io_in_bits_addr; + mem_0_prot <= io_in_bits_prot; + mem_0_id <= io_in_bits_id; + mem_0_len <= io_in_bits_len; + mem_0_size <= io_in_bits_size; + mem_0_burst <= io_in_bits_burst; + mem_0_lock <= io_in_bits_lock; + mem_0_cache <= io_in_bits_cache; + mem_0_qos <= io_in_bits_qos; + mem_0_region <= io_in_bits_region; + end + if (io_out_valid_0 & io_out_ready) + opos <= opos - 1'h1; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:2]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [1:0] i = 2'h0; i < 2'h3; i += 2'h1) begin + _RANDOM[i] = `RANDOM; + end + ipos = _RANDOM[2'h0][0]; + opos = _RANDOM[2'h0][1]; + mem_0_addr = {_RANDOM[2'h0][31:3], _RANDOM[2'h1][2:0]}; + mem_0_prot = _RANDOM[2'h1][5:3]; + mem_0_id = _RANDOM[2'h1][11:6]; + mem_0_len = _RANDOM[2'h1][19:12]; + mem_0_size = _RANDOM[2'h1][22:20]; + mem_0_burst = _RANDOM[2'h1][24:23]; + mem_0_lock = _RANDOM[2'h1][25]; + mem_0_cache = _RANDOM[2'h1][29:26]; + mem_0_qos = {_RANDOM[2'h1][31:30], _RANDOM[2'h2][1:0]}; + mem_0_region = _RANDOM[2'h2][5:2]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ipos = 1'h0; + opos = 1'h0; + mem_0_addr = 32'h0; + mem_0_prot = 3'h0; + mem_0_id = 6'h0; + mem_0_len = 8'h0; + mem_0_size = 3'h0; + mem_0_burst = 2'h0; + mem_0_lock = 1'h0; + mem_0_cache = 4'h0; + mem_0_qos = 4'h0; + mem_0_region = 4'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_in_ready = io_in_ready_0; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_addr = mem_0_addr; + assign io_out_bits_prot = mem_0_prot; + assign io_out_bits_id = mem_0_id; + assign io_out_bits_len = mem_0_len; + assign io_out_bits_size = mem_0_size; + assign io_out_bits_burst = mem_0_burst; + assign io_out_bits_lock = mem_0_lock; + assign io_out_bits_cache = mem_0_cache; + assign io_out_bits_qos = mem_0_qos; + assign io_out_bits_region = mem_0_region; +endmodule + +module FifoX_1( + input clock, + reset, + io_in_valid, + input [31:0] io_in_bits_0_bits_addr, + input [7:0] io_in_bits_0_bits_len, + input [2:0] io_in_bits_0_bits_size, + input io_in_bits_1_valid, + input [31:0] io_in_bits_1_bits_addr, + input [2:0] io_in_bits_1_bits_size, + input io_out_ready, + output io_out_valid, + output [31:0] io_out_bits_addr, + output [2:0] io_out_bits_prot, + output [5:0] io_out_bits_id, + output [7:0] io_out_bits_len, + output [2:0] io_out_bits_size, + output [1:0] io_out_bits_burst, + output io_out_bits_lock, + output [3:0] io_out_bits_cache, + io_out_bits_qos, + io_out_bits_region, + output [1:0] io_count +); + + wire io_in_ready; + wire _mslice_io_in_ready; + wire _mslice_io_out_valid; + reg [31:0] mem_0_addr; + reg [2:0] mem_0_prot; + reg [7:0] mem_0_len; + reg [2:0] mem_0_size; + reg [1:0] mem_0_burst; + reg [31:0] mem_1_addr; + reg [2:0] mem_1_prot; + reg [7:0] mem_1_len; + reg [2:0] mem_1_size; + reg [1:0] mem_1_burst; + reg inxpos_0; + reg inxpos_1; + reg [1:0] outpos; + reg [1:0] mcount; + wire ivalid = io_in_valid & io_in_ready; + wire [1:0] _GEN = {1'h0, io_in_bits_1_valid}; + wire [1:0] icount = _GEN + 2'h1; + wire mslice_io_in_valid = (|mcount) ? io_out_ready : ivalid; + wire [3:0][31:0] _GEN_0 = {{mem_0_addr}, {32'h0}, {mem_1_addr}, {mem_0_addr}}; + wire [3:0][2:0] _GEN_1 = {{mem_0_prot}, {3'h0}, {mem_1_prot}, {mem_0_prot}}; + wire [3:0][7:0] _GEN_2 = {{mem_0_len}, {8'h0}, {mem_1_len}, {mem_0_len}}; + wire [3:0][2:0] _GEN_3 = {{mem_0_size}, {3'h0}, {mem_1_size}, {mem_0_size}}; + wire [3:0][1:0] _GEN_4 = {{mem_0_burst}, {2'h0}, {mem_1_burst}, {mem_0_burst}}; + assign io_in_ready = mcount <= 2'h2 - icount; + wire [2:0] outpos_c = {1'h0, outpos} + 3'h1; + wire dec = mslice_io_in_valid & _mslice_io_in_ready; + wire _inxvalid_T_7 = _GEN + 2'h1 == 2'h1 & io_in_bits_1_valid; + wire _inxvalid_T_20 = _GEN + 2'h1 == 2'h2 & io_in_bits_1_valid; + always @(posedge clock or posedge reset) begin + if (reset) begin + mem_0_addr <= 32'h0; + mem_0_prot <= 3'h0; + mem_0_len <= 8'h0; + mem_0_size <= 3'h0; + mem_0_burst <= 2'h0; + mem_1_addr <= 32'h0; + mem_1_prot <= 3'h0; + mem_1_len <= 8'h0; + mem_1_size <= 3'h0; + mem_1_burst <= 2'h0; + inxpos_0 <= 1'h0; + inxpos_1 <= 1'h1; + outpos <= 2'h0; + mcount <= 2'h0; + end + else begin + if (ivalid + & (|({1'h0, ~inxpos_0} + + {1'h0, ~inxpos_0 & _inxvalid_T_7 | ~inxpos_1 & _inxvalid_T_20}))) begin + mem_0_addr <= inxpos_0 ? io_in_bits_1_bits_addr : io_in_bits_0_bits_addr; + mem_0_prot <= 3'h2; + mem_0_len <= inxpos_0 ? 8'h0 : io_in_bits_0_bits_len; + mem_0_size <= inxpos_0 ? io_in_bits_1_bits_size : io_in_bits_0_bits_size; + mem_0_burst <= 2'h1; + end + if (ivalid + & (|({1'h0, inxpos_0} + + {1'h0, inxpos_0 & _inxvalid_T_7 | inxpos_1 & _inxvalid_T_20}))) begin + mem_1_addr <= inxpos_0 ? io_in_bits_0_bits_addr : io_in_bits_1_bits_addr; + mem_1_prot <= 3'h2; + mem_1_len <= inxpos_0 ? io_in_bits_0_bits_len : 8'h0; + mem_1_size <= inxpos_0 ? io_in_bits_0_bits_size : io_in_bits_1_bits_size; + mem_1_burst <= 2'h1; + end + if (ivalid) begin + inxpos_0 <= inxpos_0 + icount[0]; + inxpos_1 <= inxpos_1 + icount[0]; + end + if (dec) + outpos <= outpos_c < 3'h2 ? outpos_c[1:0] : outpos - 2'h1; + if (ivalid | dec) + mcount <= mcount + (ivalid ? icount : 2'h0) - {1'h0, dec}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:6]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h7; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + mem_0_addr = _RANDOM[3'h0]; + mem_0_prot = _RANDOM[3'h1][2:0]; + mem_0_len = _RANDOM[3'h1][16:9]; + mem_0_size = _RANDOM[3'h1][19:17]; + mem_0_burst = _RANDOM[3'h1][21:20]; + mem_1_addr = {_RANDOM[3'h2][31:3], _RANDOM[3'h3][2:0]}; + mem_1_prot = _RANDOM[3'h3][5:3]; + mem_1_len = _RANDOM[3'h3][19:12]; + mem_1_size = _RANDOM[3'h3][22:20]; + mem_1_burst = _RANDOM[3'h3][24:23]; + inxpos_0 = _RANDOM[3'h6][9]; + inxpos_1 = _RANDOM[3'h6][10]; + outpos = _RANDOM[3'h6][12:11]; + mcount = _RANDOM[3'h6][14:13]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + mem_0_addr = 32'h0; + mem_0_prot = 3'h0; + mem_0_len = 8'h0; + mem_0_size = 3'h0; + mem_0_burst = 2'h0; + mem_1_addr = 32'h0; + mem_1_prot = 3'h0; + mem_1_len = 8'h0; + mem_1_size = 3'h0; + mem_1_burst = 2'h0; + inxpos_0 = 1'h0; + inxpos_1 = 1'h1; + outpos = 2'h0; + mcount = 2'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Slice_2 mslice ( + .clock (clock), + .reset (reset), + .io_in_ready (_mslice_io_in_ready), + .io_in_valid (mslice_io_in_valid), + .io_in_bits_addr ((|mcount) ? _GEN_0[outpos] : io_in_bits_0_bits_addr), + .io_in_bits_prot ((|mcount) ? _GEN_1[outpos] : 3'h2), + .io_in_bits_id (6'h0), + .io_in_bits_len ((|mcount) ? _GEN_2[outpos] : io_in_bits_0_bits_len), + .io_in_bits_size ((|mcount) ? _GEN_3[outpos] : io_in_bits_0_bits_size), + .io_in_bits_burst ((|mcount) ? _GEN_4[outpos] : 2'h1), + .io_in_bits_lock (1'h0), + .io_in_bits_cache (4'h0), + .io_in_bits_qos (4'h0), + .io_in_bits_region (4'h0), + .io_out_ready (io_out_ready), + .io_out_valid (_mslice_io_out_valid), + .io_out_bits_addr (io_out_bits_addr), + .io_out_bits_prot (io_out_bits_prot), + .io_out_bits_id (io_out_bits_id), + .io_out_bits_len (io_out_bits_len), + .io_out_bits_size (io_out_bits_size), + .io_out_bits_burst (io_out_bits_burst), + .io_out_bits_lock (io_out_bits_lock), + .io_out_bits_cache (io_out_bits_cache), + .io_out_bits_qos (io_out_bits_qos), + .io_out_bits_region (io_out_bits_region) + ); + assign io_out_valid = _mslice_io_out_valid; + assign io_count = mcount + {1'h0, _mslice_io_out_valid}; +endmodule + +module Slice_4( + input clock, + reset, + output io_in_ready, + input io_in_valid, + input [127:0] io_in_bits_data, + input io_in_bits_last, + input [15:0] io_in_bits_strb, + input io_out_ready, + output io_out_valid, + output [127:0] io_out_bits_data, + output io_out_bits_last, + output [15:0] io_out_bits_strb +); + + reg ipos; + reg opos; + reg [127:0] mem_0_data; + reg mem_0_last; + reg [15:0] mem_0_strb; + wire io_in_ready_0 = ipos == opos | io_out_ready; + wire io_out_valid_0 = ipos != opos; + always @(posedge clock or posedge reset) begin + if (reset) begin + ipos <= 1'h0; + opos <= 1'h0; + mem_0_data <= 128'h0; + mem_0_last <= 1'h0; + mem_0_strb <= 16'h0; + end + else begin + if (io_in_valid & io_in_ready_0) begin + ipos <= ipos - 1'h1; + mem_0_data <= io_in_bits_data; + mem_0_last <= io_in_bits_last; + mem_0_strb <= io_in_bits_strb; + end + if (io_out_valid_0 & io_out_ready) + opos <= opos - 1'h1; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:4]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + ipos = _RANDOM[3'h0][0]; + opos = _RANDOM[3'h0][1]; + mem_0_data = + {_RANDOM[3'h0][31:3], + _RANDOM[3'h1], + _RANDOM[3'h2], + _RANDOM[3'h3], + _RANDOM[3'h4][2:0]}; + mem_0_last = _RANDOM[3'h4][3]; + mem_0_strb = _RANDOM[3'h4][19:4]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + ipos = 1'h0; + opos = 1'h0; + mem_0_data = 128'h0; + mem_0_last = 1'h0; + mem_0_strb = 16'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_in_ready = io_in_ready_0; + assign io_out_valid = io_out_valid_0; + assign io_out_bits_data = mem_0_data; + assign io_out_bits_last = mem_0_last; + assign io_out_bits_strb = mem_0_strb; +endmodule + +module FifoX_3( + input clock, + reset, + io_in_valid, + input [127:0] io_in_bits_0_bits_data, + input [15:0] io_in_bits_0_bits_strb, + input io_in_bits_1_valid, + input [127:0] io_in_bits_1_bits_data, + input [15:0] io_in_bits_1_bits_strb, + input io_out_ready, + output io_out_valid, + output [127:0] io_out_bits_data, + output io_out_bits_last, + output [15:0] io_out_bits_strb, + output [1:0] io_count +); + + wire io_in_ready; + wire _mslice_io_in_ready; + wire _mslice_io_out_valid; + reg [127:0] mem_0_data; + reg mem_0_last; + reg [15:0] mem_0_strb; + reg [127:0] mem_1_data; + reg mem_1_last; + reg [15:0] mem_1_strb; + reg inxpos_0; + reg inxpos_1; + reg [1:0] outpos; + reg [1:0] mcount; + wire ivalid = io_in_valid & io_in_ready; + wire [1:0] _GEN = {1'h0, io_in_bits_1_valid}; + wire [1:0] icount = _GEN + 2'h1; + wire mslice_io_in_valid = (|mcount) ? io_out_ready : ivalid; + wire [3:0][127:0] _GEN_0 = {{mem_0_data}, {128'h0}, {mem_1_data}, {mem_0_data}}; + wire [3:0] _GEN_1 = {{mem_0_last}, {1'h0}, {mem_1_last}, {mem_0_last}}; + wire [3:0][15:0] _GEN_2 = {{mem_0_strb}, {16'h0}, {mem_1_strb}, {mem_0_strb}}; + assign io_in_ready = mcount <= 2'h2 - icount; + wire [2:0] outpos_c = {1'h0, outpos} + 3'h1; + wire dec = mslice_io_in_valid & _mslice_io_in_ready; + wire _inxvalid_T_7 = _GEN + 2'h1 == 2'h1 & io_in_bits_1_valid; + wire _inxvalid_T_20 = _GEN + 2'h1 == 2'h2 & io_in_bits_1_valid; + wire _GEN_3 = + ivalid + & (|({1'h0, ~inxpos_0} + + {1'h0, ~inxpos_0 & _inxvalid_T_7 | ~inxpos_1 & _inxvalid_T_20})); + wire _GEN_4 = + ivalid + & (|({1'h0, inxpos_0} + + {1'h0, inxpos_0 & _inxvalid_T_7 | inxpos_1 & _inxvalid_T_20})); + always @(posedge clock or posedge reset) begin + if (reset) begin + mem_0_data <= 128'h0; + mem_0_last <= 1'h0; + mem_0_strb <= 16'h0; + mem_1_data <= 128'h0; + mem_1_last <= 1'h0; + mem_1_strb <= 16'h0; + inxpos_0 <= 1'h0; + inxpos_1 <= 1'h1; + outpos <= 2'h0; + mcount <= 2'h0; + end + else begin + if (_GEN_3) begin + mem_0_data <= inxpos_0 ? io_in_bits_1_bits_data : io_in_bits_0_bits_data; + mem_0_strb <= inxpos_0 ? io_in_bits_1_bits_strb : io_in_bits_0_bits_strb; + end + mem_0_last <= _GEN_3 | mem_0_last; + if (_GEN_4) begin + mem_1_data <= inxpos_0 ? io_in_bits_0_bits_data : io_in_bits_1_bits_data; + mem_1_strb <= inxpos_0 ? io_in_bits_0_bits_strb : io_in_bits_1_bits_strb; + end + mem_1_last <= _GEN_4 | mem_1_last; + if (ivalid) begin + inxpos_0 <= inxpos_0 + icount[0]; + inxpos_1 <= inxpos_1 + icount[0]; + end + if (dec) + outpos <= outpos_c < 3'h2 ? outpos_c[1:0] : outpos - 2'h1; + if (ivalid | dec) + mcount <= mcount + (ivalid ? icount : 2'h0) - {1'h0, dec}; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:13]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [3:0] i = 4'h0; i < 4'hE; i += 4'h1) begin + _RANDOM[i] = `RANDOM; + end + mem_0_data = {_RANDOM[4'h0], _RANDOM[4'h1], _RANDOM[4'h2], _RANDOM[4'h3]}; + mem_0_last = _RANDOM[4'h4][0]; + mem_0_strb = _RANDOM[4'h4][16:1]; + mem_1_data = + {_RANDOM[4'h4][31:17], + _RANDOM[4'h5], + _RANDOM[4'h6], + _RANDOM[4'h7], + _RANDOM[4'h8][16:0]}; + mem_1_last = _RANDOM[4'h8][17]; + mem_1_strb = {_RANDOM[4'h8][31:18], _RANDOM[4'h9][1:0]}; + inxpos_0 = _RANDOM[4'hD][19]; + inxpos_1 = _RANDOM[4'hD][20]; + outpos = _RANDOM[4'hD][22:21]; + mcount = _RANDOM[4'hD][24:23]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + mem_0_data = 128'h0; + mem_0_last = 1'h0; + mem_0_strb = 16'h0; + mem_1_data = 128'h0; + mem_1_last = 1'h0; + mem_1_strb = 16'h0; + inxpos_0 = 1'h0; + inxpos_1 = 1'h1; + outpos = 2'h0; + mcount = 2'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + Slice_4 mslice ( + .clock (clock), + .reset (reset), + .io_in_ready (_mslice_io_in_ready), + .io_in_valid (mslice_io_in_valid), + .io_in_bits_data ((|mcount) ? _GEN_0[outpos] : io_in_bits_0_bits_data), + .io_in_bits_last (~(|mcount) | _GEN_1[outpos]), + .io_in_bits_strb ((|mcount) ? _GEN_2[outpos] : io_in_bits_0_bits_strb), + .io_out_ready (io_out_ready), + .io_out_valid (_mslice_io_out_valid), + .io_out_bits_data (io_out_bits_data), + .io_out_bits_last (io_out_bits_last), + .io_out_bits_strb (io_out_bits_strb) + ); + assign io_out_valid = _mslice_io_out_valid; + assign io_count = mcount + {1'h0, _mslice_io_out_valid}; +endmodule + +module DBus2AxiV1( + input clock, + reset, + io_dbus_valid, + output io_dbus_ready, + input io_dbus_write, + input [31:0] io_dbus_pc, + io_dbus_addr, + input [4:0] io_dbus_size, + input [127:0] io_dbus_wdata, + output [127:0] io_dbus_rdata, + input io_axi_write_addr_ready, + output io_axi_write_addr_valid, + output [31:0] io_axi_write_addr_bits_addr, + output [2:0] io_axi_write_addr_bits_prot, + output [5:0] io_axi_write_addr_bits_id, + output [7:0] io_axi_write_addr_bits_len, + output [2:0] io_axi_write_addr_bits_size, + output [1:0] io_axi_write_addr_bits_burst, + output io_axi_write_addr_bits_lock, + output [3:0] io_axi_write_addr_bits_cache, + io_axi_write_addr_bits_qos, + io_axi_write_addr_bits_region, + input io_axi_write_data_ready, + output io_axi_write_data_valid, + output [127:0] io_axi_write_data_bits_data, + output io_axi_write_data_bits_last, + output [15:0] io_axi_write_data_bits_strb, + output io_axi_write_resp_ready, + input io_axi_write_resp_valid, + input [5:0] io_axi_write_resp_bits_id, + input [1:0] io_axi_write_resp_bits_resp, + input io_axi_read_addr_ready, + output io_axi_read_addr_valid, + output [31:0] io_axi_read_addr_bits_addr, + output [2:0] io_axi_read_addr_bits_prot, + output [5:0] io_axi_read_addr_bits_id, + output [7:0] io_axi_read_addr_bits_len, + output [2:0] io_axi_read_addr_bits_size, + output [1:0] io_axi_read_addr_bits_burst, + output io_axi_read_addr_bits_lock, + output [3:0] io_axi_read_addr_bits_cache, + io_axi_read_addr_bits_qos, + io_axi_read_addr_bits_region, + output io_axi_read_data_ready, + input io_axi_read_data_valid, + input [127:0] io_axi_read_data_bits_data, + input [5:0] io_axi_read_data_bits_id, + input [1:0] io_axi_read_data_bits_resp, + input io_axi_read_data_bits_last, + output io_fault_valid, + io_fault_bits_write, + output [31:0] io_fault_bits_addr, + io_fault_bits_epc +); + + wire _writeDataQ_io_out_valid; + wire [1:0] _writeDataQ_io_count; + wire _writeAddrQ_io_out_valid; + wire [1:0] _writeAddrQ_io_count; + wire _readAddrQ_io_out_valid; + wire [1:0] _readAddrQ_io_count; + reg txnActive; + wire newTxn = io_dbus_valid & ~txnActive; + reg [127:0] sdata; + wire [4:0] _dbusAddrAligned_T = io_dbus_size - 5'h1; + wire [4:0] misalignment = io_dbus_addr[4:0] & _dbusAddrAligned_T; + wire [31:0] _crossLineBoundary_T_4 = + {26'h0, {2'h0, io_dbus_addr[3:0]} + {1'h0, io_dbus_size}}; + wire crossLineBoundary = _crossLineBoundary_T_4 > 32'h10; + wire [2:0] belowLineBoundary = 3'h0 - io_dbus_addr[2:0]; + wire [1:0] txnCount = (|misalignment) | crossLineBoundary ? 2'h2 : 2'h1; + wire [4:0] txnSizes_0 = + crossLineBoundary + ? {2'h0, belowLineBoundary} + : (|misalignment) ? io_dbus_size - misalignment : io_dbus_size; + wire [4:0] txnSizes_1 = + crossLineBoundary + ? io_dbus_size - {2'h0, belowLineBoundary} + : (|misalignment) ? misalignment : 5'h0; + wire [31:0] writeAddrQ_io_in_bits_0_bits_addr = + io_dbus_addr - {27'h0, io_dbus_addr[4:0] & _dbusAddrAligned_T}; + reg [1:0] transactionsCompleted; + wire [1:0] _io_dbus_ready_T_11 = transactionsCompleted + 2'h1; + wire _mask0_T_40 = txnSizes_0 > 5'h2; + wire _mask0_T_42 = txnSizes_0 > 5'h4; + wire _mask0_T_43 = txnSizes_0 > 5'h5; + wire _mask0_T_44 = txnSizes_0 > 5'h6; + wire _mask0_T_46 = txnSizes_0 > 5'h8; + wire _mask0_T_47 = txnSizes_0 > 5'h9; + wire _mask0_T_48 = txnSizes_0 > 5'hA; + wire _mask0_T_49 = txnSizes_0 > 5'hB; + wire _mask0_T_50 = txnSizes_0 > 5'hC; + wire _mask0_T_51 = txnSizes_0 > 5'hD; + wire _mask0_T_52 = txnSizes_0 > 5'hE; + wire _mask1_T_42 = txnSizes_1 > 5'h2; + wire _mask1_T_44 = txnSizes_1 > 5'h4; + wire _mask1_T_45 = txnSizes_1 > 5'h5; + wire _mask1_T_46 = txnSizes_1 > 5'h6; + wire _mask1_T_48 = txnSizes_1 > 5'h8; + wire _mask1_T_49 = txnSizes_1 > 5'h9; + wire _mask1_T_50 = txnSizes_1 > 5'hA; + wire _mask1_T_51 = txnSizes_1 > 5'hB; + wire _mask1_T_52 = txnSizes_1 > 5'hC; + wire _mask1_T_53 = txnSizes_1 > 5'hD; + wire _mask1_T_54 = txnSizes_1 > 5'hE; + wire writeDataQ_io_in_valid = newTxn & io_dbus_write; + wire [15:0] _mask0_T_63 = + io_dbus_addr[0] + ? {_mask0_T_52, + _mask0_T_51, + _mask0_T_50, + _mask0_T_49, + _mask0_T_48, + _mask0_T_47, + _mask0_T_46, + |(txnSizes_0[4:3]), + _mask0_T_44, + _mask0_T_43, + _mask0_T_42, + |(txnSizes_0[4:2]), + _mask0_T_40, + |(txnSizes_0[4:1]), + |txnSizes_0, + txnSizes_0[4]} + : {txnSizes_0[4], + _mask0_T_52, + _mask0_T_51, + _mask0_T_50, + _mask0_T_49, + _mask0_T_48, + _mask0_T_47, + _mask0_T_46, + |(txnSizes_0[4:3]), + _mask0_T_44, + _mask0_T_43, + _mask0_T_42, + |(txnSizes_0[4:2]), + _mask0_T_40, + |(txnSizes_0[4:1]), + |txnSizes_0}; + wire [15:0] _mask0_T_67 = + io_dbus_addr[1] ? {_mask0_T_63[13:0], _mask0_T_63[15:14]} : _mask0_T_63; + wire [15:0] _mask0_T_71 = + io_dbus_addr[2] ? {_mask0_T_67[11:0], _mask0_T_67[15:12]} : _mask0_T_67; + wire [15:0] wmask0 = + io_dbus_addr[3] ? {_mask0_T_71[7:0], _mask0_T_71[15:8]} : _mask0_T_71; + wire [3:0] _mask1_T_57 = io_dbus_addr[3:0] + txnSizes_0[3:0]; + wire [15:0] _mask1_T_67 = + _mask1_T_57[0] + ? {_mask1_T_54, + _mask1_T_53, + _mask1_T_52, + _mask1_T_51, + _mask1_T_50, + _mask1_T_49, + _mask1_T_48, + |(txnSizes_1[4:3]), + _mask1_T_46, + _mask1_T_45, + _mask1_T_44, + |(txnSizes_1[4:2]), + _mask1_T_42, + |(txnSizes_1[4:1]), + |txnSizes_1, + txnSizes_1[4]} + : {txnSizes_1[4], + _mask1_T_54, + _mask1_T_53, + _mask1_T_52, + _mask1_T_51, + _mask1_T_50, + _mask1_T_49, + _mask1_T_48, + |(txnSizes_1[4:3]), + _mask1_T_46, + _mask1_T_45, + _mask1_T_44, + |(txnSizes_1[4:2]), + _mask1_T_42, + |(txnSizes_1[4:1]), + |txnSizes_1}; + wire [15:0] _mask1_T_71 = + _mask1_T_57[1] ? {_mask1_T_67[13:0], _mask1_T_67[15:14]} : _mask1_T_67; + wire [15:0] _mask1_T_75 = + _mask1_T_57[2] ? {_mask1_T_71[11:0], _mask1_T_71[15:12]} : _mask1_T_71; + wire [15:0] wmask1 = + _mask1_T_57[3] ? {_mask1_T_75[7:0], _mask1_T_75[15:8]} : _mask1_T_75; + wire io_dbus_ready_0 = + io_dbus_write + ? io_axi_write_resp_valid & _writeAddrQ_io_count == 2'h0 + & _writeDataQ_io_count == 2'h0 & _io_dbus_ready_T_11 == txnCount + : io_axi_read_data_valid & io_axi_read_data_bits_last + & _io_dbus_ready_T_11 == txnCount; + wire [15:0] _mask0_T_25 = + io_dbus_addr[0] + ? {_mask0_T_52, + _mask0_T_51, + _mask0_T_50, + _mask0_T_49, + _mask0_T_48, + _mask0_T_47, + _mask0_T_46, + |(txnSizes_0[4:3]), + _mask0_T_44, + _mask0_T_43, + _mask0_T_42, + |(txnSizes_0[4:2]), + _mask0_T_40, + |(txnSizes_0[4:1]), + |txnSizes_0, + txnSizes_0[4]} + : {txnSizes_0[4], + _mask0_T_52, + _mask0_T_51, + _mask0_T_50, + _mask0_T_49, + _mask0_T_48, + _mask0_T_47, + _mask0_T_46, + |(txnSizes_0[4:3]), + _mask0_T_44, + _mask0_T_43, + _mask0_T_42, + |(txnSizes_0[4:2]), + _mask0_T_40, + |(txnSizes_0[4:1]), + |txnSizes_0}; + wire [15:0] _mask0_T_29 = + io_dbus_addr[1] ? {_mask0_T_25[13:0], _mask0_T_25[15:14]} : _mask0_T_25; + wire [15:0] _mask0_T_33 = + io_dbus_addr[2] ? {_mask0_T_29[11:0], _mask0_T_29[15:12]} : _mask0_T_29; + wire [15:0] rmask0 = + io_dbus_addr[3] ? {_mask0_T_33[7:0], _mask0_T_33[15:8]} : _mask0_T_33; + wire [3:0] _mask1_T_17 = io_dbus_addr[3:0] + txnSizes_0[3:0]; + wire [15:0] _mask1_T_27 = + _mask1_T_17[0] + ? {_mask1_T_54, + _mask1_T_53, + _mask1_T_52, + _mask1_T_51, + _mask1_T_50, + _mask1_T_49, + _mask1_T_48, + |(txnSizes_1[4:3]), + _mask1_T_46, + _mask1_T_45, + _mask1_T_44, + |(txnSizes_1[4:2]), + _mask1_T_42, + |(txnSizes_1[4:1]), + |txnSizes_1, + txnSizes_1[4]} + : {txnSizes_1[4], + _mask1_T_54, + _mask1_T_53, + _mask1_T_52, + _mask1_T_51, + _mask1_T_50, + _mask1_T_49, + _mask1_T_48, + |(txnSizes_1[4:3]), + _mask1_T_46, + _mask1_T_45, + _mask1_T_44, + |(txnSizes_1[4:2]), + _mask1_T_42, + |(txnSizes_1[4:1]), + |txnSizes_1}; + wire [15:0] _mask1_T_31 = + _mask1_T_17[1] ? {_mask1_T_27[13:0], _mask1_T_27[15:14]} : _mask1_T_27; + wire [15:0] _mask1_T_35 = + _mask1_T_17[2] ? {_mask1_T_31[11:0], _mask1_T_31[15:12]} : _mask1_T_31; + wire [15:0] rmask1 = + _mask1_T_17[3] ? {_mask1_T_35[7:0], _mask1_T_35[15:8]} : _mask1_T_35; + wire [15:0] rbitmask = + crossLineBoundary + ? (transactionsCompleted == 2'h1 + ? rmask1 + : transactionsCompleted == 2'h0 ? rmask0 : 16'h0) + : rmask1 == 16'h0 | ~io_axi_read_data_bits_last ? rmask0 : rmask1; + wire [127:0] rbytemask = + {{8{rbitmask[15]}}, + {8{rbitmask[14]}}, + {8{rbitmask[13]}}, + {8{rbitmask[12]}}, + {8{rbitmask[11]}}, + {8{rbitmask[10]}}, + {8{rbitmask[9]}}, + {8{rbitmask[8]}}, + {8{rbitmask[7]}}, + {8{rbitmask[6]}}, + {8{rbitmask[5]}}, + {8{rbitmask[4]}}, + {8{rbitmask[3]}}, + {8{rbitmask[2]}}, + {8{rbitmask[1]}}, + {8{rbitmask[0]}}}; + always @(posedge clock or posedge reset) begin + if (reset) begin + txnActive <= 1'h0; + sdata <= 128'h0; + transactionsCompleted <= 2'h0; + end + else begin + txnActive <= ~(io_dbus_valid & io_dbus_ready_0) & (io_dbus_valid | txnActive); + if (io_axi_read_data_valid) + sdata <= sdata & ~rbytemask | io_axi_read_data_bits_data & rbytemask; + else if (newTxn) + sdata <= 128'h0; + if (newTxn) + transactionsCompleted <= 2'h0; + else if (txnActive & io_dbus_write & io_axi_write_resp_valid | txnActive + & ~io_dbus_write & io_axi_read_data_valid) + transactionsCompleted <= _io_dbus_ready_T_11; + end + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:4]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin + _RANDOM[i] = `RANDOM; + end + txnActive = _RANDOM[3'h0][0]; + sdata = + {_RANDOM[3'h0][31:1], + _RANDOM[3'h1], + _RANDOM[3'h2], + _RANDOM[3'h3], + _RANDOM[3'h4][0]}; + transactionsCompleted = _RANDOM[3'h4][2:1]; + `endif // RANDOMIZE_REG_INIT + if (reset) begin + txnActive = 1'h0; + sdata = 128'h0; + transactionsCompleted = 2'h0; + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + FifoX_1 readAddrQ ( + .clock (clock), + .reset (reset), + .io_in_valid (newTxn & ~io_dbus_write), + .io_in_bits_0_bits_addr (io_dbus_addr), + .io_in_bits_0_bits_len ({7'h0, (|misalignment) & _crossLineBoundary_T_4 < 32'h11}), + .io_in_bits_0_bits_size + (io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] + ? 3'h2 + : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), + .io_in_bits_1_valid (crossLineBoundary), + .io_in_bits_1_bits_addr (io_dbus_addr + 32'h10 & 32'hFFFFFFF0), + .io_in_bits_1_bits_size + (io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] + ? 3'h2 + : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), + .io_out_ready (io_axi_read_addr_ready & _readAddrQ_io_out_valid), + .io_out_valid (_readAddrQ_io_out_valid), + .io_out_bits_addr (io_axi_read_addr_bits_addr), + .io_out_bits_prot (io_axi_read_addr_bits_prot), + .io_out_bits_id (io_axi_read_addr_bits_id), + .io_out_bits_len (io_axi_read_addr_bits_len), + .io_out_bits_size (io_axi_read_addr_bits_size), + .io_out_bits_burst (io_axi_read_addr_bits_burst), + .io_out_bits_lock (io_axi_read_addr_bits_lock), + .io_out_bits_cache (io_axi_read_addr_bits_cache), + .io_out_bits_qos (io_axi_read_addr_bits_qos), + .io_out_bits_region (io_axi_read_addr_bits_region), + .io_count (_readAddrQ_io_count) + ); + FifoX_1 writeAddrQ ( + .clock (clock), + .reset (reset), + .io_in_valid (writeDataQ_io_in_valid), + .io_in_bits_0_bits_addr (writeAddrQ_io_in_bits_0_bits_addr), + .io_in_bits_0_bits_len (8'h0), + .io_in_bits_0_bits_size + (io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] + ? 3'h2 + : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), + .io_in_bits_1_valid (txnCount[1]), + .io_in_bits_1_bits_addr (writeAddrQ_io_in_bits_0_bits_addr + {27'h0, io_dbus_size}), + .io_in_bits_1_bits_size + (io_dbus_size[0] + ? 3'h0 + : io_dbus_size[1] + ? 3'h1 + : io_dbus_size[2] + ? 3'h2 + : io_dbus_size[3] ? 3'h3 : {2'h2, ~(io_dbus_size[4])}), + .io_out_ready (io_axi_write_addr_ready & _writeAddrQ_io_out_valid), + .io_out_valid (_writeAddrQ_io_out_valid), + .io_out_bits_addr (io_axi_write_addr_bits_addr), + .io_out_bits_prot (io_axi_write_addr_bits_prot), + .io_out_bits_id (io_axi_write_addr_bits_id), + .io_out_bits_len (io_axi_write_addr_bits_len), + .io_out_bits_size (io_axi_write_addr_bits_size), + .io_out_bits_burst (io_axi_write_addr_bits_burst), + .io_out_bits_lock (io_axi_write_addr_bits_lock), + .io_out_bits_cache (io_axi_write_addr_bits_cache), + .io_out_bits_qos (io_axi_write_addr_bits_qos), + .io_out_bits_region (io_axi_write_addr_bits_region), + .io_count (_writeAddrQ_io_count) + ); + FifoX_3 writeDataQ ( + .clock (clock), + .reset (reset), + .io_in_valid (writeDataQ_io_in_valid), + .io_in_bits_0_bits_data + (io_dbus_wdata + & {{8{wmask0[15]}}, + {8{wmask0[14]}}, + {8{wmask0[13]}}, + {8{wmask0[12]}}, + {8{wmask0[11]}}, + {8{wmask0[10]}}, + {8{wmask0[9]}}, + {8{wmask0[8]}}, + {8{wmask0[7]}}, + {8{wmask0[6]}}, + {8{wmask0[5]}}, + {8{wmask0[4]}}, + {8{wmask0[3]}}, + {8{wmask0[2]}}, + {8{wmask0[1]}}, + {8{wmask0[0]}}}), + .io_in_bits_0_bits_strb (wmask0), + .io_in_bits_1_valid (txnCount[1]), + .io_in_bits_1_bits_data + (io_dbus_wdata + & {{8{wmask1[15]}}, + {8{wmask1[14]}}, + {8{wmask1[13]}}, + {8{wmask1[12]}}, + {8{wmask1[11]}}, + {8{wmask1[10]}}, + {8{wmask1[9]}}, + {8{wmask1[8]}}, + {8{wmask1[7]}}, + {8{wmask1[6]}}, + {8{wmask1[5]}}, + {8{wmask1[4]}}, + {8{wmask1[3]}}, + {8{wmask1[2]}}, + {8{wmask1[1]}}, + {8{wmask1[0]}}}), + .io_in_bits_1_bits_strb (wmask1), + .io_out_ready (io_axi_write_data_ready & _writeDataQ_io_out_valid), + .io_out_valid (_writeDataQ_io_out_valid), + .io_out_bits_data (io_axi_write_data_bits_data), + .io_out_bits_last (io_axi_write_data_bits_last), + .io_out_bits_strb (io_axi_write_data_bits_strb), + .io_count (_writeDataQ_io_count) + ); + assign io_dbus_ready = io_dbus_ready_0; + assign io_dbus_rdata = sdata; + assign io_axi_write_addr_valid = _writeAddrQ_io_out_valid; + assign io_axi_write_data_valid = _writeDataQ_io_out_valid; + assign io_axi_write_resp_ready = io_axi_write_resp_valid; + assign io_axi_read_addr_valid = _readAddrQ_io_out_valid; + assign io_axi_read_data_ready = io_axi_read_data_valid; + assign io_fault_valid = + io_axi_write_resp_valid + ? (|io_axi_write_resp_bits_resp) & io_axi_write_resp_bits_resp != 2'h1 + : io_axi_read_data_valid & io_axi_read_data_bits_last + & (|io_axi_read_data_bits_resp) & io_axi_read_data_bits_resp != 2'h1; + assign io_fault_bits_write = io_axi_write_resp_valid; + assign io_fault_bits_addr = io_dbus_addr; + assign io_fault_bits_epc = io_dbus_pc; +endmodule + +module CoreMiniAxi( + input io_aclk, + io_aresetn, + output io_axi_slave_write_addr_ready, + input io_axi_slave_write_addr_valid, + input [31:0] io_axi_slave_write_addr_bits_addr, + input [2:0] io_axi_slave_write_addr_bits_prot, + input [5:0] io_axi_slave_write_addr_bits_id, + input [7:0] io_axi_slave_write_addr_bits_len, + input [2:0] io_axi_slave_write_addr_bits_size, + input [1:0] io_axi_slave_write_addr_bits_burst, + input io_axi_slave_write_addr_bits_lock, + input [3:0] io_axi_slave_write_addr_bits_cache, + io_axi_slave_write_addr_bits_qos, + io_axi_slave_write_addr_bits_region, + output io_axi_slave_write_data_ready, + input io_axi_slave_write_data_valid, + input [127:0] io_axi_slave_write_data_bits_data, + input io_axi_slave_write_data_bits_last, + input [15:0] io_axi_slave_write_data_bits_strb, + input io_axi_slave_write_resp_ready, + output io_axi_slave_write_resp_valid, + output [5:0] io_axi_slave_write_resp_bits_id, + output [1:0] io_axi_slave_write_resp_bits_resp, + output io_axi_slave_read_addr_ready, + input io_axi_slave_read_addr_valid, + input [31:0] io_axi_slave_read_addr_bits_addr, + input [2:0] io_axi_slave_read_addr_bits_prot, + input [5:0] io_axi_slave_read_addr_bits_id, + input [7:0] io_axi_slave_read_addr_bits_len, + input [2:0] io_axi_slave_read_addr_bits_size, + input [1:0] io_axi_slave_read_addr_bits_burst, + input io_axi_slave_read_addr_bits_lock, + input [3:0] io_axi_slave_read_addr_bits_cache, + io_axi_slave_read_addr_bits_qos, + io_axi_slave_read_addr_bits_region, + input io_axi_slave_read_data_ready, + output io_axi_slave_read_data_valid, + output [127:0] io_axi_slave_read_data_bits_data, + output [5:0] io_axi_slave_read_data_bits_id, + output [1:0] io_axi_slave_read_data_bits_resp, + output io_axi_slave_read_data_bits_last, + input io_axi_master_write_addr_ready, + output io_axi_master_write_addr_valid, + output [31:0] io_axi_master_write_addr_bits_addr, + output [2:0] io_axi_master_write_addr_bits_prot, + output [5:0] io_axi_master_write_addr_bits_id, + output [7:0] io_axi_master_write_addr_bits_len, + output [2:0] io_axi_master_write_addr_bits_size, + output [1:0] io_axi_master_write_addr_bits_burst, + output io_axi_master_write_addr_bits_lock, + output [3:0] io_axi_master_write_addr_bits_cache, + io_axi_master_write_addr_bits_qos, + io_axi_master_write_addr_bits_region, + input io_axi_master_write_data_ready, + output io_axi_master_write_data_valid, + output [127:0] io_axi_master_write_data_bits_data, + output io_axi_master_write_data_bits_last, + output [15:0] io_axi_master_write_data_bits_strb, + output io_axi_master_write_resp_ready, + input io_axi_master_write_resp_valid, + input [5:0] io_axi_master_write_resp_bits_id, + input [1:0] io_axi_master_write_resp_bits_resp, + input io_axi_master_read_addr_ready, + output io_axi_master_read_addr_valid, + output [31:0] io_axi_master_read_addr_bits_addr, + output [2:0] io_axi_master_read_addr_bits_prot, + output [5:0] io_axi_master_read_addr_bits_id, + output [7:0] io_axi_master_read_addr_bits_len, + output [2:0] io_axi_master_read_addr_bits_size, + output [1:0] io_axi_master_read_addr_bits_burst, + output io_axi_master_read_addr_bits_lock, + output [3:0] io_axi_master_read_addr_bits_cache, + io_axi_master_read_addr_bits_qos, + io_axi_master_read_addr_bits_region, + output io_axi_master_read_data_ready, + input io_axi_master_read_data_valid, + input [127:0] io_axi_master_read_data_bits_data, + input [5:0] io_axi_master_read_data_bits_id, + input [1:0] io_axi_master_read_data_bits_resp, + input io_axi_master_read_data_bits_last, + output io_halted, + io_fault, + io_wfi, + input io_irq, + output [3:0] io_debug_en, + output [31:0] io_debug_addr_0, + io_debug_addr_1, + io_debug_addr_2, + io_debug_addr_3, + io_debug_inst_0, + io_debug_inst_1, + io_debug_inst_2, + io_debug_inst_3, + io_debug_cycles, + output io_debug_dbus_valid, + output [31:0] io_debug_dbus_bits_addr, + output [127:0] io_debug_dbus_bits_wdata, + output io_debug_dbus_bits_write, + io_debug_dispatch_0_instFire, + output [31:0] io_debug_dispatch_0_instAddr, + io_debug_dispatch_0_instInst, + output io_debug_dispatch_1_instFire, + output [31:0] io_debug_dispatch_1_instAddr, + io_debug_dispatch_1_instInst, + output io_debug_dispatch_2_instFire, + output [31:0] io_debug_dispatch_2_instAddr, + io_debug_dispatch_2_instInst, + output io_debug_dispatch_3_instFire, + output [31:0] io_debug_dispatch_3_instAddr, + io_debug_dispatch_3_instInst, + output io_debug_regfile_writeAddr_0_valid, + output [4:0] io_debug_regfile_writeAddr_0_bits, + output io_debug_regfile_writeAddr_1_valid, + output [4:0] io_debug_regfile_writeAddr_1_bits, + output io_debug_regfile_writeAddr_2_valid, + output [4:0] io_debug_regfile_writeAddr_2_bits, + output io_debug_regfile_writeAddr_3_valid, + output [4:0] io_debug_regfile_writeAddr_3_bits, + output io_debug_regfile_writeData_0_valid, + output [4:0] io_debug_regfile_writeData_0_bits_addr, + output [31:0] io_debug_regfile_writeData_0_bits_data, + output io_debug_regfile_writeData_1_valid, + output [4:0] io_debug_regfile_writeData_1_bits_addr, + output [31:0] io_debug_regfile_writeData_1_bits_data, + output io_debug_regfile_writeData_2_valid, + output [4:0] io_debug_regfile_writeData_2_bits_addr, + output [31:0] io_debug_regfile_writeData_2_bits_data, + output io_debug_regfile_writeData_3_valid, + output [4:0] io_debug_regfile_writeData_3_bits_addr, + output [31:0] io_debug_regfile_writeData_3_bits_data, + output io_debug_regfile_writeData_4_valid, + output [4:0] io_debug_regfile_writeData_4_bits_addr, + output [31:0] io_debug_regfile_writeData_4_bits_data, + output io_debug_regfile_writeData_5_valid, + output [4:0] io_debug_regfile_writeData_5_bits_addr, + output [31:0] io_debug_regfile_writeData_5_bits_data, + output io_debug_float_writeAddr_valid, + output [4:0] io_debug_float_writeAddr_bits, + output io_debug_float_writeData_0_valid, + output [31:0] io_debug_float_writeData_0_bits_addr, + io_debug_float_writeData_0_bits_data, + output io_debug_float_writeData_1_valid, + output [31:0] io_debug_float_writeData_1_bits_addr, + io_debug_float_writeData_1_bits_data, + output io_slog_valid, + output [4:0] io_slog_addr, + output [31:0] io_slog_data, + input io_te +); + + wire _ebus2axi_io_dbus_ready; + wire [127:0] _ebus2axi_io_dbus_rdata; + wire _ebus2axi_io_fault_valid; + wire _ebus2axi_io_fault_bits_write; + wire [31:0] _ebus2axi_io_fault_bits_addr; + wire [31:0] _ebus2axi_io_fault_bits_epc; + wire _axiSlave_io_axi_write_addr_ready; + wire _axiSlave_io_axi_write_data_ready; + wire _axiSlave_io_axi_write_resp_valid; + wire _axiSlave_io_axi_read_addr_ready; + wire _axiSlave_io_axi_read_data_valid; + wire _axiSlave_io_fabric_readDataAddr_valid; + wire [31:0] _axiSlave_io_fabric_readDataAddr_bits; + wire _axiSlave_io_fabric_writeDataAddr_valid; + wire [31:0] _axiSlave_io_fabric_writeDataAddr_bits; + wire [127:0] _axiSlave_io_fabric_writeDataBits; + wire [15:0] _axiSlave_io_fabric_writeDataStrb; + wire _fabricMux_io_source_readData_valid; + wire [127:0] _fabricMux_io_source_readData_bits; + wire _fabricMux_io_source_writeResp; + wire _fabricMux_io_fabricBusy; + wire _fabricMux_io_ports_0_readDataAddr_valid; + wire [31:0] _fabricMux_io_ports_0_readDataAddr_bits; + wire _fabricMux_io_ports_0_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_0_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_0_writeDataBits; + wire [15:0] _fabricMux_io_ports_0_writeDataStrb; + wire _fabricMux_io_ports_1_readDataAddr_valid; + wire [31:0] _fabricMux_io_ports_1_readDataAddr_bits; + wire _fabricMux_io_ports_1_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_1_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_1_writeDataBits; + wire [15:0] _fabricMux_io_ports_1_writeDataStrb; + wire [31:0] _fabricMux_io_ports_2_readDataAddr_bits; + wire _fabricMux_io_ports_2_writeDataAddr_valid; + wire [31:0] _fabricMux_io_ports_2_writeDataAddr_bits; + wire [127:0] _fabricMux_io_ports_2_writeDataBits; + wire [127:0] _dtcmArbiter_io_source_0_readData_bits; + wire _dtcmArbiter_io_source_1_readData_valid; + wire [127:0] _dtcmArbiter_io_source_1_readData_bits; + wire _dtcmArbiter_io_fabricBusy; + wire _dtcmArbiter_io_port_readDataAddr_valid; + wire [31:0] _dtcmArbiter_io_port_readDataAddr_bits; + wire _dtcmArbiter_io_port_writeDataAddr_valid; + wire [31:0] _dtcmArbiter_io_port_writeDataAddr_bits; + wire [127:0] _dtcmArbiter_io_port_writeDataBits; + wire [15:0] _dtcmArbiter_io_port_writeDataStrb; + wire _dtcmWrapper_io_fabric_readData_valid; + wire [127:0] _dtcmWrapper_io_fabric_readData_bits; + wire [10:0] _dtcmWrapper_io_sram_address; + wire _dtcmWrapper_io_sram_enable; + wire _dtcmWrapper_io_sram_isWrite; + wire [7:0] _dtcmWrapper_io_sram_writeData_0; + wire [7:0] _dtcmWrapper_io_sram_writeData_1; + wire [7:0] _dtcmWrapper_io_sram_writeData_2; + wire [7:0] _dtcmWrapper_io_sram_writeData_3; + wire [7:0] _dtcmWrapper_io_sram_writeData_4; + wire [7:0] _dtcmWrapper_io_sram_writeData_5; + wire [7:0] _dtcmWrapper_io_sram_writeData_6; + wire [7:0] _dtcmWrapper_io_sram_writeData_7; + wire [7:0] _dtcmWrapper_io_sram_writeData_8; + wire [7:0] _dtcmWrapper_io_sram_writeData_9; + wire [7:0] _dtcmWrapper_io_sram_writeData_10; + wire [7:0] _dtcmWrapper_io_sram_writeData_11; + wire [7:0] _dtcmWrapper_io_sram_writeData_12; + wire [7:0] _dtcmWrapper_io_sram_writeData_13; + wire [7:0] _dtcmWrapper_io_sram_writeData_14; + wire [7:0] _dtcmWrapper_io_sram_writeData_15; + wire _dtcmWrapper_io_sram_mask_0; + wire _dtcmWrapper_io_sram_mask_1; + wire _dtcmWrapper_io_sram_mask_2; + wire _dtcmWrapper_io_sram_mask_3; + wire _dtcmWrapper_io_sram_mask_4; + wire _dtcmWrapper_io_sram_mask_5; + wire _dtcmWrapper_io_sram_mask_6; + wire _dtcmWrapper_io_sram_mask_7; + wire _dtcmWrapper_io_sram_mask_8; + wire _dtcmWrapper_io_sram_mask_9; + wire _dtcmWrapper_io_sram_mask_10; + wire _dtcmWrapper_io_sram_mask_11; + wire _dtcmWrapper_io_sram_mask_12; + wire _dtcmWrapper_io_sram_mask_13; + wire _dtcmWrapper_io_sram_mask_14; + wire _dtcmWrapper_io_sram_mask_15; + wire [7:0] _dtcm_io_rdata_0; + wire [7:0] _dtcm_io_rdata_1; + wire [7:0] _dtcm_io_rdata_2; + wire [7:0] _dtcm_io_rdata_3; + wire [7:0] _dtcm_io_rdata_4; + wire [7:0] _dtcm_io_rdata_5; + wire [7:0] _dtcm_io_rdata_6; + wire [7:0] _dtcm_io_rdata_7; + wire [7:0] _dtcm_io_rdata_8; + wire [7:0] _dtcm_io_rdata_9; + wire [7:0] _dtcm_io_rdata_10; + wire [7:0] _dtcm_io_rdata_11; + wire [7:0] _dtcm_io_rdata_12; + wire [7:0] _dtcm_io_rdata_13; + wire [7:0] _dtcm_io_rdata_14; + wire [7:0] _dtcm_io_rdata_15; + wire [127:0] _itcmArbiter_io_source_0_readData_bits; + wire _itcmArbiter_io_source_1_readData_valid; + wire [127:0] _itcmArbiter_io_source_1_readData_bits; + wire _itcmArbiter_io_fabricBusy; + wire _itcmArbiter_io_port_readDataAddr_valid; + wire [31:0] _itcmArbiter_io_port_readDataAddr_bits; + wire _itcmArbiter_io_port_writeDataAddr_valid; + wire [31:0] _itcmArbiter_io_port_writeDataAddr_bits; + wire [127:0] _itcmArbiter_io_port_writeDataBits; + wire [15:0] _itcmArbiter_io_port_writeDataStrb; + wire _itcmWrapper_io_fabric_readData_valid; + wire [127:0] _itcmWrapper_io_fabric_readData_bits; + wire [8:0] _itcmWrapper_io_sram_address; + wire _itcmWrapper_io_sram_enable; + wire _itcmWrapper_io_sram_isWrite; + wire [7:0] _itcmWrapper_io_sram_writeData_0; + wire [7:0] _itcmWrapper_io_sram_writeData_1; + wire [7:0] _itcmWrapper_io_sram_writeData_2; + wire [7:0] _itcmWrapper_io_sram_writeData_3; + wire [7:0] _itcmWrapper_io_sram_writeData_4; + wire [7:0] _itcmWrapper_io_sram_writeData_5; + wire [7:0] _itcmWrapper_io_sram_writeData_6; + wire [7:0] _itcmWrapper_io_sram_writeData_7; + wire [7:0] _itcmWrapper_io_sram_writeData_8; + wire [7:0] _itcmWrapper_io_sram_writeData_9; + wire [7:0] _itcmWrapper_io_sram_writeData_10; + wire [7:0] _itcmWrapper_io_sram_writeData_11; + wire [7:0] _itcmWrapper_io_sram_writeData_12; + wire [7:0] _itcmWrapper_io_sram_writeData_13; + wire [7:0] _itcmWrapper_io_sram_writeData_14; + wire [7:0] _itcmWrapper_io_sram_writeData_15; + wire _itcmWrapper_io_sram_mask_0; + wire _itcmWrapper_io_sram_mask_1; + wire _itcmWrapper_io_sram_mask_2; + wire _itcmWrapper_io_sram_mask_3; + wire _itcmWrapper_io_sram_mask_4; + wire _itcmWrapper_io_sram_mask_5; + wire _itcmWrapper_io_sram_mask_6; + wire _itcmWrapper_io_sram_mask_7; + wire _itcmWrapper_io_sram_mask_8; + wire _itcmWrapper_io_sram_mask_9; + wire _itcmWrapper_io_sram_mask_10; + wire _itcmWrapper_io_sram_mask_11; + wire _itcmWrapper_io_sram_mask_12; + wire _itcmWrapper_io_sram_mask_13; + wire _itcmWrapper_io_sram_mask_14; + wire _itcmWrapper_io_sram_mask_15; + wire [7:0] _itcm_io_rdata_0; + wire [7:0] _itcm_io_rdata_1; + wire [7:0] _itcm_io_rdata_2; + wire [7:0] _itcm_io_rdata_3; + wire [7:0] _itcm_io_rdata_4; + wire [7:0] _itcm_io_rdata_5; + wire [7:0] _itcm_io_rdata_6; + wire [7:0] _itcm_io_rdata_7; + wire [7:0] _itcm_io_rdata_8; + wire [7:0] _itcm_io_rdata_9; + wire [7:0] _itcm_io_rdata_10; + wire [7:0] _itcm_io_rdata_11; + wire [7:0] _itcm_io_rdata_12; + wire [7:0] _itcm_io_rdata_13; + wire [7:0] _itcm_io_rdata_14; + wire [7:0] _itcm_io_rdata_15; + wire [31:0] _core_io_csr_out_value_0; + wire [31:0] _core_io_csr_out_value_1; + wire [31:0] _core_io_csr_out_value_2; + wire [31:0] _core_io_csr_out_value_3; + wire [31:0] _core_io_csr_out_value_4; + wire [31:0] _core_io_csr_out_value_5; + wire [31:0] _core_io_csr_out_value_6; + wire [31:0] _core_io_csr_out_value_7; + wire _core_io_halted; + wire _core_io_fault; + wire _core_io_wfi; + wire _core_io_ibus_valid; + wire [31:0] _core_io_ibus_addr; + wire _core_io_dbus_valid; + wire _core_io_dbus_write; + wire [31:0] _core_io_dbus_addr; + wire [127:0] _core_io_dbus_wdata; + wire [15:0] _core_io_dbus_wmask; + wire _core_io_ebus_dbus_valid; + wire _core_io_ebus_dbus_write; + wire [31:0] _core_io_ebus_dbus_pc; + wire [31:0] _core_io_ebus_dbus_addr; + wire [4:0] _core_io_ebus_dbus_size; + wire [127:0] _core_io_ebus_dbus_wdata; + wire _cg_clk_o; + wire _csr_io_fabric_readData_valid; + wire [127:0] _csr_io_fabric_readData_bits; + wire _csr_io_fabric_writeResp; + wire _csr_io_reset; + wire _csr_io_cg; + wire [31:0] _csr_io_pcStart; + wire _rst_sync_clk_o; + wire _rst_sync_rstn_o; + wire _global_reset_T_2 = ~(io_te ? io_aresetn : _rst_sync_rstn_o); + reg axiSlaveEnable; + always @(posedge _rst_sync_clk_o or posedge _global_reset_T_2) begin + if (_global_reset_T_2) + axiSlaveEnable <= 1'h0; + else + axiSlaveEnable <= 1'h1; + end // always @(posedge, posedge) + `ifdef ENABLE_INITIAL_REG_ + `ifdef FIRRTL_BEFORE_INITIAL + `FIRRTL_BEFORE_INITIAL + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:0]; + initial begin + `ifdef INIT_RANDOM_PROLOG_ + `INIT_RANDOM_PROLOG_ + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT + _RANDOM[/*Zero width*/ 1'b0] = `RANDOM; + axiSlaveEnable = _RANDOM[/*Zero width*/ 1'b0][0]; + `endif // RANDOMIZE_REG_INIT + if (_global_reset_T_2) + axiSlaveEnable = 1'h0; + end // initial + `ifdef FIRRTL_AFTER_INITIAL + `FIRRTL_AFTER_INITIAL + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + RstSync rst_sync ( + .clk_i (io_aclk), + .rstn_i (io_aresetn), + .clk_en (1'h1), + .te (io_te), + .clk_o (_rst_sync_clk_o), + .rstn_o (_rst_sync_rstn_o) + ); + CoreCSR csr ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_fabric_readDataAddr_bits (_fabricMux_io_ports_2_readDataAddr_bits), + .io_fabric_readData_valid (_csr_io_fabric_readData_valid), + .io_fabric_readData_bits (_csr_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid (_fabricMux_io_ports_2_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits (_fabricMux_io_ports_2_writeDataAddr_bits), + .io_fabric_writeDataBits (_fabricMux_io_ports_2_writeDataBits), + .io_fabric_writeResp (_csr_io_fabric_writeResp), + .io_reset (_csr_io_reset), + .io_cg (_csr_io_cg), + .io_pcStart (_csr_io_pcStart), + .io_halted (_core_io_halted), + .io_fault (_core_io_fault), + .io_coralnpu_csr_value_0 (_core_io_csr_out_value_0), + .io_coralnpu_csr_value_1 (_core_io_csr_out_value_1), + .io_coralnpu_csr_value_2 (_core_io_csr_out_value_2), + .io_coralnpu_csr_value_3 (_core_io_csr_out_value_3), + .io_coralnpu_csr_value_4 (_core_io_csr_out_value_4), + .io_coralnpu_csr_value_5 (_core_io_csr_out_value_5), + .io_coralnpu_csr_value_6 (_core_io_csr_out_value_6), + .io_coralnpu_csr_value_7 (_core_io_csr_out_value_7) + ); + ClockGate cg ( + .clk_i (_rst_sync_clk_o), + .enable (io_irq | ~_csr_io_cg & ~_core_io_wfi), + .te (io_te), + .clk_o (_cg_clk_o) + ); + CoreMini core ( + .clock (_cg_clk_o), + .reset (io_te ? ~io_aresetn : _csr_io_reset), + .io_csr_in_value_0 (_csr_io_pcStart), + .io_csr_out_value_0 (_core_io_csr_out_value_0), + .io_csr_out_value_1 (_core_io_csr_out_value_1), + .io_csr_out_value_2 (_core_io_csr_out_value_2), + .io_csr_out_value_3 (_core_io_csr_out_value_3), + .io_csr_out_value_4 (_core_io_csr_out_value_4), + .io_csr_out_value_5 (_core_io_csr_out_value_5), + .io_csr_out_value_6 (_core_io_csr_out_value_6), + .io_csr_out_value_7 (_core_io_csr_out_value_7), + .io_halted (_core_io_halted), + .io_fault (_core_io_fault), + .io_wfi (_core_io_wfi), + .io_irq (io_irq), + .io_ibus_valid (_core_io_ibus_valid), + .io_ibus_addr (_core_io_ibus_addr), + .io_ibus_rdata (_itcmArbiter_io_source_0_readData_bits), + .io_ibus_fault_valid + (_core_io_ibus_valid & (|(_core_io_ibus_addr[31:13]))), + .io_ibus_fault_bits_epc (_core_io_ibus_addr), + .io_dbus_valid (_core_io_dbus_valid), + .io_dbus_write (_core_io_dbus_write), + .io_dbus_addr (_core_io_dbus_addr), + .io_dbus_wdata (_core_io_dbus_wdata), + .io_dbus_wmask (_core_io_dbus_wmask), + .io_dbus_rdata (_dtcmArbiter_io_source_0_readData_bits), + .io_ebus_dbus_valid (_core_io_ebus_dbus_valid), + .io_ebus_dbus_ready (_ebus2axi_io_dbus_ready), + .io_ebus_dbus_write (_core_io_ebus_dbus_write), + .io_ebus_dbus_pc (_core_io_ebus_dbus_pc), + .io_ebus_dbus_addr (_core_io_ebus_dbus_addr), + .io_ebus_dbus_size (_core_io_ebus_dbus_size), + .io_ebus_dbus_wdata (_core_io_ebus_dbus_wdata), + .io_ebus_dbus_rdata (_ebus2axi_io_dbus_rdata), + .io_ebus_fault_valid (_ebus2axi_io_fault_valid), + .io_ebus_fault_bits_write (_ebus2axi_io_fault_bits_write), + .io_ebus_fault_bits_addr (_ebus2axi_io_fault_bits_addr), + .io_ebus_fault_bits_epc (_ebus2axi_io_fault_bits_epc), + .io_slog_valid (io_slog_valid), + .io_slog_addr (io_slog_addr), + .io_slog_data (io_slog_data), + .io_debug_en (io_debug_en), + .io_debug_addr_0 (io_debug_addr_0), + .io_debug_addr_1 (io_debug_addr_1), + .io_debug_addr_2 (io_debug_addr_2), + .io_debug_addr_3 (io_debug_addr_3), + .io_debug_inst_0 (io_debug_inst_0), + .io_debug_inst_1 (io_debug_inst_1), + .io_debug_inst_2 (io_debug_inst_2), + .io_debug_inst_3 (io_debug_inst_3), + .io_debug_cycles (io_debug_cycles), + .io_debug_dbus_valid (io_debug_dbus_valid), + .io_debug_dbus_bits_addr (io_debug_dbus_bits_addr), + .io_debug_dbus_bits_wdata (io_debug_dbus_bits_wdata), + .io_debug_dbus_bits_write (io_debug_dbus_bits_write), + .io_debug_dispatch_0_instFire (io_debug_dispatch_0_instFire), + .io_debug_dispatch_0_instAddr (io_debug_dispatch_0_instAddr), + .io_debug_dispatch_0_instInst (io_debug_dispatch_0_instInst), + .io_debug_dispatch_1_instFire (io_debug_dispatch_1_instFire), + .io_debug_dispatch_1_instAddr (io_debug_dispatch_1_instAddr), + .io_debug_dispatch_1_instInst (io_debug_dispatch_1_instInst), + .io_debug_dispatch_2_instFire (io_debug_dispatch_2_instFire), + .io_debug_dispatch_2_instAddr (io_debug_dispatch_2_instAddr), + .io_debug_dispatch_2_instInst (io_debug_dispatch_2_instInst), + .io_debug_dispatch_3_instFire (io_debug_dispatch_3_instFire), + .io_debug_dispatch_3_instAddr (io_debug_dispatch_3_instAddr), + .io_debug_dispatch_3_instInst (io_debug_dispatch_3_instInst), + .io_debug_regfile_writeAddr_0_valid (io_debug_regfile_writeAddr_0_valid), + .io_debug_regfile_writeAddr_0_bits (io_debug_regfile_writeAddr_0_bits), + .io_debug_regfile_writeAddr_1_valid (io_debug_regfile_writeAddr_1_valid), + .io_debug_regfile_writeAddr_1_bits (io_debug_regfile_writeAddr_1_bits), + .io_debug_regfile_writeAddr_2_valid (io_debug_regfile_writeAddr_2_valid), + .io_debug_regfile_writeAddr_2_bits (io_debug_regfile_writeAddr_2_bits), + .io_debug_regfile_writeAddr_3_valid (io_debug_regfile_writeAddr_3_valid), + .io_debug_regfile_writeAddr_3_bits (io_debug_regfile_writeAddr_3_bits), + .io_debug_regfile_writeData_0_valid (io_debug_regfile_writeData_0_valid), + .io_debug_regfile_writeData_0_bits_addr (io_debug_regfile_writeData_0_bits_addr), + .io_debug_regfile_writeData_0_bits_data (io_debug_regfile_writeData_0_bits_data), + .io_debug_regfile_writeData_1_valid (io_debug_regfile_writeData_1_valid), + .io_debug_regfile_writeData_1_bits_addr (io_debug_regfile_writeData_1_bits_addr), + .io_debug_regfile_writeData_1_bits_data (io_debug_regfile_writeData_1_bits_data), + .io_debug_regfile_writeData_2_valid (io_debug_regfile_writeData_2_valid), + .io_debug_regfile_writeData_2_bits_addr (io_debug_regfile_writeData_2_bits_addr), + .io_debug_regfile_writeData_2_bits_data (io_debug_regfile_writeData_2_bits_data), + .io_debug_regfile_writeData_3_valid (io_debug_regfile_writeData_3_valid), + .io_debug_regfile_writeData_3_bits_addr (io_debug_regfile_writeData_3_bits_addr), + .io_debug_regfile_writeData_3_bits_data (io_debug_regfile_writeData_3_bits_data), + .io_debug_regfile_writeData_4_valid (io_debug_regfile_writeData_4_valid), + .io_debug_regfile_writeData_4_bits_addr (io_debug_regfile_writeData_4_bits_addr), + .io_debug_regfile_writeData_4_bits_data (io_debug_regfile_writeData_4_bits_data), + .io_debug_regfile_writeData_5_valid (io_debug_regfile_writeData_5_valid), + .io_debug_regfile_writeData_5_bits_addr (io_debug_regfile_writeData_5_bits_addr), + .io_debug_regfile_writeData_5_bits_data (io_debug_regfile_writeData_5_bits_data), + .io_debug_float_writeAddr_valid (io_debug_float_writeAddr_valid), + .io_debug_float_writeAddr_bits (io_debug_float_writeAddr_bits), + .io_debug_float_writeData_0_valid (io_debug_float_writeData_0_valid), + .io_debug_float_writeData_0_bits_addr (io_debug_float_writeData_0_bits_addr), + .io_debug_float_writeData_0_bits_data (io_debug_float_writeData_0_bits_data), + .io_debug_float_writeData_1_valid (io_debug_float_writeData_1_valid), + .io_debug_float_writeData_1_bits_addr (io_debug_float_writeData_1_bits_addr), + .io_debug_float_writeData_1_bits_data (io_debug_float_writeData_1_bits_data) + ); + TCM128 itcm ( + .clock (_rst_sync_clk_o), + .io_addr (_itcmWrapper_io_sram_address), + .io_enable (_itcmWrapper_io_sram_enable), + .io_write (_itcmWrapper_io_sram_isWrite), + .io_wdata_0 (_itcmWrapper_io_sram_writeData_0), + .io_wdata_1 (_itcmWrapper_io_sram_writeData_1), + .io_wdata_2 (_itcmWrapper_io_sram_writeData_2), + .io_wdata_3 (_itcmWrapper_io_sram_writeData_3), + .io_wdata_4 (_itcmWrapper_io_sram_writeData_4), + .io_wdata_5 (_itcmWrapper_io_sram_writeData_5), + .io_wdata_6 (_itcmWrapper_io_sram_writeData_6), + .io_wdata_7 (_itcmWrapper_io_sram_writeData_7), + .io_wdata_8 (_itcmWrapper_io_sram_writeData_8), + .io_wdata_9 (_itcmWrapper_io_sram_writeData_9), + .io_wdata_10 (_itcmWrapper_io_sram_writeData_10), + .io_wdata_11 (_itcmWrapper_io_sram_writeData_11), + .io_wdata_12 (_itcmWrapper_io_sram_writeData_12), + .io_wdata_13 (_itcmWrapper_io_sram_writeData_13), + .io_wdata_14 (_itcmWrapper_io_sram_writeData_14), + .io_wdata_15 (_itcmWrapper_io_sram_writeData_15), + .io_wmask_0 (_itcmWrapper_io_sram_mask_0), + .io_wmask_1 (_itcmWrapper_io_sram_mask_1), + .io_wmask_2 (_itcmWrapper_io_sram_mask_2), + .io_wmask_3 (_itcmWrapper_io_sram_mask_3), + .io_wmask_4 (_itcmWrapper_io_sram_mask_4), + .io_wmask_5 (_itcmWrapper_io_sram_mask_5), + .io_wmask_6 (_itcmWrapper_io_sram_mask_6), + .io_wmask_7 (_itcmWrapper_io_sram_mask_7), + .io_wmask_8 (_itcmWrapper_io_sram_mask_8), + .io_wmask_9 (_itcmWrapper_io_sram_mask_9), + .io_wmask_10 (_itcmWrapper_io_sram_mask_10), + .io_wmask_11 (_itcmWrapper_io_sram_mask_11), + .io_wmask_12 (_itcmWrapper_io_sram_mask_12), + .io_wmask_13 (_itcmWrapper_io_sram_mask_13), + .io_wmask_14 (_itcmWrapper_io_sram_mask_14), + .io_wmask_15 (_itcmWrapper_io_sram_mask_15), + .io_rdata_0 (_itcm_io_rdata_0), + .io_rdata_1 (_itcm_io_rdata_1), + .io_rdata_2 (_itcm_io_rdata_2), + .io_rdata_3 (_itcm_io_rdata_3), + .io_rdata_4 (_itcm_io_rdata_4), + .io_rdata_5 (_itcm_io_rdata_5), + .io_rdata_6 (_itcm_io_rdata_6), + .io_rdata_7 (_itcm_io_rdata_7), + .io_rdata_8 (_itcm_io_rdata_8), + .io_rdata_9 (_itcm_io_rdata_9), + .io_rdata_10 (_itcm_io_rdata_10), + .io_rdata_11 (_itcm_io_rdata_11), + .io_rdata_12 (_itcm_io_rdata_12), + .io_rdata_13 (_itcm_io_rdata_13), + .io_rdata_14 (_itcm_io_rdata_14), + .io_rdata_15 (_itcm_io_rdata_15) + ); + SRAM itcmWrapper ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_fabric_readDataAddr_valid (_itcmArbiter_io_port_readDataAddr_valid), + .io_fabric_readDataAddr_bits (_itcmArbiter_io_port_readDataAddr_bits), + .io_fabric_readData_valid (_itcmWrapper_io_fabric_readData_valid), + .io_fabric_readData_bits (_itcmWrapper_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid (_itcmArbiter_io_port_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits (_itcmArbiter_io_port_writeDataAddr_bits), + .io_fabric_writeDataBits (_itcmArbiter_io_port_writeDataBits), + .io_fabric_writeDataStrb (_itcmArbiter_io_port_writeDataStrb), + .io_sram_address (_itcmWrapper_io_sram_address), + .io_sram_enable (_itcmWrapper_io_sram_enable), + .io_sram_isWrite (_itcmWrapper_io_sram_isWrite), + .io_sram_readData_0 (_itcm_io_rdata_0), + .io_sram_readData_1 (_itcm_io_rdata_1), + .io_sram_readData_2 (_itcm_io_rdata_2), + .io_sram_readData_3 (_itcm_io_rdata_3), + .io_sram_readData_4 (_itcm_io_rdata_4), + .io_sram_readData_5 (_itcm_io_rdata_5), + .io_sram_readData_6 (_itcm_io_rdata_6), + .io_sram_readData_7 (_itcm_io_rdata_7), + .io_sram_readData_8 (_itcm_io_rdata_8), + .io_sram_readData_9 (_itcm_io_rdata_9), + .io_sram_readData_10 (_itcm_io_rdata_10), + .io_sram_readData_11 (_itcm_io_rdata_11), + .io_sram_readData_12 (_itcm_io_rdata_12), + .io_sram_readData_13 (_itcm_io_rdata_13), + .io_sram_readData_14 (_itcm_io_rdata_14), + .io_sram_readData_15 (_itcm_io_rdata_15), + .io_sram_writeData_0 (_itcmWrapper_io_sram_writeData_0), + .io_sram_writeData_1 (_itcmWrapper_io_sram_writeData_1), + .io_sram_writeData_2 (_itcmWrapper_io_sram_writeData_2), + .io_sram_writeData_3 (_itcmWrapper_io_sram_writeData_3), + .io_sram_writeData_4 (_itcmWrapper_io_sram_writeData_4), + .io_sram_writeData_5 (_itcmWrapper_io_sram_writeData_5), + .io_sram_writeData_6 (_itcmWrapper_io_sram_writeData_6), + .io_sram_writeData_7 (_itcmWrapper_io_sram_writeData_7), + .io_sram_writeData_8 (_itcmWrapper_io_sram_writeData_8), + .io_sram_writeData_9 (_itcmWrapper_io_sram_writeData_9), + .io_sram_writeData_10 (_itcmWrapper_io_sram_writeData_10), + .io_sram_writeData_11 (_itcmWrapper_io_sram_writeData_11), + .io_sram_writeData_12 (_itcmWrapper_io_sram_writeData_12), + .io_sram_writeData_13 (_itcmWrapper_io_sram_writeData_13), + .io_sram_writeData_14 (_itcmWrapper_io_sram_writeData_14), + .io_sram_writeData_15 (_itcmWrapper_io_sram_writeData_15), + .io_sram_mask_0 (_itcmWrapper_io_sram_mask_0), + .io_sram_mask_1 (_itcmWrapper_io_sram_mask_1), + .io_sram_mask_2 (_itcmWrapper_io_sram_mask_2), + .io_sram_mask_3 (_itcmWrapper_io_sram_mask_3), + .io_sram_mask_4 (_itcmWrapper_io_sram_mask_4), + .io_sram_mask_5 (_itcmWrapper_io_sram_mask_5), + .io_sram_mask_6 (_itcmWrapper_io_sram_mask_6), + .io_sram_mask_7 (_itcmWrapper_io_sram_mask_7), + .io_sram_mask_8 (_itcmWrapper_io_sram_mask_8), + .io_sram_mask_9 (_itcmWrapper_io_sram_mask_9), + .io_sram_mask_10 (_itcmWrapper_io_sram_mask_10), + .io_sram_mask_11 (_itcmWrapper_io_sram_mask_11), + .io_sram_mask_12 (_itcmWrapper_io_sram_mask_12), + .io_sram_mask_13 (_itcmWrapper_io_sram_mask_13), + .io_sram_mask_14 (_itcmWrapper_io_sram_mask_14), + .io_sram_mask_15 (_itcmWrapper_io_sram_mask_15) + ); + FabricArbiter itcmArbiter ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_source_0_readDataAddr_valid (_core_io_ibus_valid), + .io_source_0_readDataAddr_bits (_core_io_ibus_addr), + .io_source_0_readData_bits (_itcmArbiter_io_source_0_readData_bits), + .io_source_0_writeDataAddr_valid (1'h0), + .io_source_0_writeDataAddr_bits (32'h0), + .io_source_0_writeDataBits (128'h0), + .io_source_0_writeDataStrb (16'h0), + .io_source_1_readDataAddr_valid (_fabricMux_io_ports_0_readDataAddr_valid), + .io_source_1_readDataAddr_bits (_fabricMux_io_ports_0_readDataAddr_bits), + .io_source_1_readData_valid (_itcmArbiter_io_source_1_readData_valid), + .io_source_1_readData_bits (_itcmArbiter_io_source_1_readData_bits), + .io_source_1_writeDataAddr_valid (_fabricMux_io_ports_0_writeDataAddr_valid), + .io_source_1_writeDataAddr_bits (_fabricMux_io_ports_0_writeDataAddr_bits), + .io_source_1_writeDataBits (_fabricMux_io_ports_0_writeDataBits), + .io_source_1_writeDataStrb (_fabricMux_io_ports_0_writeDataStrb), + .io_fabricBusy (_itcmArbiter_io_fabricBusy), + .io_port_readDataAddr_valid (_itcmArbiter_io_port_readDataAddr_valid), + .io_port_readDataAddr_bits (_itcmArbiter_io_port_readDataAddr_bits), + .io_port_readData_valid (_itcmWrapper_io_fabric_readData_valid), + .io_port_readData_bits (_itcmWrapper_io_fabric_readData_bits), + .io_port_writeDataAddr_valid (_itcmArbiter_io_port_writeDataAddr_valid), + .io_port_writeDataAddr_bits (_itcmArbiter_io_port_writeDataAddr_bits), + .io_port_writeDataBits (_itcmArbiter_io_port_writeDataBits), + .io_port_writeDataStrb (_itcmArbiter_io_port_writeDataStrb) + ); + TCM128_1 dtcm ( + .clock (_rst_sync_clk_o), + .io_addr (_dtcmWrapper_io_sram_address), + .io_enable (_dtcmWrapper_io_sram_enable), + .io_write (_dtcmWrapper_io_sram_isWrite), + .io_wdata_0 (_dtcmWrapper_io_sram_writeData_0), + .io_wdata_1 (_dtcmWrapper_io_sram_writeData_1), + .io_wdata_2 (_dtcmWrapper_io_sram_writeData_2), + .io_wdata_3 (_dtcmWrapper_io_sram_writeData_3), + .io_wdata_4 (_dtcmWrapper_io_sram_writeData_4), + .io_wdata_5 (_dtcmWrapper_io_sram_writeData_5), + .io_wdata_6 (_dtcmWrapper_io_sram_writeData_6), + .io_wdata_7 (_dtcmWrapper_io_sram_writeData_7), + .io_wdata_8 (_dtcmWrapper_io_sram_writeData_8), + .io_wdata_9 (_dtcmWrapper_io_sram_writeData_9), + .io_wdata_10 (_dtcmWrapper_io_sram_writeData_10), + .io_wdata_11 (_dtcmWrapper_io_sram_writeData_11), + .io_wdata_12 (_dtcmWrapper_io_sram_writeData_12), + .io_wdata_13 (_dtcmWrapper_io_sram_writeData_13), + .io_wdata_14 (_dtcmWrapper_io_sram_writeData_14), + .io_wdata_15 (_dtcmWrapper_io_sram_writeData_15), + .io_wmask_0 (_dtcmWrapper_io_sram_mask_0), + .io_wmask_1 (_dtcmWrapper_io_sram_mask_1), + .io_wmask_2 (_dtcmWrapper_io_sram_mask_2), + .io_wmask_3 (_dtcmWrapper_io_sram_mask_3), + .io_wmask_4 (_dtcmWrapper_io_sram_mask_4), + .io_wmask_5 (_dtcmWrapper_io_sram_mask_5), + .io_wmask_6 (_dtcmWrapper_io_sram_mask_6), + .io_wmask_7 (_dtcmWrapper_io_sram_mask_7), + .io_wmask_8 (_dtcmWrapper_io_sram_mask_8), + .io_wmask_9 (_dtcmWrapper_io_sram_mask_9), + .io_wmask_10 (_dtcmWrapper_io_sram_mask_10), + .io_wmask_11 (_dtcmWrapper_io_sram_mask_11), + .io_wmask_12 (_dtcmWrapper_io_sram_mask_12), + .io_wmask_13 (_dtcmWrapper_io_sram_mask_13), + .io_wmask_14 (_dtcmWrapper_io_sram_mask_14), + .io_wmask_15 (_dtcmWrapper_io_sram_mask_15), + .io_rdata_0 (_dtcm_io_rdata_0), + .io_rdata_1 (_dtcm_io_rdata_1), + .io_rdata_2 (_dtcm_io_rdata_2), + .io_rdata_3 (_dtcm_io_rdata_3), + .io_rdata_4 (_dtcm_io_rdata_4), + .io_rdata_5 (_dtcm_io_rdata_5), + .io_rdata_6 (_dtcm_io_rdata_6), + .io_rdata_7 (_dtcm_io_rdata_7), + .io_rdata_8 (_dtcm_io_rdata_8), + .io_rdata_9 (_dtcm_io_rdata_9), + .io_rdata_10 (_dtcm_io_rdata_10), + .io_rdata_11 (_dtcm_io_rdata_11), + .io_rdata_12 (_dtcm_io_rdata_12), + .io_rdata_13 (_dtcm_io_rdata_13), + .io_rdata_14 (_dtcm_io_rdata_14), + .io_rdata_15 (_dtcm_io_rdata_15) + ); + SRAM_1 dtcmWrapper ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_fabric_readDataAddr_valid (_dtcmArbiter_io_port_readDataAddr_valid), + .io_fabric_readDataAddr_bits (_dtcmArbiter_io_port_readDataAddr_bits), + .io_fabric_readData_valid (_dtcmWrapper_io_fabric_readData_valid), + .io_fabric_readData_bits (_dtcmWrapper_io_fabric_readData_bits), + .io_fabric_writeDataAddr_valid (_dtcmArbiter_io_port_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits (_dtcmArbiter_io_port_writeDataAddr_bits), + .io_fabric_writeDataBits (_dtcmArbiter_io_port_writeDataBits), + .io_fabric_writeDataStrb (_dtcmArbiter_io_port_writeDataStrb), + .io_sram_address (_dtcmWrapper_io_sram_address), + .io_sram_enable (_dtcmWrapper_io_sram_enable), + .io_sram_isWrite (_dtcmWrapper_io_sram_isWrite), + .io_sram_readData_0 (_dtcm_io_rdata_0), + .io_sram_readData_1 (_dtcm_io_rdata_1), + .io_sram_readData_2 (_dtcm_io_rdata_2), + .io_sram_readData_3 (_dtcm_io_rdata_3), + .io_sram_readData_4 (_dtcm_io_rdata_4), + .io_sram_readData_5 (_dtcm_io_rdata_5), + .io_sram_readData_6 (_dtcm_io_rdata_6), + .io_sram_readData_7 (_dtcm_io_rdata_7), + .io_sram_readData_8 (_dtcm_io_rdata_8), + .io_sram_readData_9 (_dtcm_io_rdata_9), + .io_sram_readData_10 (_dtcm_io_rdata_10), + .io_sram_readData_11 (_dtcm_io_rdata_11), + .io_sram_readData_12 (_dtcm_io_rdata_12), + .io_sram_readData_13 (_dtcm_io_rdata_13), + .io_sram_readData_14 (_dtcm_io_rdata_14), + .io_sram_readData_15 (_dtcm_io_rdata_15), + .io_sram_writeData_0 (_dtcmWrapper_io_sram_writeData_0), + .io_sram_writeData_1 (_dtcmWrapper_io_sram_writeData_1), + .io_sram_writeData_2 (_dtcmWrapper_io_sram_writeData_2), + .io_sram_writeData_3 (_dtcmWrapper_io_sram_writeData_3), + .io_sram_writeData_4 (_dtcmWrapper_io_sram_writeData_4), + .io_sram_writeData_5 (_dtcmWrapper_io_sram_writeData_5), + .io_sram_writeData_6 (_dtcmWrapper_io_sram_writeData_6), + .io_sram_writeData_7 (_dtcmWrapper_io_sram_writeData_7), + .io_sram_writeData_8 (_dtcmWrapper_io_sram_writeData_8), + .io_sram_writeData_9 (_dtcmWrapper_io_sram_writeData_9), + .io_sram_writeData_10 (_dtcmWrapper_io_sram_writeData_10), + .io_sram_writeData_11 (_dtcmWrapper_io_sram_writeData_11), + .io_sram_writeData_12 (_dtcmWrapper_io_sram_writeData_12), + .io_sram_writeData_13 (_dtcmWrapper_io_sram_writeData_13), + .io_sram_writeData_14 (_dtcmWrapper_io_sram_writeData_14), + .io_sram_writeData_15 (_dtcmWrapper_io_sram_writeData_15), + .io_sram_mask_0 (_dtcmWrapper_io_sram_mask_0), + .io_sram_mask_1 (_dtcmWrapper_io_sram_mask_1), + .io_sram_mask_2 (_dtcmWrapper_io_sram_mask_2), + .io_sram_mask_3 (_dtcmWrapper_io_sram_mask_3), + .io_sram_mask_4 (_dtcmWrapper_io_sram_mask_4), + .io_sram_mask_5 (_dtcmWrapper_io_sram_mask_5), + .io_sram_mask_6 (_dtcmWrapper_io_sram_mask_6), + .io_sram_mask_7 (_dtcmWrapper_io_sram_mask_7), + .io_sram_mask_8 (_dtcmWrapper_io_sram_mask_8), + .io_sram_mask_9 (_dtcmWrapper_io_sram_mask_9), + .io_sram_mask_10 (_dtcmWrapper_io_sram_mask_10), + .io_sram_mask_11 (_dtcmWrapper_io_sram_mask_11), + .io_sram_mask_12 (_dtcmWrapper_io_sram_mask_12), + .io_sram_mask_13 (_dtcmWrapper_io_sram_mask_13), + .io_sram_mask_14 (_dtcmWrapper_io_sram_mask_14), + .io_sram_mask_15 (_dtcmWrapper_io_sram_mask_15) + ); + FabricArbiter dtcmArbiter ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_source_0_readDataAddr_valid (_core_io_dbus_valid & ~_core_io_dbus_write), + .io_source_0_readDataAddr_bits (_core_io_dbus_addr), + .io_source_0_readData_bits (_dtcmArbiter_io_source_0_readData_bits), + .io_source_0_writeDataAddr_valid (_core_io_dbus_valid & _core_io_dbus_write), + .io_source_0_writeDataAddr_bits (_core_io_dbus_addr), + .io_source_0_writeDataBits (_core_io_dbus_wdata), + .io_source_0_writeDataStrb (_core_io_dbus_wmask), + .io_source_1_readDataAddr_valid (_fabricMux_io_ports_1_readDataAddr_valid), + .io_source_1_readDataAddr_bits (_fabricMux_io_ports_1_readDataAddr_bits), + .io_source_1_readData_valid (_dtcmArbiter_io_source_1_readData_valid), + .io_source_1_readData_bits (_dtcmArbiter_io_source_1_readData_bits), + .io_source_1_writeDataAddr_valid (_fabricMux_io_ports_1_writeDataAddr_valid), + .io_source_1_writeDataAddr_bits (_fabricMux_io_ports_1_writeDataAddr_bits), + .io_source_1_writeDataBits (_fabricMux_io_ports_1_writeDataBits), + .io_source_1_writeDataStrb (_fabricMux_io_ports_1_writeDataStrb), + .io_fabricBusy (_dtcmArbiter_io_fabricBusy), + .io_port_readDataAddr_valid (_dtcmArbiter_io_port_readDataAddr_valid), + .io_port_readDataAddr_bits (_dtcmArbiter_io_port_readDataAddr_bits), + .io_port_readData_valid (_dtcmWrapper_io_fabric_readData_valid), + .io_port_readData_bits (_dtcmWrapper_io_fabric_readData_bits), + .io_port_writeDataAddr_valid (_dtcmArbiter_io_port_writeDataAddr_valid), + .io_port_writeDataAddr_bits (_dtcmArbiter_io_port_writeDataAddr_bits), + .io_port_writeDataBits (_dtcmArbiter_io_port_writeDataBits), + .io_port_writeDataStrb (_dtcmArbiter_io_port_writeDataStrb) + ); + FabricMux fabricMux ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_source_readDataAddr_valid (_axiSlave_io_fabric_readDataAddr_valid), + .io_source_readDataAddr_bits (_axiSlave_io_fabric_readDataAddr_bits), + .io_source_readData_valid (_fabricMux_io_source_readData_valid), + .io_source_readData_bits (_fabricMux_io_source_readData_bits), + .io_source_writeDataAddr_valid (_axiSlave_io_fabric_writeDataAddr_valid), + .io_source_writeDataAddr_bits (_axiSlave_io_fabric_writeDataAddr_bits), + .io_source_writeDataBits (_axiSlave_io_fabric_writeDataBits), + .io_source_writeDataStrb (_axiSlave_io_fabric_writeDataStrb), + .io_source_writeResp (_fabricMux_io_source_writeResp), + .io_fabricBusy (_fabricMux_io_fabricBusy), + .io_ports_0_readDataAddr_valid (_fabricMux_io_ports_0_readDataAddr_valid), + .io_ports_0_readDataAddr_bits (_fabricMux_io_ports_0_readDataAddr_bits), + .io_ports_0_readData_valid (_itcmArbiter_io_source_1_readData_valid), + .io_ports_0_readData_bits (_itcmArbiter_io_source_1_readData_bits), + .io_ports_0_writeDataAddr_valid (_fabricMux_io_ports_0_writeDataAddr_valid), + .io_ports_0_writeDataAddr_bits (_fabricMux_io_ports_0_writeDataAddr_bits), + .io_ports_0_writeDataBits (_fabricMux_io_ports_0_writeDataBits), + .io_ports_0_writeDataStrb (_fabricMux_io_ports_0_writeDataStrb), + .io_ports_1_readDataAddr_valid (_fabricMux_io_ports_1_readDataAddr_valid), + .io_ports_1_readDataAddr_bits (_fabricMux_io_ports_1_readDataAddr_bits), + .io_ports_1_readData_valid (_dtcmArbiter_io_source_1_readData_valid), + .io_ports_1_readData_bits (_dtcmArbiter_io_source_1_readData_bits), + .io_ports_1_writeDataAddr_valid (_fabricMux_io_ports_1_writeDataAddr_valid), + .io_ports_1_writeDataAddr_bits (_fabricMux_io_ports_1_writeDataAddr_bits), + .io_ports_1_writeDataBits (_fabricMux_io_ports_1_writeDataBits), + .io_ports_1_writeDataStrb (_fabricMux_io_ports_1_writeDataStrb), + .io_ports_2_readDataAddr_bits (_fabricMux_io_ports_2_readDataAddr_bits), + .io_ports_2_readData_valid (_csr_io_fabric_readData_valid), + .io_ports_2_readData_bits (_csr_io_fabric_readData_bits), + .io_ports_2_writeDataAddr_valid (_fabricMux_io_ports_2_writeDataAddr_valid), + .io_ports_2_writeDataAddr_bits (_fabricMux_io_ports_2_writeDataAddr_bits), + .io_ports_2_writeDataBits (_fabricMux_io_ports_2_writeDataBits), + .io_ports_2_writeResp (_csr_io_fabric_writeResp), + .io_periBusy_0 (_itcmArbiter_io_fabricBusy), + .io_periBusy_1 (_dtcmArbiter_io_fabricBusy) + ); + AxiSlave axiSlave ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_axi_write_addr_ready (_axiSlave_io_axi_write_addr_ready), + .io_axi_write_addr_valid (io_axi_slave_write_addr_valid & axiSlaveEnable), + .io_axi_write_addr_bits_addr (io_axi_slave_write_addr_bits_addr), + .io_axi_write_addr_bits_prot (io_axi_slave_write_addr_bits_prot), + .io_axi_write_addr_bits_id (io_axi_slave_write_addr_bits_id), + .io_axi_write_addr_bits_len (io_axi_slave_write_addr_bits_len), + .io_axi_write_addr_bits_size (io_axi_slave_write_addr_bits_size), + .io_axi_write_addr_bits_burst (io_axi_slave_write_addr_bits_burst), + .io_axi_write_addr_bits_lock (io_axi_slave_write_addr_bits_lock), + .io_axi_write_addr_bits_cache (io_axi_slave_write_addr_bits_cache), + .io_axi_write_addr_bits_qos (io_axi_slave_write_addr_bits_qos), + .io_axi_write_addr_bits_region (io_axi_slave_write_addr_bits_region), + .io_axi_write_data_ready (_axiSlave_io_axi_write_data_ready), + .io_axi_write_data_valid (io_axi_slave_write_data_valid & axiSlaveEnable), + .io_axi_write_data_bits_data (io_axi_slave_write_data_bits_data), + .io_axi_write_data_bits_last (io_axi_slave_write_data_bits_last), + .io_axi_write_data_bits_strb (io_axi_slave_write_data_bits_strb), + .io_axi_write_resp_ready (io_axi_slave_write_resp_ready & axiSlaveEnable), + .io_axi_write_resp_valid (_axiSlave_io_axi_write_resp_valid), + .io_axi_write_resp_bits_id (io_axi_slave_write_resp_bits_id), + .io_axi_write_resp_bits_resp (io_axi_slave_write_resp_bits_resp), + .io_axi_read_addr_ready (_axiSlave_io_axi_read_addr_ready), + .io_axi_read_addr_valid (io_axi_slave_read_addr_valid & axiSlaveEnable), + .io_axi_read_addr_bits_addr (io_axi_slave_read_addr_bits_addr), + .io_axi_read_addr_bits_prot (io_axi_slave_read_addr_bits_prot), + .io_axi_read_addr_bits_id (io_axi_slave_read_addr_bits_id), + .io_axi_read_addr_bits_len (io_axi_slave_read_addr_bits_len), + .io_axi_read_addr_bits_size (io_axi_slave_read_addr_bits_size), + .io_axi_read_addr_bits_burst (io_axi_slave_read_addr_bits_burst), + .io_axi_read_addr_bits_lock (io_axi_slave_read_addr_bits_lock), + .io_axi_read_addr_bits_cache (io_axi_slave_read_addr_bits_cache), + .io_axi_read_addr_bits_qos (io_axi_slave_read_addr_bits_qos), + .io_axi_read_addr_bits_region (io_axi_slave_read_addr_bits_region), + .io_axi_read_data_ready (io_axi_slave_read_data_ready & axiSlaveEnable), + .io_axi_read_data_valid (_axiSlave_io_axi_read_data_valid), + .io_axi_read_data_bits_data (io_axi_slave_read_data_bits_data), + .io_axi_read_data_bits_id (io_axi_slave_read_data_bits_id), + .io_axi_read_data_bits_resp (io_axi_slave_read_data_bits_resp), + .io_axi_read_data_bits_last (io_axi_slave_read_data_bits_last), + .io_fabric_readDataAddr_valid (_axiSlave_io_fabric_readDataAddr_valid), + .io_fabric_readDataAddr_bits (_axiSlave_io_fabric_readDataAddr_bits), + .io_fabric_readData_valid (_fabricMux_io_source_readData_valid), + .io_fabric_readData_bits (_fabricMux_io_source_readData_bits), + .io_fabric_writeDataAddr_valid (_axiSlave_io_fabric_writeDataAddr_valid), + .io_fabric_writeDataAddr_bits (_axiSlave_io_fabric_writeDataAddr_bits), + .io_fabric_writeDataBits (_axiSlave_io_fabric_writeDataBits), + .io_fabric_writeDataStrb (_axiSlave_io_fabric_writeDataStrb), + .io_fabric_writeResp (_fabricMux_io_source_writeResp), + .io_periBusy (_fabricMux_io_fabricBusy) + ); + DBus2AxiV1 ebus2axi ( + .clock (_rst_sync_clk_o), + .reset (_global_reset_T_2), + .io_dbus_valid (_core_io_ebus_dbus_valid), + .io_dbus_ready (_ebus2axi_io_dbus_ready), + .io_dbus_write (_core_io_ebus_dbus_write), + .io_dbus_pc (_core_io_ebus_dbus_pc), + .io_dbus_addr (_core_io_ebus_dbus_addr), + .io_dbus_size (_core_io_ebus_dbus_size), + .io_dbus_wdata (_core_io_ebus_dbus_wdata), + .io_dbus_rdata (_ebus2axi_io_dbus_rdata), + .io_axi_write_addr_ready (io_axi_master_write_addr_ready), + .io_axi_write_addr_valid (io_axi_master_write_addr_valid), + .io_axi_write_addr_bits_addr (io_axi_master_write_addr_bits_addr), + .io_axi_write_addr_bits_prot (io_axi_master_write_addr_bits_prot), + .io_axi_write_addr_bits_id (io_axi_master_write_addr_bits_id), + .io_axi_write_addr_bits_len (io_axi_master_write_addr_bits_len), + .io_axi_write_addr_bits_size (io_axi_master_write_addr_bits_size), + .io_axi_write_addr_bits_burst (io_axi_master_write_addr_bits_burst), + .io_axi_write_addr_bits_lock (io_axi_master_write_addr_bits_lock), + .io_axi_write_addr_bits_cache (io_axi_master_write_addr_bits_cache), + .io_axi_write_addr_bits_qos (io_axi_master_write_addr_bits_qos), + .io_axi_write_addr_bits_region (io_axi_master_write_addr_bits_region), + .io_axi_write_data_ready (io_axi_master_write_data_ready), + .io_axi_write_data_valid (io_axi_master_write_data_valid), + .io_axi_write_data_bits_data (io_axi_master_write_data_bits_data), + .io_axi_write_data_bits_last (io_axi_master_write_data_bits_last), + .io_axi_write_data_bits_strb (io_axi_master_write_data_bits_strb), + .io_axi_write_resp_ready (io_axi_master_write_resp_ready), + .io_axi_write_resp_valid (io_axi_master_write_resp_valid), + .io_axi_write_resp_bits_id (io_axi_master_write_resp_bits_id), + .io_axi_write_resp_bits_resp (io_axi_master_write_resp_bits_resp), + .io_axi_read_addr_ready (io_axi_master_read_addr_ready), + .io_axi_read_addr_valid (io_axi_master_read_addr_valid), + .io_axi_read_addr_bits_addr (io_axi_master_read_addr_bits_addr), + .io_axi_read_addr_bits_prot (io_axi_master_read_addr_bits_prot), + .io_axi_read_addr_bits_id (io_axi_master_read_addr_bits_id), + .io_axi_read_addr_bits_len (io_axi_master_read_addr_bits_len), + .io_axi_read_addr_bits_size (io_axi_master_read_addr_bits_size), + .io_axi_read_addr_bits_burst (io_axi_master_read_addr_bits_burst), + .io_axi_read_addr_bits_lock (io_axi_master_read_addr_bits_lock), + .io_axi_read_addr_bits_cache (io_axi_master_read_addr_bits_cache), + .io_axi_read_addr_bits_qos (io_axi_master_read_addr_bits_qos), + .io_axi_read_addr_bits_region (io_axi_master_read_addr_bits_region), + .io_axi_read_data_ready (io_axi_master_read_data_ready), + .io_axi_read_data_valid (io_axi_master_read_data_valid), + .io_axi_read_data_bits_data (io_axi_master_read_data_bits_data), + .io_axi_read_data_bits_id (io_axi_master_read_data_bits_id), + .io_axi_read_data_bits_resp (io_axi_master_read_data_bits_resp), + .io_axi_read_data_bits_last (io_axi_master_read_data_bits_last), + .io_fault_valid (_ebus2axi_io_fault_valid), + .io_fault_bits_write (_ebus2axi_io_fault_bits_write), + .io_fault_bits_addr (_ebus2axi_io_fault_bits_addr), + .io_fault_bits_epc (_ebus2axi_io_fault_bits_epc) + ); + assign io_axi_slave_write_addr_ready = + _axiSlave_io_axi_write_addr_ready & axiSlaveEnable; + assign io_axi_slave_write_data_ready = + _axiSlave_io_axi_write_data_ready & axiSlaveEnable; + assign io_axi_slave_write_resp_valid = + _axiSlave_io_axi_write_resp_valid & axiSlaveEnable; + assign io_axi_slave_read_addr_ready = _axiSlave_io_axi_read_addr_ready & axiSlaveEnable; + assign io_axi_slave_read_data_valid = _axiSlave_io_axi_read_data_valid & axiSlaveEnable; + assign io_halted = _core_io_halted; + assign io_fault = _core_io_fault; + assign io_wfi = _core_io_wfi; +endmodule + + +// ----- 8< ----- FILE "verification/cover/layers-CoreMiniAxi-Verification_Cover.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +`ifndef layers_CoreMiniAxi_Verification_Cover +`define layers_CoreMiniAxi_Verification_Cover +`endif // layers_CoreMiniAxi_Verification_Cover + +// ----- 8< ----- FILE "verification/assume/layers-CoreMiniAxi-Verification_Assume.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +`ifndef layers_CoreMiniAxi_Verification_Assume +`define layers_CoreMiniAxi_Verification_Assume +`endif // layers_CoreMiniAxi_Verification_Assume + +// ----- 8< ----- FILE "verification/assert/layers-CoreMiniAxi-Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +`ifndef layers_CoreMiniAxi_Verification_Assert +`define layers_CoreMiniAxi_Verification_Assert +bind Regfile Regfile_Verification_Assert verification_Assert ( + ._GEN (valid_1), + ._GEN_0 (valid_2), + ._GEN_1 (_valid_T), + ._GEN_2 (_valid_T_8), + ._GEN_3 (_valid_T_10), + ._GEN_4 (valid_3), + .reset (reset), + ._GEN_5 (1'h1), + ._GEN_6 (valid_1_1), + ._GEN_7 (valid_2_1), + ._GEN_8 (_valid_T_12), + ._GEN_9 (_valid_T_20), + ._GEN_10 (_valid_T_22), + ._GEN_11 (valid_3_1), + ._GEN_12 (valid_1_2), + ._GEN_13 (valid_2_2), + ._GEN_14 (_valid_T_24), + ._GEN_15 (_valid_T_32), + ._GEN_16 (_valid_T_34), + ._GEN_17 (valid_3_2), + ._GEN_18 (valid_1_3), + ._GEN_19 (valid_2_3), + ._GEN_20 (_valid_T_36), + ._GEN_21 (_valid_T_44), + ._GEN_22 (_valid_T_46), + ._GEN_23 (valid_3_3), + ._GEN_24 (valid_1_4), + ._GEN_25 (valid_2_4), + ._GEN_26 (_valid_T_48), + ._GEN_27 (_valid_T_56), + ._GEN_28 (_valid_T_58), + ._GEN_29 (valid_3_4), + ._GEN_30 (valid_1_5), + ._GEN_31 (valid_2_5), + ._GEN_32 (_valid_T_60), + ._GEN_33 (_valid_T_68), + ._GEN_34 (_valid_T_70), + ._GEN_35 (valid_3_5), + ._GEN_36 (valid_1_6), + ._GEN_37 (valid_2_6), + ._GEN_38 (_valid_T_72), + ._GEN_39 (_valid_T_80), + ._GEN_40 (_valid_T_82), + ._GEN_41 (valid_3_6), + ._GEN_42 (valid_1_7), + ._GEN_43 (valid_2_7), + ._GEN_44 (_valid_T_84), + ._GEN_45 (_valid_T_92), + ._GEN_46 (_valid_T_94), + ._GEN_47 (valid_3_7), + ._GEN_48 (valid_1_8), + ._GEN_49 (valid_2_8), + ._GEN_50 (_valid_T_96), + ._GEN_51 (_valid_T_104), + ._GEN_52 (_valid_T_106), + ._GEN_53 (valid_3_8), + ._GEN_54 (valid_1_9), + ._GEN_55 (valid_2_9), + ._GEN_56 (_valid_T_108), + ._GEN_57 (_valid_T_116), + ._GEN_58 (_valid_T_118), + ._GEN_59 (valid_3_9), + ._GEN_60 (valid_1_10), + ._GEN_61 (valid_2_10), + ._GEN_62 (_valid_T_120), + ._GEN_63 (_valid_T_128), + ._GEN_64 (_valid_T_130), + ._GEN_65 (valid_3_10), + ._GEN_66 (valid_1_11), + ._GEN_67 (valid_2_11), + ._GEN_68 (_valid_T_132), + ._GEN_69 (_valid_T_140), + ._GEN_70 (_valid_T_142), + ._GEN_71 (valid_3_11), + ._GEN_72 (valid_1_12), + ._GEN_73 (valid_2_12), + ._GEN_74 (_valid_T_144), + ._GEN_75 (_valid_T_152), + ._GEN_76 (_valid_T_154), + ._GEN_77 (valid_3_12), + ._GEN_78 (valid_1_13), + ._GEN_79 (valid_2_13), + ._GEN_80 (_valid_T_156), + ._GEN_81 (_valid_T_164), + ._GEN_82 (_valid_T_166), + ._GEN_83 (valid_3_13), + ._GEN_84 (valid_1_14), + ._GEN_85 (valid_2_14), + ._GEN_86 (_valid_T_168), + ._GEN_87 (_valid_T_176), + ._GEN_88 (_valid_T_178), + ._GEN_89 (valid_3_14), + ._GEN_90 (valid_1_15), + ._GEN_91 (valid_2_15), + ._GEN_92 (_valid_T_180), + ._GEN_93 (_valid_T_188), + ._GEN_94 (_valid_T_190), + ._GEN_95 (valid_3_15), + ._GEN_96 (valid_1_16), + ._GEN_97 (valid_2_16), + ._GEN_98 (_valid_T_192), + ._GEN_99 (_valid_T_200), + ._GEN_100 (_valid_T_202), + ._GEN_101 (valid_3_16), + ._GEN_102 (valid_1_17), + ._GEN_103 (valid_2_17), + ._GEN_104 (_valid_T_204), + ._GEN_105 (_valid_T_212), + ._GEN_106 (_valid_T_214), + ._GEN_107 (valid_3_17), + ._GEN_108 (valid_1_18), + ._GEN_109 (valid_2_18), + ._GEN_110 (_valid_T_216), + ._GEN_111 (_valid_T_224), + ._GEN_112 (_valid_T_226), + ._GEN_113 (valid_3_18), + ._GEN_114 (valid_1_19), + ._GEN_115 (valid_2_19), + ._GEN_116 (_valid_T_228), + ._GEN_117 (_valid_T_236), + ._GEN_118 (_valid_T_238), + ._GEN_119 (valid_3_19), + ._GEN_120 (valid_1_20), + ._GEN_121 (valid_2_20), + ._GEN_122 (_valid_T_240), + ._GEN_123 (_valid_T_248), + ._GEN_124 (_valid_T_250), + ._GEN_125 (valid_3_20), + ._GEN_126 (valid_1_21), + ._GEN_127 (valid_2_21), + ._GEN_128 (_valid_T_252), + ._GEN_129 (_valid_T_260), + ._GEN_130 (_valid_T_262), + ._GEN_131 (valid_3_21), + ._GEN_132 (valid_1_22), + ._GEN_133 (valid_2_22), + ._GEN_134 (_valid_T_264), + ._GEN_135 (_valid_T_272), + ._GEN_136 (_valid_T_274), + ._GEN_137 (valid_3_22), + ._GEN_138 (valid_1_23), + ._GEN_139 (valid_2_23), + ._GEN_140 (_valid_T_276), + ._GEN_141 (_valid_T_284), + ._GEN_142 (_valid_T_286), + ._GEN_143 (valid_3_23), + ._GEN_144 (valid_1_24), + ._GEN_145 (valid_2_24), + ._GEN_146 (_valid_T_288), + ._GEN_147 (_valid_T_296), + ._GEN_148 (_valid_T_298), + ._GEN_149 (valid_3_24), + ._GEN_150 (valid_1_25), + ._GEN_151 (valid_2_25), + ._GEN_152 (_valid_T_300), + ._GEN_153 (_valid_T_308), + ._GEN_154 (_valid_T_310), + ._GEN_155 (valid_3_25), + ._GEN_156 (valid_1_26), + ._GEN_157 (valid_2_26), + ._GEN_158 (_valid_T_312), + ._GEN_159 (_valid_T_320), + ._GEN_160 (_valid_T_322), + ._GEN_161 (valid_3_26), + ._GEN_162 (valid_1_27), + ._GEN_163 (valid_2_27), + ._GEN_164 (_valid_T_324), + ._GEN_165 (_valid_T_332), + ._GEN_166 (_valid_T_334), + ._GEN_167 (valid_3_27), + ._GEN_168 (valid_1_28), + ._GEN_169 (valid_2_28), + ._GEN_170 (_valid_T_336), + ._GEN_171 (_valid_T_344), + ._GEN_172 (_valid_T_346), + ._GEN_173 (valid_3_28), + ._GEN_174 (valid_1_29), + ._GEN_175 (valid_2_29), + ._GEN_176 (_valid_T_348), + ._GEN_177 (_valid_T_356), + ._GEN_178 (_valid_T_358), + ._GEN_179 (valid_3_29), + ._GEN_180 (valid_1_30), + ._GEN_181 (valid_2_30), + ._GEN_182 (_valid_T_360), + ._GEN_183 (_valid_T_368), + ._GEN_184 (_valid_T_370), + ._GEN_185 (valid_3_30), + .write_fail (write_fail), + .write_fail_1 (write_fail_1), + .write_fail_2 (write_fail_2), + .write_fail_3 (write_fail_3), + .write_fail_4 (write_fail_4), + .write_fail_5 (write_fail_5), + .write_fail_6 (write_fail_6), + .write_fail_7 (write_fail_7), + .write_fail_8 (write_fail_8), + .write_fail_9 (write_fail_9), + .write_fail_10 (write_fail_10), + .write_fail_11 (write_fail_11), + .write_fail_12 (write_fail_12), + .write_fail_13 (write_fail_13), + .write_fail_14 (write_fail_14), + .scoreboard_error (scoreboard_error), + .clock (clock) +); +bind CircularBufferMulti CircularBufferMulti_Verification_Assert verification_Assert ( + .io_nEnqueued (nEnqueued), + .io_enqValid (io_enqValid), + .io_deqReady (io_deqReady), + .reset (reset), + ._GEN (4'h8), + .clock (clock) +); +bind InstructionBuffer InstructionBuffer_Verification_Assert verification_Assert ( + ._GEN (_nReady_T), + ._GEN_0 (_nReady_T_1), + ._GEN_1 (_nReady_T_2), + ._GEN_2 (_nReady_T_3), + .reset (reset), + .clock (clock) +); +bind Csr Csr_Verification_Assert verification_Assert ( + ._GEN (fflagsEn), + ._GEN_0 (frmEn), + .csr_address (req_pipe_b_index), + ._GEN_1 (fcsrEn), + ._GEN_2 (mstatusEn), + ._GEN_3 (misaEn), + ._GEN_4 (mieEn), + ._GEN_5 (mtvecEn), + ._GEN_6 (mscratchEn), + ._GEN_7 (mepcEn), + ._GEN_8 (mcauseEn), + ._GEN_9 (mtvalEn), + ._GEN_10 (mcontext0En), + ._GEN_11 (mcontext1En), + ._GEN_12 (mcontext2En), + ._GEN_13 (mcontext3En), + ._GEN_14 (mcontext4En), + ._GEN_15 (mcontext5En), + ._GEN_16 (mcontext6En), + ._GEN_17 (mcontext7En), + ._GEN_18 (mpcEn), + ._GEN_19 (mspEn), + ._GEN_20 (mcycleEn), + ._GEN_21 (minstretEn), + ._GEN_22 (mcyclehEn), + ._GEN_23 (minstrethEn), + ._GEN_24 (mvendoridEn), + ._GEN_25 (marchidEn), + ._GEN_26 (mimpidEn), + ._GEN_27 (mhartidEn), + ._GEN_28 (kisaEn), + ._GEN_29 (kscm0En), + ._GEN_30 (kscm1En), + ._GEN_31 (kscm2En), + ._GEN_32 (kscm3En), + ._GEN_33 (kscm4En), + .req_valid (req_pipe_v), + .reset (reset), + .io_halted (halted), + .io_wfi (wfi), + .io_fault (fault), + .io_rs1_valid (io_rs1_valid), + .clock (clock) +); +bind Alu Alu_Verification_Assert verification_Assert ( + .io_rs1_valid (io_rs1_valid), + ._GEN (op == 5'hA), + .valid (valid), + .reset (reset), + .io_rs2_valid (io_rs2_valid), + ._rs1Only_WIRE_5 (op == 5'h15), + ._rs1Only_WIRE_4 (op == 5'h16), + ._rs1Only_WIRE_7 (op == 5'h1A), + ._rs1Only_WIRE_6 (op == 5'h19), + ._rs1Only_WIRE_1 (op == 5'hF), + ._rs1Only_WIRE_0 (op == 5'hE), + ._rs1Only_WIRE_3 (op == 5'h1B), + ._rs1Only_WIRE_2 (op == 5'h10), + .clock (clock) +); +bind Bru Bru_Verification_Assert verification_Assert ( + .io_rs1_valid (io_rs1_valid), + .stateReg_valid (stateReg_valid), + ._ignore_WIRE_5 (_ignore_T_5), + ._ignore_WIRE_4 (_ignore_T_4), + ._ignore_WIRE_7 (_ignore_T_7), + ._ignore_WIRE_6 (_ignore_T_6), + ._ignore_WIRE_1 (stateReg_bits_op == 4'h1), + ._ignore_WIRE_0 (~(|stateReg_bits_op)), + ._ignore_WIRE_3 (_ignore_T_3), + ._ignore_WIRE_2 (_ignore_T_2), + .reset (reset), + .io_rs2_valid (io_rs2_valid), + .clock (clock) +); +bind Bru_1 Bru_1_Verification_Assert verification_Assert ( + ._GEN (_ignore_T_6), + ._GEN_0 (_ignore_T_5), + ._GEN_1 (_ignore_T_3), + ._GEN_2 (_ignore_T_2), + ._GEN_3 (_ignore_T_4), + .reset (reset), + .io_rs1_valid (io_rs1_valid), + .stateReg_valid (stateReg_valid), + ._ignore_WIRE_5 (_ignore_T_5), + ._ignore_WIRE_4 (_ignore_T_4), + ._ignore_WIRE_7 (stateReg_bits_op == 4'hD), + ._ignore_WIRE_6 (_ignore_T_6), + ._ignore_WIRE_1 (stateReg_bits_op == 4'h1), + ._ignore_WIRE_0 (~(|stateReg_bits_op)), + ._ignore_WIRE_3 (_ignore_T_3), + ._ignore_WIRE_2 (_ignore_T_2), + .io_rs2_valid (io_rs2_valid), + .clock (clock) +); +bind FifoX FifoX_Verification_Assert verification_Assert ( + .reset (reset), + .mcount (mcount), + ._GEN (4'h8), + .clock (clock) +); +bind LsuV1 LsuV1_Verification_Assert verification_Assert ( + .ctrl_io_out_bits_addr (_ctrl_io_out_bits_addr), + .io_dbus_valid (io_dbus_valid_0), + .reset (reset), + .io_dbus_addr (io_dbus_addr_0), + .io_dbus_adrx ({1'h0, _ctrl_io_out_bits_adrx[30:0]}), + .ctrl_io_out_bits_fldst (_ctrl_io_out_bits_fldst), + .ctrl_io_out_bits_sldst (_ctrl_io_out_bits_sldst), + .ctrl_io_out_bits_vldst (_ctrl_io_out_bits_vldst), + ._GEN (1'h1), + .ctrl_io_out_valid (_ctrl_io_out_valid), + .data_io_out_bits_fldst (_data_io_out_bits_fldst), + .data_io_out_bits_sldst (_data_io_out_bits_sldst), + .data_io_out_valid (_data_io_out_valid), + .clock (clock) +); +bind Mlu Mlu_Verification_Assert verification_Assert ( + .io_rs1_0_valid (io_rs1_0_valid), + .stage2Input_q_io_deq_valid (_stage2Input_q_io_deq_valid), + ._GEN (_stage2Input_q_io_deq_bits_sel[0]), + .reset (reset), + .io_rs2_0_valid (io_rs2_0_valid), + .io_rs1_1_valid (io_rs1_1_valid), + ._GEN_0 (_stage2Input_q_io_deq_bits_sel[1]), + .io_rs2_1_valid (io_rs2_1_valid), + .io_rs1_2_valid (io_rs1_2_valid), + ._GEN_1 (_stage2Input_q_io_deq_bits_sel[2]), + .io_rs2_2_valid (io_rs2_2_valid), + .io_rs1_3_valid (io_rs1_3_valid), + ._GEN_2 (_stage2Input_q_io_deq_bits_sel[3]), + .io_rs2_3_valid (io_rs2_3_valid), + .clock (clock) +); +bind FloatCore FloatCore_Verification_Assert verification_Assert ( + .io_csr_out_frm (io_csr_out_frm), + ._GEN (1'h1), + ._GEN_0 (2'h2), + ._GEN_1 (2'h3), + ._GEN_2 (3'h4), + ._GEN_3 (3'h5), + ._GEN_4 (reset), + .clock (clock) +); +bind FRegfile FRegfile_Verification_Assert verification_Assert ( + .reset (reset), + .scoreboard_error (scoreboard_error), + .clock (clock) +); +bind SCore SCore_Verification_Assert verification_Assert ( + .csr_io_rd_valid (_csr_io_rd_valid), + .alu_0_io_rd_valid (_alu_0_io_rd_valid), + .bru_0_io_rd_valid (_bru_0_io_rd_valid), + .reset (reset), + ._GEN (1'h1), + .alu_1_io_rd_valid (_alu_1_io_rd_valid), + .bru_1_io_rd_valid (_bru_1_io_rd_valid), + .alu_2_io_rd_valid (_alu_2_io_rd_valid), + .bru_2_io_rd_valid (_bru_2_io_rd_valid), + .alu_3_io_rd_valid (_alu_3_io_rd_valid), + .bru_3_io_rd_valid (_bru_3_io_rd_valid), + .clock (clock) +); +bind FabricArbiter FabricArbiter_Verification_Assert verification_Assert ( + .io_source_0_readDataAddr_valid (io_source_0_readDataAddr_valid), + .io_source_0_writeDataAddr_valid (io_source_0_writeDataAddr_valid), + .reset (reset), + .io_source_1_readDataAddr_valid (io_source_1_readDataAddr_valid), + .io_source_1_writeDataAddr_valid (io_source_1_writeDataAddr_valid), + .clock (clock) +); +bind FabricMux FabricMux_Verification_Assert verification_Assert ( + .io_source_readDataAddr_valid (io_source_readDataAddr_valid), + .io_source_writeDataAddr_valid (io_source_writeDataAddr_valid), + .reset (reset), + ._GEN (portSelected_1), + ._GEN_0 (_portSelected_T_7), + ._GEN_1 (portSelected_0), + ._GEN_2 (1'h1), + .clock (clock) +); +bind AxiSlave AxiSlave_Verification_Assert verification_Assert ( + .readIssued (readIssued), + .reset (reset), + .readDataQueue_io_enq_ready (_readDataQueue_io_enq_ready), + .clock (clock) +); +bind FifoX_1 FifoX_1_Verification_Assert verification_Assert ( + .reset (reset), + .mcount (mcount), + ._GEN (2'h2), + .clock (clock) +); +bind FifoX_3 FifoX_3_Verification_Assert verification_Assert ( + .reset (reset), + .mcount (mcount), + ._GEN (2'h2), + .clock (clock) +); +bind DBus2AxiV1 DBus2AxiV1_Verification_Assert verification_Assert ( + .io_dbus_size (io_dbus_size), + ._GEN (1'h1), + .io_dbus_valid (io_dbus_valid), + .reset (reset), + .txnActive (txnActive), + ._GEN_0 (txnCount), + .readAddrQ_io_count (_readAddrQ_io_count), + ._GEN_1 (newTxn), + .io_axi_read_data_bits_id (io_axi_read_data_bits_id), + .io_axi_read_data_valid (io_axi_read_data_valid), + .writeAddrQ_io_count (_writeAddrQ_io_count), + .writeDataQ_io_count (_writeDataQ_io_count), + .io_axi_write_resp_bits_id (io_axi_write_resp_bits_id), + .io_axi_write_resp_valid (io_axi_write_resp_valid), + .clock (clock) +); +`endif // layers_CoreMiniAxi_Verification_Assert + +// ----- 8< ----- FILE "verification/assert/Regfile_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Regfile_Verification_Assert( + input _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + reset, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + _GEN_16, + _GEN_17, + _GEN_18, + _GEN_19, + _GEN_20, + _GEN_21, + _GEN_22, + _GEN_23, + _GEN_24, + _GEN_25, + _GEN_26, + _GEN_27, + _GEN_28, + _GEN_29, + _GEN_30, + _GEN_31, + _GEN_32, + _GEN_33, + _GEN_34, + _GEN_35, + _GEN_36, + _GEN_37, + _GEN_38, + _GEN_39, + _GEN_40, + _GEN_41, + _GEN_42, + _GEN_43, + _GEN_44, + _GEN_45, + _GEN_46, + _GEN_47, + _GEN_48, + _GEN_49, + _GEN_50, + _GEN_51, + _GEN_52, + _GEN_53, + _GEN_54, + _GEN_55, + _GEN_56, + _GEN_57, + _GEN_58, + _GEN_59, + _GEN_60, + _GEN_61, + _GEN_62, + _GEN_63, + _GEN_64, + _GEN_65, + _GEN_66, + _GEN_67, + _GEN_68, + _GEN_69, + _GEN_70, + _GEN_71, + _GEN_72, + _GEN_73, + _GEN_74, + _GEN_75, + _GEN_76, + _GEN_77, + _GEN_78, + _GEN_79, + _GEN_80, + _GEN_81, + _GEN_82, + _GEN_83, + _GEN_84, + _GEN_85, + _GEN_86, + _GEN_87, + _GEN_88, + _GEN_89, + _GEN_90, + _GEN_91, + _GEN_92, + _GEN_93, + _GEN_94, + _GEN_95, + _GEN_96, + _GEN_97, + _GEN_98, + _GEN_99, + _GEN_100, + _GEN_101, + _GEN_102, + _GEN_103, + _GEN_104, + _GEN_105, + _GEN_106, + _GEN_107, + _GEN_108, + _GEN_109, + _GEN_110, + _GEN_111, + _GEN_112, + _GEN_113, + _GEN_114, + _GEN_115, + _GEN_116, + _GEN_117, + _GEN_118, + _GEN_119, + _GEN_120, + _GEN_121, + _GEN_122, + _GEN_123, + _GEN_124, + _GEN_125, + _GEN_126, + _GEN_127, + _GEN_128, + _GEN_129, + _GEN_130, + _GEN_131, + _GEN_132, + _GEN_133, + _GEN_134, + _GEN_135, + _GEN_136, + _GEN_137, + _GEN_138, + _GEN_139, + _GEN_140, + _GEN_141, + _GEN_142, + _GEN_143, + _GEN_144, + _GEN_145, + _GEN_146, + _GEN_147, + _GEN_148, + _GEN_149, + _GEN_150, + _GEN_151, + _GEN_152, + _GEN_153, + _GEN_154, + _GEN_155, + _GEN_156, + _GEN_157, + _GEN_158, + _GEN_159, + _GEN_160, + _GEN_161, + _GEN_162, + _GEN_163, + _GEN_164, + _GEN_165, + _GEN_166, + _GEN_167, + _GEN_168, + _GEN_169, + _GEN_170, + _GEN_171, + _GEN_172, + _GEN_173, + _GEN_174, + _GEN_175, + _GEN_176, + _GEN_177, + _GEN_178, + _GEN_179, + _GEN_180, + _GEN_181, + _GEN_182, + _GEN_183, + _GEN_184, + _GEN_185, + write_fail, + write_fail_1, + write_fail_2, + write_fail_3, + write_fail_4, + write_fail_5, + write_fail_6, + write_fail_7, + write_fail_8, + write_fail_9, + write_fail_10, + write_fail_11, + write_fail_12, + write_fail_13, + write_fail_14, + scoreboard_error, + clock +); + + `ifndef SYNTHESIS + wire [2:0] _GEN_186 = {2'h0, _GEN_5}; + always @(posedge clock) begin + if (~reset & {1'h0, {1'h0, _GEN_1} + {1'h0, _GEN} + {1'h0, _GEN_0}} + + {1'h0, {1'h0, _GEN_4} + {1'h0, _GEN_2} + {1'h0, _GEN_3}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_8} + {1'h0, _GEN_6} + {1'h0, _GEN_7}} + + {1'h0, {1'h0, _GEN_11} + {1'h0, _GEN_9} + {1'h0, _GEN_10}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_14} + {1'h0, _GEN_12} + {1'h0, _GEN_13}} + + {1'h0, {1'h0, _GEN_17} + {1'h0, _GEN_15} + {1'h0, _GEN_16}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_20} + {1'h0, _GEN_18} + {1'h0, _GEN_19}} + + {1'h0, {1'h0, _GEN_23} + {1'h0, _GEN_21} + {1'h0, _GEN_22}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_26} + {1'h0, _GEN_24} + {1'h0, _GEN_25}} + + {1'h0, {1'h0, _GEN_29} + {1'h0, _GEN_27} + {1'h0, _GEN_28}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_32} + {1'h0, _GEN_30} + {1'h0, _GEN_31}} + + {1'h0, {1'h0, _GEN_35} + {1'h0, _GEN_33} + {1'h0, _GEN_34}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_38} + {1'h0, _GEN_36} + {1'h0, _GEN_37}} + + {1'h0, {1'h0, _GEN_41} + {1'h0, _GEN_39} + {1'h0, _GEN_40}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_44} + {1'h0, _GEN_42} + {1'h0, _GEN_43}} + + {1'h0, {1'h0, _GEN_47} + {1'h0, _GEN_45} + {1'h0, _GEN_46}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_50} + {1'h0, _GEN_48} + {1'h0, _GEN_49}} + + {1'h0, {1'h0, _GEN_53} + {1'h0, _GEN_51} + {1'h0, _GEN_52}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_56} + {1'h0, _GEN_54} + {1'h0, _GEN_55}} + + {1'h0, {1'h0, _GEN_59} + {1'h0, _GEN_57} + {1'h0, _GEN_58}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_62} + {1'h0, _GEN_60} + {1'h0, _GEN_61}} + + {1'h0, {1'h0, _GEN_65} + {1'h0, _GEN_63} + {1'h0, _GEN_64}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_68} + {1'h0, _GEN_66} + {1'h0, _GEN_67}} + + {1'h0, {1'h0, _GEN_71} + {1'h0, _GEN_69} + {1'h0, _GEN_70}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_74} + {1'h0, _GEN_72} + {1'h0, _GEN_73}} + + {1'h0, {1'h0, _GEN_77} + {1'h0, _GEN_75} + {1'h0, _GEN_76}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_80} + {1'h0, _GEN_78} + {1'h0, _GEN_79}} + + {1'h0, {1'h0, _GEN_83} + {1'h0, _GEN_81} + {1'h0, _GEN_82}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_86} + {1'h0, _GEN_84} + {1'h0, _GEN_85}} + + {1'h0, {1'h0, _GEN_89} + {1'h0, _GEN_87} + {1'h0, _GEN_88}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_92} + {1'h0, _GEN_90} + {1'h0, _GEN_91}} + + {1'h0, {1'h0, _GEN_95} + {1'h0, _GEN_93} + {1'h0, _GEN_94}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_98} + {1'h0, _GEN_96} + {1'h0, _GEN_97}} + + {1'h0, + {1'h0, _GEN_101} + {1'h0, _GEN_99} + {1'h0, _GEN_100}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_104} + {1'h0, _GEN_102} + {1'h0, _GEN_103}} + + {1'h0, + {1'h0, _GEN_107} + {1'h0, _GEN_105} + {1'h0, _GEN_106}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_110} + {1'h0, _GEN_108} + {1'h0, _GEN_109}} + + {1'h0, + {1'h0, _GEN_113} + {1'h0, _GEN_111} + {1'h0, _GEN_112}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_116} + {1'h0, _GEN_114} + {1'h0, _GEN_115}} + + {1'h0, + {1'h0, _GEN_119} + {1'h0, _GEN_117} + {1'h0, _GEN_118}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_122} + {1'h0, _GEN_120} + {1'h0, _GEN_121}} + + {1'h0, + {1'h0, _GEN_125} + {1'h0, _GEN_123} + {1'h0, _GEN_124}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_128} + {1'h0, _GEN_126} + {1'h0, _GEN_127}} + + {1'h0, + {1'h0, _GEN_131} + {1'h0, _GEN_129} + {1'h0, _GEN_130}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_134} + {1'h0, _GEN_132} + {1'h0, _GEN_133}} + + {1'h0, + {1'h0, _GEN_137} + {1'h0, _GEN_135} + {1'h0, _GEN_136}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_140} + {1'h0, _GEN_138} + {1'h0, _GEN_139}} + + {1'h0, + {1'h0, _GEN_143} + {1'h0, _GEN_141} + {1'h0, _GEN_142}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_146} + {1'h0, _GEN_144} + {1'h0, _GEN_145}} + + {1'h0, + {1'h0, _GEN_149} + {1'h0, _GEN_147} + {1'h0, _GEN_148}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_152} + {1'h0, _GEN_150} + {1'h0, _GEN_151}} + + {1'h0, + {1'h0, _GEN_155} + {1'h0, _GEN_153} + {1'h0, _GEN_154}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_158} + {1'h0, _GEN_156} + {1'h0, _GEN_157}} + + {1'h0, + {1'h0, _GEN_161} + {1'h0, _GEN_159} + {1'h0, _GEN_160}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_164} + {1'h0, _GEN_162} + {1'h0, _GEN_163}} + + {1'h0, + {1'h0, _GEN_167} + {1'h0, _GEN_165} + {1'h0, _GEN_166}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_170} + {1'h0, _GEN_168} + {1'h0, _GEN_169}} + + {1'h0, + {1'h0, _GEN_173} + {1'h0, _GEN_171} + {1'h0, _GEN_172}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_176} + {1'h0, _GEN_174} + {1'h0, _GEN_175}} + + {1'h0, + {1'h0, _GEN_179} + {1'h0, _GEN_177} + {1'h0, _GEN_178}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, {1'h0, _GEN_182} + {1'h0, _GEN_180} + {1'h0, _GEN_181}} + + {1'h0, + {1'h0, _GEN_185} + {1'h0, _GEN_183} + {1'h0, _GEN_184}} > _GEN_186) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:148\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_1) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_2) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_3) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_4) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_5) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_6) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_7) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_8) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_9) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_10) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_11) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_12) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_13) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & write_fail_14) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:234\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & scoreboard_error) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Regfile.scala:241\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/CircularBufferMulti_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module CircularBufferMulti_Verification_Assert( + input [3:0] io_nEnqueued, + input [2:0] io_enqValid, + io_deqReady, + input reset, + input [3:0] _GEN, + input clock +); + + `ifndef SYNTHESIS + wire [4:0] _GEN_0 = {1'h0, io_nEnqueued}; + wire [4:0] _GEN_1 = {2'h0, io_enqValid}; + always @(posedge clock) begin + if (~reset & {1'h0, _GEN_0 + _GEN_1} - {3'h0, io_deqReady} > {2'h0, _GEN}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at CircularBufferMulti.scala:43\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_1 > {1'h0, _GEN} - _GEN_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at CircularBufferMulti.scala:44\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, io_deqReady} > io_nEnqueued) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at CircularBufferMulti.scala:46\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/InstructionBuffer_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module InstructionBuffer_Verification_Assert( + input _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + reset, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & (~_GEN & _GEN_0 | ~_GEN_0 & _GEN_1 | ~_GEN_1 & _GEN_2)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed: OneHotInOrder - Instructions not dispatched in order.\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/Csr_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Csr_Verification_Assert( + input _GEN, + _GEN_0, + input [11:0] csr_address, + input _GEN_1, + _GEN_2, + _GEN_3, + _GEN_4, + _GEN_5, + _GEN_6, + _GEN_7, + _GEN_8, + _GEN_9, + _GEN_10, + _GEN_11, + _GEN_12, + _GEN_13, + _GEN_14, + _GEN_15, + _GEN_16, + _GEN_17, + _GEN_18, + _GEN_19, + _GEN_20, + _GEN_21, + _GEN_22, + _GEN_23, + _GEN_24, + _GEN_25, + _GEN_26, + _GEN_27, + _GEN_28, + _GEN_29, + _GEN_30, + _GEN_31, + _GEN_32, + _GEN_33, + req_valid, + reset, + io_halted, + io_wfi, + io_fault, + io_rs1_valid, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & req_valid + & ~(_GEN | _GEN_0 | _GEN_1 | csr_address == 12'h8 | csr_address == 12'h9 + | csr_address == 12'hA | _GEN_2 | _GEN_3 | _GEN_4 | _GEN_5 | _GEN_6 | _GEN_7 + | _GEN_8 | _GEN_9 | csr_address == 12'h7A0 | csr_address == 12'h7A1 + | csr_address == 12'h7A2 | csr_address == 12'h7A4 | csr_address == 12'h7B0 + | csr_address == 12'h7B1 | csr_address == 12'h7B2 | csr_address == 12'h7B3 + | _GEN_10 | _GEN_11 | _GEN_12 | _GEN_13 | _GEN_14 | _GEN_15 | _GEN_16 + | _GEN_17 | _GEN_18 | _GEN_19 | _GEN_20 | _GEN_21 | _GEN_22 | _GEN_23 + | csr_address == 12'hC20 | csr_address == 12'hC21 | csr_address == 12'hC22 + | _GEN_24 | _GEN_25 | _GEN_26 | _GEN_27 | _GEN_28 | _GEN_29 | _GEN_30 + | _GEN_31 | _GEN_32 | _GEN_33)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Csr.scala:301\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_fault & ~io_halted & ~io_wfi) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Csr.scala:373\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & req_valid & ~io_rs1_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Csr.scala:603\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/Alu_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Alu_Verification_Assert( + input io_rs1_valid, + _GEN, + valid, + reset, + io_rs2_valid, + _rs1Only_WIRE_5, + _rs1Only_WIRE_4, + _rs1Only_WIRE_7, + _rs1Only_WIRE_6, + _rs1Only_WIRE_1, + _rs1Only_WIRE_0, + _rs1Only_WIRE_3, + _rs1Only_WIRE_2, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & valid & ~io_rs1_valid & ~_GEN) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Alu.scala:159\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & valid & ~io_rs2_valid + & {_rs1Only_WIRE_7, + _rs1Only_WIRE_6, + _rs1Only_WIRE_5, + _rs1Only_WIRE_4, + _rs1Only_WIRE_3, + _rs1Only_WIRE_2, + _rs1Only_WIRE_1, + _rs1Only_WIRE_0} == 8'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Alu.scala:160\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/Bru_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Bru_Verification_Assert( + input io_rs1_valid, + stateReg_valid, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_1, + _ignore_WIRE_0, + _ignore_WIRE_3, + _ignore_WIRE_2, + reset, + io_rs2_valid, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset + & {~(stateReg_valid & ~io_rs1_valid), + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_3, + _ignore_WIRE_2, + _ignore_WIRE_1, + _ignore_WIRE_0} == 9'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Bru.scala:264\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {~(stateReg_valid & ~io_rs2_valid), + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_3, + _ignore_WIRE_2, + _ignore_WIRE_1, + _ignore_WIRE_0} == 9'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Bru.scala:265\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/Bru_1_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Bru_1_Verification_Assert( + input _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + _GEN_3, + reset, + io_rs1_valid, + stateReg_valid, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_1, + _ignore_WIRE_0, + _ignore_WIRE_3, + _ignore_WIRE_2, + io_rs2_valid, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & (|{_GEN, _GEN_0, _GEN_3, _GEN_1, _GEN_2})) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Bru.scala:162\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {~(stateReg_valid & ~io_rs1_valid), + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_3, + _ignore_WIRE_2, + _ignore_WIRE_1, + _ignore_WIRE_0} == 9'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Bru.scala:264\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {~(stateReg_valid & ~io_rs2_valid), + _ignore_WIRE_7, + _ignore_WIRE_6, + _ignore_WIRE_5, + _ignore_WIRE_4, + _ignore_WIRE_3, + _ignore_WIRE_2, + _ignore_WIRE_1, + _ignore_WIRE_0} == 9'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Bru.scala:265\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FifoX_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FifoX_Verification_Assert( + input reset, + input [3:0] mcount, + _GEN, + input clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & mcount > _GEN) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at FifoX.scala:158\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/LsuV1_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module LsuV1_Verification_Assert( + input [31:0] ctrl_io_out_bits_addr, + input io_dbus_valid, + reset, + input [31:0] io_dbus_addr, + io_dbus_adrx, + input ctrl_io_out_bits_fldst, + ctrl_io_out_bits_sldst, + ctrl_io_out_bits_vldst, + _GEN, + ctrl_io_out_valid, + data_io_out_bits_fldst, + data_io_out_bits_sldst, + data_io_out_valid, + clock +); + + `ifndef SYNTHESIS + wire [1:0] _GEN_0 = {1'h0, _GEN}; + always @(posedge clock) begin + if (~reset & io_dbus_valid & ctrl_io_out_bits_addr[31]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Lsu.scala:949\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_dbus_valid & io_dbus_addr[31]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Lsu.scala:950\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_dbus_valid & io_dbus_adrx[31]) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Lsu.scala:951\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & ~(~ctrl_io_out_valid | {1'h0, ctrl_io_out_bits_vldst} + + {1'h0, ctrl_io_out_bits_sldst} + + {1'h0, ctrl_io_out_bits_fldst} <= _GEN_0)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Lsu.scala:1108\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & ~(~data_io_out_valid | {1'h0, data_io_out_bits_sldst} + + {1'h0, data_io_out_bits_fldst} <= _GEN_0)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Lsu.scala:1109\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/Mlu_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module Mlu_Verification_Assert( + input io_rs1_0_valid, + stage2Input_q_io_deq_valid, + _GEN, + reset, + io_rs2_0_valid, + io_rs1_1_valid, + _GEN_0, + io_rs2_1_valid, + io_rs1_2_valid, + _GEN_1, + io_rs2_2_valid, + io_rs1_3_valid, + _GEN_2, + io_rs2_3_valid, + clock +); + + `ifndef SYNTHESIS + wire _GEN_3 = stage2Input_q_io_deq_valid & _GEN; + wire _GEN_4 = stage2Input_q_io_deq_valid & _GEN_0; + wire _GEN_5 = stage2Input_q_io_deq_valid & _GEN_1; + wire _GEN_6 = stage2Input_q_io_deq_valid & _GEN_2; + always @(posedge clock) begin + if (~reset & _GEN_3 & ~io_rs1_0_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:120\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_3 & ~io_rs2_0_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:121\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_4 & ~io_rs1_1_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:120\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_4 & ~io_rs2_1_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:121\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_5 & ~io_rs1_2_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:120\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_5 & ~io_rs2_2_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:121\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_6 & ~io_rs1_3_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:120\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_6 & ~io_rs2_3_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Mlu.scala:121\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FloatCore_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FloatCore_Verification_Assert( + input [2:0] io_csr_out_frm, + input _GEN, + input [1:0] _GEN_0, + _GEN_1, + input [2:0] _GEN_2, + _GEN_3, + input _GEN_4, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~_GEN_4 + & ~(io_csr_out_frm == 3'h0 | io_csr_out_frm == {2'h0, _GEN} + | io_csr_out_frm == {1'h0, _GEN_0} | io_csr_out_frm == {1'h0, _GEN_1} + | io_csr_out_frm == _GEN_2 | io_csr_out_frm == _GEN_3 + | (&io_csr_out_frm))) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at FloatCore.scala:311\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FRegfile_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FRegfile_Verification_Assert( + input reset, + scoreboard_error, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & scoreboard_error) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at FRegfile.scala:47\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/SCore_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module SCore_Verification_Assert( + input csr_io_rd_valid, + alu_0_io_rd_valid, + bru_0_io_rd_valid, + reset, + _GEN, + alu_1_io_rd_valid, + bru_1_io_rd_valid, + alu_2_io_rd_valid, + bru_2_io_rd_valid, + alu_3_io_rd_valid, + bru_3_io_rd_valid, + clock +); + + `ifndef SYNTHESIS + wire [2:0] _GEN_0 = {2'h0, _GEN}; + always @(posedge clock) begin + if (~reset & {1'h0, {1'h0, csr_io_rd_valid} + {1'h0, alu_0_io_rd_valid}} + + {2'h0, bru_0_io_rd_valid} > _GEN_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at SCore.scala:335\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {1'h0, {1'h0, alu_1_io_rd_valid} + {1'h0, bru_1_io_rd_valid}} > _GEN_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at SCore.scala:335\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {1'h0, {1'h0, alu_2_io_rd_valid} + {1'h0, bru_2_io_rd_valid}} > _GEN_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at SCore.scala:335\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset + & {1'h0, {1'h0, alu_3_io_rd_valid} + {1'h0, bru_3_io_rd_valid}} > _GEN_0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at SCore.scala:335\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FabricArbiter_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FabricArbiter_Verification_Assert( + input io_source_0_readDataAddr_valid, + io_source_0_writeDataAddr_valid, + reset, + io_source_1_readDataAddr_valid, + io_source_1_writeDataAddr_valid, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & io_source_0_readDataAddr_valid & io_source_0_writeDataAddr_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Fabric.scala:31\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_source_1_readDataAddr_valid & io_source_1_writeDataAddr_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Fabric.scala:32\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FabricMux_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FabricMux_Verification_Assert( + input io_source_readDataAddr_valid, + io_source_writeDataAddr_valid, + reset, + _GEN, + _GEN_0, + _GEN_1, + _GEN_2, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & io_source_readDataAddr_valid & io_source_writeDataAddr_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Fabric.scala:68\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & {1'h0, _GEN_1} + {1'h0, _GEN} + {1'h0, _GEN_0} > {1'h0, _GEN_2}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at Fabric.scala:84\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/AxiSlave_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module AxiSlave_Verification_Assert( + input readIssued, + reset, + readDataQueue_io_enq_ready, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & ~(~readIssued | readDataQueue_io_enq_ready)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at AxiSlave.scala:115\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FifoX_1_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FifoX_1_Verification_Assert( + input reset, + input [1:0] mcount, + _GEN, + input clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & mcount > _GEN) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at FifoX.scala:158\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/FifoX_3_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module FifoX_3_Verification_Assert( + input reset, + input [1:0] mcount, + _GEN, + input clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & mcount > _GEN) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at FifoX.scala:158\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "verification/assert/DBus2AxiV1_Verification_Assert.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 + +// Users can define 'STOP_COND' to add an extra gate to stop conditions. +`ifndef STOP_COND_ + `ifdef STOP_COND + `define STOP_COND_ (`STOP_COND) + `else // STOP_COND + `define STOP_COND_ 1 + `endif // STOP_COND +`endif // not def STOP_COND_ + +// Users can define 'ASSERT_VERBOSE_COND' to add an extra gate to assert error printing. +`ifndef ASSERT_VERBOSE_COND_ + `ifdef ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ (`ASSERT_VERBOSE_COND) + `else // ASSERT_VERBOSE_COND + `define ASSERT_VERBOSE_COND_ 1 + `endif // ASSERT_VERBOSE_COND +`endif // not def ASSERT_VERBOSE_COND_ +module DBus2AxiV1_Verification_Assert( + input [4:0] io_dbus_size, + input _GEN, + io_dbus_valid, + reset, + txnActive, + input [1:0] _GEN_0, + readAddrQ_io_count, + input _GEN_1, + input [5:0] io_axi_read_data_bits_id, + input io_axi_read_data_valid, + input [1:0] writeAddrQ_io_count, + writeDataQ_io_count, + input [5:0] io_axi_write_resp_bits_id, + input io_axi_write_resp_valid, + clock +); + + `ifndef SYNTHESIS + always @(posedge clock) begin + if (~reset & io_dbus_valid + & {1'h0, {1'h0, io_dbus_size[0]} + {1'h0, io_dbus_size[1]}} + + {1'h0, + {1'h0, io_dbus_size[2]} + {1'h0, io_dbus_size[3]} + + {1'h0, io_dbus_size[4]}} != {2'h0, _GEN}) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:57\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & txnActive & ~io_dbus_valid) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:63\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_dbus_valid & _GEN_0 == 2'h0) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:86\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_1 & (|readAddrQ_io_count)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:93\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_axi_read_data_valid & (|io_axi_read_data_bits_id)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:133\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_1 & (|writeAddrQ_io_count)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:141\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & _GEN_1 & (|writeDataQ_io_count)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:164\n"); + if (`STOP_COND_) + $fatal; + end + if (~reset & io_axi_write_resp_valid & (|io_axi_write_resp_bits_id)) begin + if (`ASSERT_VERBOSE_COND_) + $error("Assertion failed at DBus2Axi.scala:191\n"); + if (`STOP_COND_) + $fatal; + end + end // always @(posedge) + `endif // not def SYNTHESIS +endmodule + + +// ----- 8< ----- FILE "./RstSync.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A module for synchronizing Asynchronous external reset to +// an internal synchronous deassert reset +// Clock is disabled while reset is asserted to prevent a race +// between clock and reset. +module RstSync + ( + // Input clock + input clk_i, + // Input active-low async reset + input rstn_i, + // Functional clock gate enable. clk_o is enabled when clk_en + // is 1, and we are out of reset + // clk_en is assumed to be synchronous to clk_o or clk_i + input clk_en, + input te, + + // Output clock + output clk_o, + // Output reset active low + output rstn_o); + + localparam RST_DELAY = 2; + localparam CLK_DELAY = 2; + + logic [RST_DELAY + CLK_DELAY - 1 : 0] rst_delay_reg; + always_ff @(posedge clk_i or negedge rstn_i) begin + if (~rstn_i) + rst_delay_reg <= '0; + else + rst_delay_reg <= {rst_delay_reg[RST_DELAY + CLK_DELAY - 2 : 0], 1'b1}; + end + + assign rstn_o = rst_delay_reg[RST_DELAY - 1]; + + logic clk_en_int; + assign clk_en_int = clk_en & rst_delay_reg[CLK_DELAY + RST_DELAY - 1]; + + ClockGate icg(.clk_i(clk_i), + .enable(clk_en_int), + .te(te), + .clk_o(clk_o)); + +`ifndef SYNTHESIS + initial begin + assert (RST_DELAY >= 2); + assert (CLK_DELAY >= 2); + end +`endif +endmodule +// ----- 8< ----- FILE "./ClockGate.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2023 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +// A ClockGate module. The underlying implementation varies based on +// preprocessor. +// Default: ASIC implementation +// USE_GENERIC default: Verilator implementation (adapted from OpenTitan) +// USE_GENERIC and FPGA_XILINX: UltraScale Plus specific clockgate. +module ClockGate( + input clk_i, + input enable, // '1' passthrough, '0' disable. + input te, // test enable + output clk_o +); + +/////////////////////////// +/// ClockGate Selection /// +/////////////////////////// + // Default: Verilator implementation + logic en_latch /* verilator clock_enable */; + always_latch begin + if (!clk_i) begin + en_latch = enable | te; + end + end + assign clk_o = en_latch & clk_i; + +endmodule // ClockGate +// ----- 8< ----- FILE "./registers.svh" ----- 8< ----- + +// Copyright 2018 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +// Common register defines for RTL designs +`ifndef COMMON_CELLS_REGISTERS_SVH_ +`define COMMON_CELLS_REGISTERS_SVH_ + +// Abridged Summary of available FF macros: +// `FF: asynchronous active-low reset (implicit clock and reset) +// `FFAR: asynchronous active-high reset +// `FFARN: asynchronous active-low reset +// `FFSR: synchronous active-high reset +// `FFSRN: synchronous active-low reset +// `FFNR: without reset +// `FFL: load-enable and asynchronous active-low reset (implicit clock and reset) +// `FFLAR: load-enable and asynchronous active-high reset +// `FFLARN: load-enable and asynchronous active-low reset +// `FFLARNC: load-enable and asynchronous active-low reset and synchronous active-high clear +// `FFLSR: load-enable and synchronous active-high reset +// `FFLSRN: load-enable and synchronous active-low reset +// `FFLNR: load-enable without reset + + +// Flip-Flop with asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FF(__q, __d, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFAR(__q, __d, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFARN(__q, __d, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__d); \ + end \ + end + +// Flip-Flop with synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFSR(__q, __d, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : (__d); \ + end + +// Flip-Flop with synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFSRN(__q, __d, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : (__d); \ + end + +// Always-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __clk: clock input +`define FFNR(__q, __d, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__d); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset (implicit clock and reset) +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// Implicit: +// clk_i: clock input +// rst_ni: reset input (asynchronous, active low) +`define FFL(__q, __d, __load, __reset_value) \ + always_ff @(posedge clk_i or negedge rst_ni) begin \ + if (!rst_ni) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst: asynchronous reset +`define FFLAR(__q, __d, __load, __reset_value, __clk, __arst) \ + always_ff @(posedge (__clk) or posedge (__arst)) begin \ + if (__arst) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARN(__q, __d, __load, __reset_value, __clk, __arst_n) \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__load) ? (__d) : (__q); \ + end \ + end + +// Flip-Flop with load-enable and synchronous active-high reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_clk: reset input +`define FFLSR(__q, __d, __load, __reset_value, __clk, __reset_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (__reset_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and synchronous active-low reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __reset_n_clk: reset input +`define FFLSRN(__q, __d, __load, __reset_value, __clk, __reset_n_clk) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__reset_n_clk`" *``/ \ + `endif \ + always_ff @(posedge (__clk)) begin \ + __q <= (!__reset_n_clk) ? (__reset_value) : ((__load) ? (__d) : (__q)); \ + end + +// Flip-Flop with load-enable and asynchronous active-low reset and synchronous clear +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clear: assign reset value into FF +// __reset_value: value assigned upon reset +// __clk: clock input +// __arst_n: asynchronous reset +`define FFLARNC(__q, __d, __load, __clear, __reset_value, __clk, __arst_n) \ + `ifndef VERILATOR \ + /``* synopsys sync_set_reset `"__clear`" *``/ \ + `endif \ + always_ff @(posedge (__clk) or negedge (__arst_n)) begin \ + if (!__arst_n) begin \ + __q <= (__reset_value); \ + end else begin \ + __q <= (__clear) ? (__reset_value) : (__load) ? (__d) : (__q); \ + end \ + end + +// Load-enable Flip-Flop without reset +// __q: Q output of FF +// __d: D input of FF +// __load: load d value into FF +// __clk: clock input +`define FFLNR(__q, __d, __load, __clk) \ + always_ff @(posedge (__clk)) begin \ + __q <= (__load) ? (__d) : (__q); \ + end + +`endif +// ----- 8< ----- FILE "./cf_math_pkg.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2016 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. + +/// cf_math_pkg: Constant Function Implementations of Mathematical Functions for HDL Elaboration +/// +/// This package contains a collection of mathematical functions that are commonly used when defining +/// the value of constants in HDL code. These functions are implemented as Verilog constants +/// functions. Introduced in Verilog 2001 (IEEE Std 1364-2001), a constant function (?? 10.3.5) is a +/// function whose value can be evaluated at compile time or during elaboration. A constant function +/// must be called with arguments that are constants. +package cf_math_pkg; + + /// Ceiled Division of Two Natural Numbers + /// + /// Returns the quotient of two natural numbers, rounded towards plus infinity. + function automatic integer ceil_div (input longint dividend, input longint divisor); + automatic longint remainder; + + // pragma translate_off + `ifndef VERILATOR + if (dividend < 0) begin + $fatal(1, "Dividend %0d is not a natural number!", dividend); + end + + if (divisor < 0) begin + $fatal(1, "Divisor %0d is not a natural number!", divisor); + end + + if (divisor == 0) begin + $fatal(1, "Division by zero!"); + end + `endif + // pragma translate_on + + remainder = dividend; + for (ceil_div = 0; remainder > 0; ceil_div++) begin + remainder = remainder - divisor; + end + endfunction + + /// Index width required to be able to represent up to `num_idx` indices as a binary + /// encoded signal. + /// Ensures that the minimum width if an index signal is `1`, regardless of parametrization. + /// + /// Sample usage in type definition: + /// As parameter: + /// `parameter type idx_t = logic[cf_math_pkg::idx_width(NumIdx)-1:0]` + /// As typedef: + /// `typedef logic [cf_math_pkg::idx_width(NumIdx)-1:0] idx_t` + function automatic integer unsigned idx_width (input integer unsigned num_idx); + return (num_idx > 32'd1) ? unsigned'($clog2(num_idx)) : 32'd1; + endfunction + +endpackage +// ----- 8< ----- FILE "./lzc.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright (c) 2018 - 2019 ETH Zurich, University of Bologna +// All rights reserved. +// +// This code is under development and not yet released to the public. +// Until it is released, the code is under the copyright of ETH Zurich and +// the University of Bologna, and may contain confidential and/or unpublished +// work. Any reuse/redistribution is strictly forbidden without written +// permission from ETH Zurich. +// +// Bug fixes and contributions will eventually be released under the +// SolderPad open hardware license in the context of the PULP platform +// (http://www.pulp-platform.org), under the copyright of ETH Zurich and the +// University of Bologna. + +/// A trailing zero counter / leading zero counter. +/// Set MODE to 0 for trailing zero counter => cnt_o is the number of trailing zeros (from the LSB) +/// Set MODE to 1 for leading zero counter => cnt_o is the number of leading zeros (from the MSB) +/// If the input does not contain a zero, `empty_o` is asserted. Additionally `cnt_o` contains +/// the maximum number of zeros - 1. For example: +/// in_i = 000_0000, empty_o = 1, cnt_o = 6 (mode = 0) +/// in_i = 000_0001, empty_o = 0, cnt_o = 0 (mode = 0) +/// in_i = 000_1000, empty_o = 0, cnt_o = 3 (mode = 0) +/// Furthermore, this unit contains a more efficient implementation for Verilator (simulation only). +/// This speeds up simulation significantly. +module lzc #( + /// The width of the input vector. + parameter int unsigned WIDTH = 2, + /// Mode selection: 0 -> trailing zero, 1 -> leading zero + parameter bit MODE = 1'b0, + /// Dependent parameter. Do **not** change! + /// + /// Width of the output signal with the zero count. + parameter int unsigned CNT_WIDTH = cf_math_pkg::idx_width(WIDTH) +) ( + /// Input vector to be counted. + input logic [WIDTH-1:0] in_i, + /// Count of the leading / trailing zeros. + output logic [CNT_WIDTH-1:0] cnt_o, + /// Counter is empty: Asserted if all bits in in_i are zero. + output logic empty_o +); + + if (WIDTH == 1) begin : gen_degenerate_lzc + + assign cnt_o[0] = !in_i[0]; + assign empty_o = !in_i[0]; + + end else begin : gen_lzc + + localparam int unsigned NumLevels = $clog2(WIDTH); + + // pragma translate_off + initial begin + assert(WIDTH > 0) else $fatal(1, "input must be at least one bit wide"); + end + // pragma translate_on + + logic [WIDTH-1:0][NumLevels-1:0] index_lut; + logic [2**NumLevels-1:0] sel_nodes; + logic [2**NumLevels-1:0][NumLevels-1:0] index_nodes; + + logic [WIDTH-1:0] in_tmp; + + // reverse vector if required + always_comb begin : flip_vector + for (int unsigned i = 0; i < WIDTH; i++) begin + in_tmp[i] = (MODE) ? in_i[WIDTH-1-i] : in_i[i]; + end + end + + for (genvar j = 0; unsigned'(j) < WIDTH; j++) begin : g_index_lut + assign index_lut[j] = (NumLevels)'(unsigned'(j)); + end + + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : g_levels + if (unsigned'(level) == NumLevels - 1) begin : g_last_level + for (genvar k = 0; k < 2 ** level; k++) begin : g_level + // if two successive indices are still in the vector... + if (unsigned'(k) * 2 < WIDTH - 1) begin : g_reduce + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2] | in_tmp[k * 2 + 1]; + assign index_nodes[2 ** level - 1 + k] = (in_tmp[k * 2] == 1'b1) + ? index_lut[k * 2] : + index_lut[k * 2 + 1]; + end + // if only the first index is still in the vector... + if (unsigned'(k) * 2 == WIDTH - 1) begin : g_base + assign sel_nodes[2 ** level - 1 + k] = in_tmp[k * 2]; + assign index_nodes[2 ** level - 1 + k] = index_lut[k * 2]; + end + // if index is out of range + if (unsigned'(k) * 2 > WIDTH - 1) begin : g_out_of_range + assign sel_nodes[2 ** level - 1 + k] = 1'b0; + assign index_nodes[2 ** level - 1 + k] = '0; + end + end + end else begin : g_not_last_level + for (genvar l = 0; l < 2 ** level; l++) begin : g_level + assign sel_nodes[2 ** level - 1 + l] = + sel_nodes[2 ** (level + 1) - 1 + l * 2] | sel_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + assign index_nodes[2 ** level - 1 + l] = (sel_nodes[2 ** (level + 1) - 1 + l * 2] == 1'b1) + ? index_nodes[2 ** (level + 1) - 1 + l * 2] : + index_nodes[2 ** (level + 1) - 1 + l * 2 + 1]; + end + end + end + + assign cnt_o = NumLevels > unsigned'(0) ? index_nodes[0] : {($clog2(WIDTH)) {1'b0}}; + assign empty_o = NumLevels > unsigned'(0) ? ~sel_nodes[0] : ~(|in_i); + + end : gen_lzc + +endmodule : lzc +// ----- 8< ----- FILE "./rr_arb_tree.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// Author: Michael Schaffner , ETH Zurich +// Wolfgang Roenninger , ETH Zurich +// Date: 02.04.2019 +// Description: logarithmic arbitration tree with round robin arbitration scheme. + +/// The rr_arb_tree employs non-starving round robin-arbitration - i.e., the priorities +/// rotate each cycle. +/// +/// ## Fair vs. unfair Arbitration +/// +/// This refers to fair throughput distribution when not all inputs have active requests. +/// This module has an internal state `rr_q` which defines the highest priority input. (When +/// `ExtPrio` is `1'b1` this state is provided from the outside.) The arbitration tree will +/// choose the input with the same index as currently defined by the state if it has an active +/// request. Otherwise a *random* other active input is selected. The parameter `FairArb` is used +/// to distinguish between two methods of calculating the next state. +/// * `1'b0`: The next state is calculated by advancing the current state by one. This leads to the +/// state being calculated without the context of the active request. Leading to an +/// unfair throughput distribution if not all inputs have active requests. +/// * `1'b1`: The next state jumps to the next unserved request with higher index. +/// This is achieved by using two trailing-zero-counters (`lzc`). The upper has the masked +/// `req_i` signal with all indices which will have a higher priority in the next state. +/// The trailing zero count defines the input index with the next highest priority after +/// the current one is served. When the upper is empty the lower `lzc` provides the +/// wrapped index if there are outstanding requests with lower or same priority. +/// The implication of throughput fairness on the module timing are: +/// * The trailing zero counter (`lzc`) has a loglog relation of input to output timing. This means +/// that in this module the input to register path scales with Log(Log(`NumIn`)). +/// * The `rr_arb_tree` data multiplexing scales with Log(`NumIn`). This means that the input to output +/// timing path of this module also scales scales with Log(`NumIn`). +/// This implies that in this module the input to output path is always longer than the input to +/// register path. As the output data usually also terminates in a register the parameter `FairArb` +/// only has implications on the area. When it is `1'b0` a static plus one adder is instantiated. +/// If it is `1'b1` two `lzc`, a masking logic stage and a two input multiplexer are instantiated. +/// However these are small in respect of the data multiplexers needed, as the width of the `req_i` +/// signal is usually less as than `DataWidth`. +module rr_arb_tree #( + /// Number of inputs to be arbitrated. + parameter int unsigned NumIn = 64, + /// Data width of the payload in bits. Not needed if `DataType` is overwritten. + parameter int unsigned DataWidth = 32, + /// Data type of the payload, can be overwritten with custom type. Only use of `DataWidth`. + parameter type DataType = logic [DataWidth-1:0], + /// The `ExtPrio` option allows to override the internal round robin counter via the + /// `rr_i` signal. This can be useful in case multiple arbiters need to have + /// rotating priorities that are operating in lock-step. If static priority arbitration + /// is needed, just connect `rr_i` to '0. + /// + /// Set to 1'b1 to enable. + parameter bit ExtPrio = 1'b0, + /// If `AxiVldRdy` is set, the req/gnt signals are compliant with the AXI style vld/rdy + /// handshake. Namely, upstream vld (req) must not depend on rdy (gnt), as it can be deasserted + /// again even though vld is asserted. Enabling `AxiVldRdy` leads to a reduction of arbiter + /// delay and area. + /// + /// Set to `1'b1` to treat req/gnt as vld/rdy. + parameter bit AxiVldRdy = 1'b0, + /// The `LockIn` option prevents the arbiter from changing the arbitration + /// decision when the arbiter is disabled. I.e., the index of the first request + /// that wins the arbitration will be locked in case the destination is not + /// able to grant the request in the same cycle. + /// + /// Set to `1'b1` to enable. + parameter bit LockIn = 1'b0, + /// When set, ensures that throughput gets distributed evenly between all inputs. + /// + /// Set to `1'b0` to disable. + parameter bit FairArb = 1'b1, + /// Dependent parameter, do **not** overwrite. + /// Width of the arbitration priority signal and the arbitrated index. + parameter int unsigned IdxWidth = (NumIn > 32'd1) ? unsigned'($clog2(NumIn)) : 32'd1, + /// Dependent parameter, do **not** overwrite. + /// Type for defining the arbitration priority and arbitrated index signal. + parameter type idx_t = logic [IdxWidth-1:0] +) ( + /// Clock, positive edge triggered. + input logic clk_i, + /// Asynchronous reset, active low. + input logic rst_ni, + /// Clears the arbiter state. Only used if `ExtPrio` is `1'b0` or `LockIn` is `1'b1`. + input logic flush_i, + /// External round-robin priority. Only used if `ExtPrio` is `1'b1.` + input idx_t rr_i, + /// Input requests arbitration. + input logic [NumIn-1:0] req_i, + /* verilator lint_off UNOPTFLAT */ + /// Input request is granted. + output logic [NumIn-1:0] gnt_o, + /* verilator lint_on UNOPTFLAT */ + /// Input data for arbitration. + input DataType [NumIn-1:0] data_i, + /// Output request is valid. + output logic req_o, + /// Output request is granted. + input logic gnt_i, + /// Output data. + output DataType data_o, + /// Index from which input the data came from. + output idx_t idx_o +); + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + // Default SVA reset + default disable iff (!rst_ni || flush_i); + `endif + `endif + // pragma translate_on + + // just pass through in this corner case + if (NumIn == unsigned'(1)) begin : gen_pass_through + assign req_o = req_i[0]; + assign gnt_o[0] = gnt_i; + assign data_o = data_i[0]; + assign idx_o = '0; + // non-degenerate cases + end else begin : gen_arbiter + localparam int unsigned NumLevels = unsigned'($clog2(NumIn)); + + /* verilator lint_off UNOPTFLAT */ + idx_t [2**NumLevels-2:0] index_nodes; // used to propagate the indices + DataType [2**NumLevels-2:0] data_nodes; // used to propagate the data + logic [2**NumLevels-2:0] gnt_nodes; // used to propagate the grant to masters + logic [2**NumLevels-2:0] req_nodes; // used to propagate the requests to slave + /* lint_off */ + idx_t rr_q; + logic [NumIn-1:0] req_d; + + // the final arbitration decision can be taken from the root of the tree + assign req_o = req_nodes[0]; + assign data_o = data_nodes[0]; + assign idx_o = index_nodes[0]; + + if (ExtPrio) begin : gen_ext_rr + assign rr_q = rr_i; + assign req_d = req_i; + end else begin : gen_int_rr + idx_t rr_d; + + // lock arbiter decision in case we got at least one req and no acknowledge + if (LockIn) begin : gen_lock + logic lock_d, lock_q; + logic [NumIn-1:0] req_q; + + assign lock_d = req_o & ~gnt_i; + assign req_d = (lock_q) ? req_q : req_i; + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_lock_reg + if (!rst_ni) begin + lock_q <= '0; + end else begin + if (flush_i) begin + lock_q <= '0; + end else begin + lock_q <= lock_d; + end + end + end + + // pragma translate_off + `ifndef VERILATOR + lock: assert property( + @(posedge clk_i) LockIn |-> req_o && !gnt_i |=> idx_o == $past(idx_o)) else + $fatal (1, "Lock implies same arbiter decision in next cycle if output is not \ + ready."); + + logic [NumIn-1:0] req_tmp; + assign req_tmp = req_q & req_i; + lock_req: assume property( + @(posedge clk_i) LockIn |-> lock_d |=> req_tmp == req_q) else + $fatal (1, "It is disallowed to deassert unserved request signals when LockIn is \ + enabled."); + `endif + // pragma translate_on + + always_ff @(posedge clk_i or negedge rst_ni) begin : p_req_regs + if (!rst_ni) begin + req_q <= '0; + end else begin + if (flush_i) begin + req_q <= '0; + end else begin + req_q <= req_d; + end + end + end + end else begin : gen_no_lock + assign req_d = req_i; + end + + if (FairArb) begin : gen_fair_arb + logic [NumIn-1:0] upper_mask, lower_mask; + idx_t upper_idx, lower_idx, next_idx; + logic upper_empty, lower_empty; + + for (genvar i = 0; i < NumIn; i++) begin : gen_mask + assign upper_mask[i] = (i > rr_q) ? req_d[i] : 1'b0; + assign lower_mask[i] = (i <= rr_q) ? req_d[i] : 1'b0; + end + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_upper ( + .in_i ( upper_mask ), + .cnt_o ( upper_idx ), + .empty_o ( upper_empty ) + ); + + lzc #( + .WIDTH ( NumIn ), + .MODE ( 1'b0 ) + ) i_lzc_lower ( + .in_i ( lower_mask ), + .cnt_o ( lower_idx ), + .empty_o ( /*unused*/ ) + ); + + assign next_idx = upper_empty ? lower_idx : upper_idx; + assign rr_d = (gnt_i && req_o) ? next_idx : rr_q; + + end else begin : gen_unfair_arb + assign rr_d = (gnt_i && req_o) ? ((rr_q == idx_t'(NumIn-1)) ? '0 : rr_q + 1'b1) : rr_q; + end + + // this holds the highest priority + always_ff @(posedge clk_i or negedge rst_ni) begin : p_rr_regs + if (!rst_ni) begin + rr_q <= '0; + end else begin + if (flush_i) begin + rr_q <= '0; + end else begin + rr_q <= rr_d; + end + end + end + end + + assign gnt_nodes[0] = gnt_i; + + // arbiter tree + for (genvar level = 0; unsigned'(level) < NumLevels; level++) begin : gen_levels + for (genvar l = 0; l < 2**level; l++) begin : gen_level + // local select signal + logic sel; + // index calcs + localparam int unsigned Idx0 = 2**level-1+l;// current node + localparam int unsigned Idx1 = 2**(level+1)-1+l*2; + ////////////////////////////////////////////////////////////// + // uppermost level where data is fed in from the inputs + if (unsigned'(level) == NumLevels-1) begin : gen_first_level + // if two successive indices are still in the vector... + if (unsigned'(l) * 2 < NumIn-1) begin : gen_reduce + assign req_nodes[Idx0] = req_d[l*2] | req_d[l*2+1]; + + // arbitration: round robin + assign sel = ~req_d[l*2] | req_d[l*2+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = idx_t'(sel); + assign data_nodes[Idx0] = (sel) ? data_i[l*2+1] : data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]) & ~sel; + assign gnt_o[l*2+1] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2+1]) & sel; + end + // if only the first index is still in the vector... + if (unsigned'(l) * 2 == NumIn-1) begin : gen_first + assign req_nodes[Idx0] = req_d[l*2]; + assign index_nodes[Idx0] = '0;// always zero in this case + assign data_nodes[Idx0] = data_i[l*2]; + assign gnt_o[l*2] = gnt_nodes[Idx0] & (AxiVldRdy | req_d[l*2]); + end + // if index is out of range, fill up with zeros (will get pruned) + if (unsigned'(l) * 2 > NumIn-1) begin : gen_out_of_range + assign req_nodes[Idx0] = 1'b0; + assign index_nodes[Idx0] = idx_t'('0); + assign data_nodes[Idx0] = DataType'('0); + end + ////////////////////////////////////////////////////////////// + // general case for other levels within the tree + end else begin : gen_other_levels + assign req_nodes[Idx0] = req_nodes[Idx1] | req_nodes[Idx1+1]; + + // arbitration: round robin + assign sel = ~req_nodes[Idx1] | req_nodes[Idx1+1] & rr_q[NumLevels-1-level]; + + assign index_nodes[Idx0] = (sel) ? + idx_t'({1'b1, index_nodes[Idx1+1][NumLevels-unsigned'(level)-2:0]}) : + idx_t'({1'b0, index_nodes[Idx1][NumLevels-unsigned'(level)-2:0]}); + + assign data_nodes[Idx0] = (sel) ? data_nodes[Idx1+1] : data_nodes[Idx1]; + assign gnt_nodes[Idx1] = gnt_nodes[Idx0] & ~sel; + assign gnt_nodes[Idx1+1] = gnt_nodes[Idx0] & sel; + end + ////////////////////////////////////////////////////////////// + end + end + + // pragma translate_off + `ifndef VERILATOR + `ifndef XSIM + initial begin : p_assert + assert(NumIn) + else $fatal(1, "Input must be at least one element wide."); + assert(!(LockIn && ExtPrio)) + else $fatal(1,"Cannot use LockIn feature together with external ExtPrio."); + end + + hot_one : assert property( + @(posedge clk_i) $onehot0(gnt_o)) + else $fatal (1, "Grant signal must be hot1 or zero."); + + gnt0 : assert property( + @(posedge clk_i) |gnt_o |-> gnt_i) + else $fatal (1, "Grant out implies grant in."); + + gnt1 : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> |gnt_o) + else $fatal (1, "Req out and grant in implies grant out."); + + gnt_idx : assert property( + @(posedge clk_i) req_o |-> gnt_i |-> gnt_o[idx_o]) + else $fatal (1, "Idx_o / gnt_o do not match."); + + req0 : assert property( + @(posedge clk_i) |req_i |-> req_o) + else $fatal (1, "Req in implies req out."); + + req1 : assert property( + @(posedge clk_i) req_o |-> |req_i) + else $fatal (1, "Req out implies req in."); + `endif + `endif + // pragma translate_on + end + +endmodule : rr_arb_tree +// ----- 8< ----- FILE "./fpnew_pkg.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +package fpnew_pkg; + + // --------- + // FP TYPES + // --------- + // | Enumerator | Format | Width | EXP_BITS | MAN_BITS + // |:----------:|------------------|-------:|:--------:|:--------: + // | FP32 | IEEE binary32 | 32 bit | 8 | 23 + // | FP64 | IEEE binary64 | 64 bit | 11 | 52 + // | FP16 | IEEE binary16 | 16 bit | 5 | 10 + // | FP8 | binary8 | 8 bit | 5 | 2 + // | FP16ALT | binary16alt | 16 bit | 8 | 7 + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + // Encoding for a format + typedef struct packed { + int unsigned exp_bits; + int unsigned man_bits; + } fp_encoding_t; + + localparam int unsigned NUM_FP_FORMATS = 5; // change me to add formats + localparam int unsigned FP_FORMAT_BITS = $clog2(NUM_FP_FORMATS); + + // FP formats + typedef enum logic [FP_FORMAT_BITS-1:0] { + FP32 = 'd0, + FP64 = 'd1, + FP16 = 'd2, + FP8 = 'd3, + FP16ALT = 'd4 + // add new formats here + } fp_format_e; + + // Encodings for supported FP formats + localparam fp_encoding_t [0:NUM_FP_FORMATS-1] FP_ENCODINGS = '{ + '{8, 23}, // IEEE binary32 (single) + '{11, 52}, // IEEE binary64 (double) + '{5, 10}, // IEEE binary16 (half) + '{5, 2}, // custom binary8 + '{8, 7} // custom binary16alt + // add new formats here + }; + + typedef logic [0:NUM_FP_FORMATS-1] fmt_logic_t; // Logic indexed by FP format (for masks) + typedef logic [0:NUM_FP_FORMATS-1][31:0] fmt_unsigned_t; // Unsigned indexed by FP format + + localparam fmt_logic_t CPK_FORMATS = 5'b11000; // FP32 and FP64 can provide CPK only + + // --------- + // INT TYPES + // --------- + // | Enumerator | Width | + // |:----------:|-------:| + // | INT8 | 8 bit | + // | INT16 | 16 bit | + // | INT32 | 32 bit | + // | INT64 | 64 bit | + // *NOTE:* Add new formats only at the end of the enumeration for backwards compatibilty! + + localparam int unsigned NUM_INT_FORMATS = 4; // change me to add formats + localparam int unsigned INT_FORMAT_BITS = $clog2(NUM_INT_FORMATS); + + // Int formats + typedef enum logic [INT_FORMAT_BITS-1:0] { + INT8, + INT16, + INT32, + INT64 + // add new formats here + } int_format_e; + + // Returns the width of an INT format by index + function automatic int unsigned int_width(int_format_e ifmt); + unique case (ifmt) + INT8: return 8; + INT16: return 16; + INT32: return 32; + INT64: return 64; + default: begin + // pragma translate_off + $fatal(1, "Invalid INT format supplied"); + // pragma translate_on + // just return any integer to avoid any latches + // hopefully this error is caught by simulation + return INT8; + end + endcase + endfunction + + typedef logic [0:NUM_INT_FORMATS-1] ifmt_logic_t; // Logic indexed by INT format (for masks) + + // -------------- + // FP OPERATIONS + // -------------- + localparam int unsigned NUM_OPGROUPS = 4; + + // Each FP operation belongs to an operation group + typedef enum logic [1:0] { + ADDMUL, DIVSQRT, NONCOMP, CONV + } opgroup_e; + + localparam int unsigned OP_BITS = 4; + + typedef enum logic [OP_BITS-1:0] { + FMADD, FNMSUB, ADD, MUL, // ADDMUL operation group + DIV, SQRT, // DIVSQRT operation group + SGNJ, MINMAX, CMP, CLASSIFY, // NONCOMP operation group + F2F, F2I, I2F, CPKAB, CPKCD // CONV operation group + } operation_e; + + // ------------------- + // RISC-V FP-SPECIFIC + // ------------------- + // Rounding modes + typedef enum logic [2:0] { + RNE = 3'b000, + RTZ = 3'b001, + RDN = 3'b010, + RUP = 3'b011, + RMM = 3'b100, + ROD = 3'b101, // This mode is not defined in RISC-V FP-SPEC + DYN = 3'b111 + } roundmode_e; + + // Status flags + typedef struct packed { + logic NV; // Invalid + logic DZ; // Divide by zero + logic OF; // Overflow + logic UF; // Underflow + logic NX; // Inexact + } status_t; + + // Information about a floating point value + typedef struct packed { + logic is_normal; // is the value normal + logic is_subnormal; // is the value subnormal + logic is_zero; // is the value zero + logic is_inf; // is the value infinity + logic is_nan; // is the value NaN + logic is_signalling; // is the value a signalling NaN + logic is_quiet; // is the value a quiet NaN + logic is_boxed; // is the value properly NaN-boxed (RISC-V specific) + } fp_info_t; + + // Classification mask + typedef enum logic [9:0] { + NEGINF = 10'b00_0000_0001, + NEGNORM = 10'b00_0000_0010, + NEGSUBNORM = 10'b00_0000_0100, + NEGZERO = 10'b00_0000_1000, + POSZERO = 10'b00_0001_0000, + POSSUBNORM = 10'b00_0010_0000, + POSNORM = 10'b00_0100_0000, + POSINF = 10'b00_1000_0000, + SNAN = 10'b01_0000_0000, + QNAN = 10'b10_0000_0000 + } classmask_e; + + // ------------------ + // FPU configuration + // ------------------ + // Pipelining registers can be inserted (at elaboration time) into operational units + typedef enum logic [1:0] { + BEFORE, // registers are inserted at the inputs of the unit + AFTER, // registers are inserted at the outputs of the unit + INSIDE, // registers are inserted at predetermined (suboptimal) locations in the unit + DISTRIBUTED // registers are evenly distributed, INSIDE >= AFTER >= BEFORE + } pipe_config_t; + + // Arithmetic units can be arranged in parallel (per format), merged (multi-format) or not at all. + typedef enum logic [1:0] { + DISABLED, // arithmetic units are not generated + PARALLEL, // arithmetic units are generated in prallel slices, one for each format + MERGED // arithmetic units are contained within a merged unit holding multiple formats + } unit_type_t; + + // Array of unit types indexed by format + typedef unit_type_t [0:NUM_FP_FORMATS-1] fmt_unit_types_t; + + // Array of format-specific unit types by opgroup + typedef fmt_unit_types_t [0:NUM_OPGROUPS-1] opgrp_fmt_unit_types_t; + // same with unsigned + typedef fmt_unsigned_t [0:NUM_OPGROUPS-1] opgrp_fmt_unsigned_t; + + // FPU configuration: features + typedef struct packed { + int unsigned Width; + logic EnableVectors; + logic EnableNanBox; + fmt_logic_t FpFmtMask; + ifmt_logic_t IntFmtMask; + } fpu_features_t; + + localparam fpu_features_t RV64D = '{ + Width: 64, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0011 + }; + + localparam fpu_features_t RV32D = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV32F = '{ + Width: 32, + EnableVectors: 1'b0, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10000, + IntFmtMask: 4'b0010 + }; + + localparam fpu_features_t RV64D_Xsflt = '{ + Width: 64, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b11111, + IntFmtMask: 4'b1111 + }; + + localparam fpu_features_t RV32F_Xsflt = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10111, + IntFmtMask: 4'b1110 + }; + + localparam fpu_features_t RV32F_Xf16alt_Xfvec = '{ + Width: 32, + EnableVectors: 1'b1, + EnableNanBox: 1'b1, + FpFmtMask: 5'b10001, + IntFmtMask: 4'b0110 + }; + + + // FPU configuraion: implementation + typedef struct packed { + opgrp_fmt_unsigned_t PipeRegs; + opgrp_fmt_unit_types_t UnitTypes; + pipe_config_t PipeConfig; + } fpu_implementation_t; + + localparam fpu_implementation_t DEFAULT_NOREGS = '{ + PipeRegs: '{default: 0}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: MERGED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + localparam fpu_implementation_t DEFAULT_SNITCH = '{ + PipeRegs: '{default: 1}, + UnitTypes: '{'{default: PARALLEL}, // ADDMUL + '{default: DISABLED}, // DIVSQRT + '{default: PARALLEL}, // NONCOMP + '{default: MERGED}}, // CONV + PipeConfig: BEFORE + }; + + // ----------------------- + // Synthesis optimization + // ----------------------- + localparam logic DONT_CARE = 1'b1; // the value to assign as don't care + + // ------------------------- + // General helper functions + // ------------------------- + function automatic int minimum(int a, int b); + return (a < b) ? a : b; + endfunction + + function automatic int maximum(int a, int b); + return (a > b) ? a : b; + endfunction + + // ------------------------------------------- + // Helper functions for FP formats and values + // ------------------------------------------- + // Returns the width of a FP format + function automatic int unsigned fp_width(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits + FP_ENCODINGS[fmt].man_bits + 1; + endfunction + + // Returns the widest FP format present + function automatic int unsigned max_fp_width(fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(maximum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the narrowest FP format present + function automatic int unsigned min_fp_width(fmt_logic_t cfg); + automatic int unsigned res = max_fp_width(cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i]) + res = unsigned'(minimum(res, fp_width(fp_format_e'(i)))); + return res; + endfunction + + // Returns the number of expoent bits for a format + function automatic int unsigned exp_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].exp_bits; + endfunction + + // Returns the number of mantissa bits for a format + function automatic int unsigned man_bits(fp_format_e fmt); + return FP_ENCODINGS[fmt].man_bits; + endfunction + + // Returns the bias value for a given format (as per IEEE 754-2008) + function automatic int unsigned bias(fp_format_e fmt); + return unsigned'(2**(FP_ENCODINGS[fmt].exp_bits-1)-1); // symmetrical bias + endfunction + + function automatic fp_encoding_t super_format(fmt_logic_t cfg); + automatic fp_encoding_t res; + res = '0; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + if (cfg[fmt]) begin // only active format + res.exp_bits = unsigned'(maximum(res.exp_bits, exp_bits(fp_format_e'(fmt)))); + res.man_bits = unsigned'(maximum(res.man_bits, man_bits(fp_format_e'(fmt)))); + end + return res; + endfunction + + // ------------------------------------------- + // Helper functions for INT formats and values + // ------------------------------------------- + // Returns the widest INT format present + function automatic int unsigned max_int_width(ifmt_logic_t cfg); + automatic int unsigned res = 0; + for (int ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin + if (cfg[ifmt]) res = maximum(res, int_width(int_format_e'(ifmt))); + end + return res; + endfunction + + // -------------------------------------------------- + // Helper functions for operations and FPU structure + // -------------------------------------------------- + // Returns the operation group of the given operation + function automatic opgroup_e get_opgroup(operation_e op); + unique case (op) + FMADD, FNMSUB, ADD, MUL: return ADDMUL; + DIV, SQRT: return DIVSQRT; + SGNJ, MINMAX, CMP, CLASSIFY: return NONCOMP; + F2F, F2I, I2F, CPKAB, CPKCD: return CONV; + default: return NONCOMP; + endcase + endfunction + + // Returns the number of operands by operation group + function automatic int unsigned num_operands(opgroup_e grp); + unique case (grp) + ADDMUL: return 3; + DIVSQRT: return 2; + NONCOMP: return 2; + CONV: return 3; // vectorial casts use 3 operands + default: return 0; + endcase + endfunction + + // Returns the number of lanes according to width, format and vectors + function automatic int unsigned num_lanes(int unsigned width, fp_format_e fmt, logic vec); + return vec ? width / fp_width(fmt) : 1; // if no vectors, only one lane + endfunction + + // Returns the maximum number of lanes in the FPU according to width, format config and vectors + function automatic int unsigned max_num_lanes(int unsigned width, fmt_logic_t cfg, logic vec); + // return vec ? width / min_fp_width(cfg) : 1; // if no vectors, only one lane + if (vec) begin + automatic int unsigned res = max_fp_width(cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i]) begin + automatic int unsigned format_width = FP_ENCODINGS[i].exp_bits + FP_ENCODINGS[i].man_bits + 1; + res = unsigned'(minimum(res, format_width)); + end + end + return width / res; + end else begin + return 1; + end + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a multiformat slice + function automatic fmt_logic_t get_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format + res[fmt] = cfg[fmt] & (width / fp_width(fp_format_e'(fmt)) > lane_no); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a multiformat slice + function automatic ifmt_logic_t get_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + if ((fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt)))) + res[ifmt] |= icfg[ifmt] && lanefmts[fmt]; + return res; + endfunction + + // Returns a mask of active FP formats that are present in lane lane_no of a CONV slice + function automatic fmt_logic_t get_conv_lane_formats(int unsigned width, + fmt_logic_t cfg, + int unsigned lane_no); + automatic fmt_logic_t res; + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active formats with the number of lanes for that format, CPK at least twice + res[fmt] = cfg[fmt] && ((width / fp_width(fp_format_e'(fmt)) > lane_no) || + (CPK_FORMATS[fmt] && (lane_no < 2))); + return res; + endfunction + + // Returns a mask of active INT formats that are present in lane lane_no of a CONV slice + function automatic ifmt_logic_t get_conv_lane_int_formats(int unsigned width, + fmt_logic_t cfg, + ifmt_logic_t icfg, + int unsigned lane_no); + automatic ifmt_logic_t res; + automatic fmt_logic_t lanefmts; + res = '0; + lanefmts = get_conv_lane_formats(width, cfg, lane_no); + + for (int unsigned ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) + for (int unsigned fmt = 0; fmt < NUM_FP_FORMATS; fmt++) + // Mask active int formats with the width of the float formats + res[ifmt] |= icfg[ifmt] && lanefmts[fmt] && + (fp_width(fp_format_e'(fmt)) == int_width(int_format_e'(ifmt))); + return res; + endfunction + + // Return whether any active format is set as MERGED + function automatic logic any_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return 1'b1; + return 1'b0; + endfunction + + // Return whether the given format is the first active one set as MERGED + function automatic logic is_first_enabled_multi(fp_format_e fmt, + fmt_unit_types_t types, + fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) return (fp_format_e'(i) == fmt); + end + return 1'b0; + endfunction + + // Returns the first format that is active and is set as MERGED + function automatic fp_format_e get_first_enabled_multi(fmt_unit_types_t types, fmt_logic_t cfg); + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) + if (cfg[i] && types[i] == MERGED) + return fp_format_e'(i); + return fp_format_e'(0); + endfunction + + // Returns the largest number of regs that is active and is set as MERGED + function automatic int unsigned get_num_regs_multi(fmt_unsigned_t regs, + fmt_unit_types_t types, + fmt_logic_t cfg); + automatic int unsigned res = 0; + for (int unsigned i = 0; i < NUM_FP_FORMATS; i++) begin + if (cfg[i] && types[i] == MERGED) res = maximum(res, regs[i]); + end + return res; + endfunction + +endpackage +// ----- 8< ----- FILE "./fpnew_cast_multi.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + + + +module fpnew_cast_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, + // FPU configuration + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::maximum(fpnew_pkg::max_fp_width(FpFmtConfig), + fpnew_pkg::max_int_width(IntFmtConfig)), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [WIDTH-1:0] operands_i, // 1 operand + input logic [NUM_FORMATS-1:0] is_boxed_i, // 1 operand + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + // ---------- + // Constants + // ---------- + localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS; + localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig); + + localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig); + + localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits; + localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits; + localparam int unsigned SUPER_BIAS = 2**(SUPER_EXP_BITS - 1) - 1; + + // The internal mantissa includes normal bit or an entire integer + localparam int unsigned INT_MAN_WIDTH = fpnew_pkg::maximum(SUPER_MAN_BITS + 1, MAX_INT_WIDTH); + // If needed, there will be a LZC for renormalization + localparam int unsigned LZC_RESULT_WIDTH = $clog2(INT_MAN_WIDTH); + // The internal exponent must be able to represent the smallest denormal input value as signed + // or the number of bits in an integer + localparam int unsigned INT_EXP_WIDTH = fpnew_pkg::maximum($clog2(MAX_INT_WIDTH), + fpnew_pkg::maximum(SUPER_EXP_BITS, $clog2(SUPER_BIAS + SUPER_MAN_BITS))) + 1; + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [WIDTH-1:0] operands_q; + logic [NUM_FORMATS-1:0] is_boxed_q; + logic op_mod_q; + fpnew_pkg::fp_format_e src_fmt_q; + fpnew_pkg::fp_format_e dst_fmt_q; + fpnew_pkg::int_format_e int_fmt_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][NUM_FORMATS-1:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; + fpnew_pkg::int_format_e [0:NUM_INP_REGS] inp_pipe_int_fmt_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_src_fmt_q[0] = src_fmt_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; + assign inp_pipe_int_fmt_q[0] = int_fmt_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_int_fmt_q[i+1], inp_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0)) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign is_boxed_q = inp_pipe_is_boxed_q[NUM_INP_REGS]; + assign op_mod_q = inp_pipe_op_mod_q[NUM_INP_REGS]; + assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; + assign int_fmt_q = inp_pipe_int_fmt_q[NUM_INP_REGS]; + + // ----------------- + // Input processing + // ----------------- + logic src_is_int, dst_is_int; // if 0, it's a float + + assign src_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::I2F); + assign dst_is_int = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::F2I); + + logic [INT_MAN_WIDTH-1:0] encoded_mant; // input mantissa with implicit bit + + logic [NUM_FORMATS-1:0] fmt_sign; + logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_exponent; + logic [NUM_FORMATS-1:0][INT_MAN_WIDTH-1:0] fmt_mantissa; + logic signed [NUM_FORMATS-1:0][INT_EXP_WIDTH-1:0] fmt_shift_compensation; // for LZC + + fpnew_pkg::fp_info_t [NUM_FORMATS-1:0] info; + + logic [NUM_INT_FORMATS-1:0][INT_MAN_WIDTH-1:0] ifmt_input_val; + logic int_sign; + logic [INT_MAN_WIDTH-1:0] int_value, int_mantissa; + + // FP Input initialization + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + // Classify input + fpnew_classifier #( + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .NumOperands ( 1 ) + ) i_fpnew_classifier ( + .operands_i ( operands_q[FP_WIDTH-1:0] ), + .is_boxed_i ( is_boxed_q[fmt] ), + .info_o ( info[fmt] ) + ); + + assign fmt_sign[fmt] = operands_q[FP_WIDTH-1]; + assign fmt_exponent[fmt] = signed'({1'b0, operands_q[MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[fmt] = {info[fmt].is_normal, operands_q[MAN_BITS-1:0]}; // zero pad + // Compensation for the difference in mantissa widths used for leading-zero count + assign fmt_shift_compensation[fmt] = signed'(INT_MAN_WIDTH - 1 - MAN_BITS); + end else begin : inactive_format + assign info[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled + assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_shift_compensation[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + // Sign-extend INT input + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_sign_extend_int + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format // only active formats + always_comb begin : sign_ext_input + // sign-extend value only if it's signed + ifmt_input_val[ifmt] = '{default: operands_q[INT_WIDTH-1] & ~op_mod_q}; + ifmt_input_val[ifmt][INT_WIDTH-1:0] = operands_q[INT_WIDTH-1:0]; + end + end else begin : inactive_format + assign ifmt_input_val[ifmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + // Construct input mantissa from integer + assign int_value = ifmt_input_val[int_fmt_q]; + assign int_sign = int_value[INT_MAN_WIDTH-1] & ~op_mod_q; // only signed ints are negative + assign int_mantissa = int_sign ? unsigned'(-int_value) : int_value; // get magnitude of negative + + // select mantissa with source format + assign encoded_mant = src_is_int ? int_mantissa : fmt_mantissa[src_fmt_q]; + + // -------------- + // Normalization + // -------------- + logic signed [INT_EXP_WIDTH-1:0] src_bias; // src format bias + logic signed [INT_EXP_WIDTH-1:0] src_exp; // src format exponent (biased) + logic signed [INT_EXP_WIDTH-1:0] src_subnormal; // src is subnormal + logic signed [INT_EXP_WIDTH-1:0] src_offset; // src offset within mantissa + + assign src_bias = signed'(fpnew_pkg::bias(src_fmt_q)); + assign src_exp = fmt_exponent[src_fmt_q]; + assign src_subnormal = signed'({1'b0, info[src_fmt_q].is_subnormal}); + assign src_offset = fmt_shift_compensation[src_fmt_q]; + + logic input_sign; // input sign + logic signed [INT_EXP_WIDTH-1:0] input_exp; // unbiased true exponent + logic [INT_MAN_WIDTH-1:0] input_mant; // normalized input mantissa + logic mant_is_zero; // for integer zeroes + + logic signed [INT_EXP_WIDTH-1:0] fp_input_exp; + logic signed [INT_EXP_WIDTH-1:0] int_input_exp; + + // Input mantissa needs to be normalized + logic [LZC_RESULT_WIDTH-1:0] renorm_shamt; // renormalization shift amount + logic [LZC_RESULT_WIDTH:0] renorm_shamt_sgn; // signed form for calculations + + // Leading-zero counter is needed for renormalization + lzc #( + .WIDTH ( INT_MAN_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( encoded_mant ), + .cnt_o ( renorm_shamt ), + .empty_o ( mant_is_zero ) + ); + assign renorm_shamt_sgn = signed'({1'b0, renorm_shamt}); + + // Get the sign from the proper source + assign input_sign = src_is_int ? int_sign : fmt_sign[src_fmt_q]; + // Realign input mantissa, append zeroes if destination is wider + assign input_mant = encoded_mant << renorm_shamt; + // Unbias exponent and compensate for shift + assign fp_input_exp = signed'(src_exp + src_subnormal - src_bias - + renorm_shamt_sgn + src_offset); // compensate for shift + assign int_input_exp = signed'(INT_MAN_WIDTH - 1 - renorm_shamt_sgn); + + assign input_exp = src_is_int ? int_input_exp : fp_input_exp; + + logic signed [INT_EXP_WIDTH-1:0] destination_exp; // re-biased exponent for destination + + // Rebias the exponent + assign destination_exp = input_exp + signed'(fpnew_pkg::bias(dst_fmt_q)); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic input_sign_q; + logic signed [INT_EXP_WIDTH-1:0] input_exp_q; + logic [INT_MAN_WIDTH-1:0] input_mant_q; + logic signed [INT_EXP_WIDTH-1:0] destination_exp_q; + logic src_is_int_q; + logic dst_is_int_q; + fpnew_pkg::fp_info_t info_q; + logic mant_is_zero_q; + logic op_mod_q2; + fpnew_pkg::roundmode_e rnd_mode_q; + fpnew_pkg::fp_format_e src_fmt_q2; + fpnew_pkg::fp_format_e dst_fmt_q2; + fpnew_pkg::int_format_e int_fmt_q2; + // Internal pipeline signals, index i holds signal after i register stages + + + logic [0:NUM_MID_REGS] mid_pipe_input_sign_q; + logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_input_exp_q; + logic [0:NUM_MID_REGS][INT_MAN_WIDTH-1:0] mid_pipe_input_mant_q; + logic signed [0:NUM_MID_REGS][INT_EXP_WIDTH-1:0] mid_pipe_dest_exp_q; + logic [0:NUM_MID_REGS] mid_pipe_src_is_int_q; + logic [0:NUM_MID_REGS] mid_pipe_dst_is_int_q; + fpnew_pkg::fp_info_t [0:NUM_MID_REGS] mid_pipe_info_q; + logic [0:NUM_MID_REGS] mid_pipe_mant_zero_q; + logic [0:NUM_MID_REGS] mid_pipe_op_mod_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q; + fpnew_pkg::int_format_e [0:NUM_MID_REGS] mid_pipe_int_fmt_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_input_sign_q[0] = input_sign; + assign mid_pipe_input_exp_q[0] = input_exp; + assign mid_pipe_input_mant_q[0] = input_mant; + assign mid_pipe_dest_exp_q[0] = destination_exp; + assign mid_pipe_src_is_int_q[0] = src_is_int; + assign mid_pipe_dst_is_int_q[0] = dst_is_int; + assign mid_pipe_info_q[0] = info[src_fmt_q]; + assign mid_pipe_mant_zero_q[0] = mant_is_zero; + assign mid_pipe_op_mod_q[0] = op_mod_q; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_src_fmt_q[0] = src_fmt_q; + assign mid_pipe_dst_fmt_q[0] = dst_fmt_q; + assign mid_pipe_int_fmt_q[0] = int_fmt_q; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_input_sign_q[i+1], mid_pipe_input_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_input_exp_q[i+1], mid_pipe_input_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_input_mant_q[i+1], mid_pipe_input_mant_q[i], reg_ena, '0) + `FFL(mid_pipe_dest_exp_q[i+1], mid_pipe_dest_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_src_is_int_q[i+1], mid_pipe_src_is_int_q[i], reg_ena, '0) + `FFL(mid_pipe_dst_is_int_q[i+1], mid_pipe_dst_is_int_q[i], reg_ena, '0) + `FFL(mid_pipe_info_q[i+1], mid_pipe_info_q[i], reg_ena, '0) + `FFL(mid_pipe_mant_zero_q[i+1], mid_pipe_mant_zero_q[i], reg_ena, '0) + `FFL(mid_pipe_op_mod_q[i+1], mid_pipe_op_mod_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_src_fmt_q[i+1], mid_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_int_fmt_q[i+1], mid_pipe_int_fmt_q[i], reg_ena, fpnew_pkg::int_format_e'(0)) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign input_sign_q = mid_pipe_input_sign_q[NUM_MID_REGS]; + assign input_exp_q = mid_pipe_input_exp_q[NUM_MID_REGS]; + assign input_mant_q = mid_pipe_input_mant_q[NUM_MID_REGS]; + assign destination_exp_q = mid_pipe_dest_exp_q[NUM_MID_REGS]; + assign src_is_int_q = mid_pipe_src_is_int_q[NUM_MID_REGS]; + assign dst_is_int_q = mid_pipe_dst_is_int_q[NUM_MID_REGS]; + assign info_q = mid_pipe_info_q[NUM_MID_REGS]; + assign mant_is_zero_q = mid_pipe_mant_zero_q[NUM_MID_REGS]; + assign op_mod_q2 = mid_pipe_op_mod_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign src_fmt_q2 = mid_pipe_src_fmt_q[NUM_MID_REGS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS]; + assign int_fmt_q2 = mid_pipe_int_fmt_q[NUM_MID_REGS]; + + // -------- + // Casting + // -------- + logic [INT_EXP_WIDTH-1:0] final_exp; // after eventual adjustments + + logic [2*INT_MAN_WIDTH:0] preshift_mant; // mantissa before final shift + logic [2*INT_MAN_WIDTH:0] destination_mant; // mantissa from shifter, with rnd bit + logic [SUPER_MAN_BITS-1:0] final_mant; // mantissa after adjustments + logic [MAX_INT_WIDTH-1:0] final_int; // integer shifted in position + + logic [$clog2(INT_MAN_WIDTH+1)-1:0] denorm_shamt; // shift amount for denormalization + + logic [1:0] fp_round_sticky_bits, int_round_sticky_bits, round_sticky_bits; + logic of_before_round, uf_before_round; + + + // Perform adjustments to mantissa and exponent + always_comb begin : cast_value + // Default assignment + final_exp = unsigned'(destination_exp_q); // take exponent as is, only look at lower bits + preshift_mant = '0; // initialize mantissa container with zeroes + denorm_shamt = SUPER_MAN_BITS - fpnew_pkg::man_bits(dst_fmt_q2); // right of mantissa + of_before_round = 1'b0; + uf_before_round = 1'b0; + + // Place mantissa to the left of the shifter + preshift_mant = input_mant_q << (INT_MAN_WIDTH + 1); + + // Handle INT casts + if (dst_is_int_q) begin + // By default right shift mantissa to be an integer + denorm_shamt = unsigned'(MAX_INT_WIDTH - 1 - input_exp_q); + // overflow: when converting to unsigned the range is larger by one + if ((input_exp_q >= signed'(fpnew_pkg::int_width(int_fmt_q2) - 1 + op_mod_q2)) // Exponent larger than max int range, + && !(!op_mod_q2 // unless cast to signed int + && input_sign_q // and input value is larges negative int value + && (input_exp_q == signed'(fpnew_pkg::int_width(int_fmt_q2) - 1)) + && (input_mant_q == {1'b1, {INT_MAN_WIDTH-1{1'b0}}}))) begin + denorm_shamt = '0; // prevent shifting + of_before_round = 1'b1; + // underflow + end else if (input_exp_q < -1) begin + denorm_shamt = MAX_INT_WIDTH + 1; // all bits go to the sticky + uf_before_round = 1'b1; + end + // Handle FP over-/underflows + end else begin + // Overflow or infinities (for proper rounding) + if ((destination_exp_q >= signed'(2**fpnew_pkg::exp_bits(dst_fmt_q2))-1) || + (~src_is_int_q && info_q.is_inf)) begin + final_exp = unsigned'(2**fpnew_pkg::exp_bits(dst_fmt_q2)-2); // largest normal value + preshift_mant = '1; // largest normal value and RS bits set + of_before_round = 1'b1; + // Denormalize underflowing values + end else if (destination_exp_q < 1 && + destination_exp_q >= -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin + final_exp = '0; // denormal result + denorm_shamt = unsigned'(denorm_shamt + 1 - destination_exp_q); // adjust right shifting + uf_before_round = 1'b1; + // Limit the shift to retain sticky bits + end else if (destination_exp_q < -signed'(fpnew_pkg::man_bits(dst_fmt_q2))) begin + final_exp = '0; // denormal result + denorm_shamt = unsigned'(denorm_shamt + 2 + fpnew_pkg::man_bits(dst_fmt_q2)); // to sticky + uf_before_round = 1'b1; + end + end + end + + localparam NUM_FP_STICKY = 2 * INT_MAN_WIDTH - SUPER_MAN_BITS - 1; // removed mantissa, 1. and R + localparam NUM_INT_STICKY = 2 * INT_MAN_WIDTH - MAX_INT_WIDTH; // removed int and R + + // Mantissa adjustment shift + assign destination_mant = preshift_mant >> denorm_shamt; + // Extract final mantissa and round bit, discard the normal bit (for FP) + assign {final_mant, fp_round_sticky_bits[1]} = + destination_mant[2*INT_MAN_WIDTH-1-:SUPER_MAN_BITS+1]; + assign {final_int, int_round_sticky_bits[1]} = destination_mant[2*INT_MAN_WIDTH-:MAX_INT_WIDTH+1]; + // Collapse sticky bits + assign fp_round_sticky_bits[0] = (| {destination_mant[NUM_FP_STICKY-1:0]}); + assign int_round_sticky_bits[0] = (| {destination_mant[NUM_INT_STICKY-1:0]}); + + // select RS bits for destination operation + assign round_sticky_bits = dst_is_int_q ? int_round_sticky_bits : fp_round_sticky_bits; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic [WIDTH-1:0] pre_round_abs; // absolute value of result before rnd + logic of_after_round; // overflow + logic uf_after_round; // underflow + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_pre_round_abs; // per format + logic [NUM_FORMATS-1:0] fmt_of_after_round; + logic [NUM_FORMATS-1:0] fmt_uf_after_round; + + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_pre_round_abs; // per format + logic [NUM_INT_FORMATS-1:0] ifmt_of_after_round; + + logic rounded_sign; + logic [WIDTH-1:0] rounded_abs; // absolute value of result after rounding + logic result_true_zero; + + logic [WIDTH-1:0] rounded_int_res; // after possible inversion + logic rounded_int_res_zero; // after rounding + + + // Pack exponent and mantissa into proper rounding form + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble + // Set up some constants + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : assemble_result + fmt_pre_round_abs[fmt] = {final_exp[EXP_BITS-1:0], final_mant[MAN_BITS-1:0]}; // 0-extend + end + end else begin : inactive_format + assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Sign-extend integer result + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_res_sign_ext + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : assemble_result + // sign-extend reusult + ifmt_pre_round_abs[ifmt] = '{default: final_int[INT_WIDTH-1]}; + ifmt_pre_round_abs[ifmt][INT_WIDTH-1:0] = final_int[INT_WIDTH-1:0]; + end + end else begin : inactive_format + assign ifmt_pre_round_abs[ifmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Select output with destination format and operation + assign pre_round_abs = dst_is_int_q ? ifmt_pre_round_abs[int_fmt_q2] : fmt_pre_round_abs[dst_fmt_q2]; + + fpnew_rounding #( + .AbsWidth ( WIDTH ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( input_sign_q ), // source format + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( 1'b0 ), // no operation happened + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_true_zero ) + ); + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result; + + // Detect overflows and inject sign + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : post_process + // detect of / uf + fmt_uf_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0; // denormal + fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. + + // Assemble regular result, nan box short ones. Int zeroes need to be detected` + fmt_result[fmt] = '1; + fmt_result[fmt][FP_WIDTH-1:0] = src_is_int_q & mant_is_zero_q + ? '0 + : {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]}; + end + end else begin : inactive_format + assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Negative integer result needs to be brought into two's complement + assign rounded_int_res = rounded_sign ? unsigned'(-rounded_abs) : rounded_abs; + assign rounded_int_res_zero = (rounded_int_res == '0); + + // Detect integer overflows after rounding (only positives) + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_int_overflow + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : detect_overflow + ifmt_of_after_round[ifmt] = 1'b0; + // Int result can overflow if we're at the max exponent + if (!rounded_sign && input_exp_q == signed'(INT_WIDTH - 2 + op_mod_q2)) begin + // Check whether the rounded MSB differs from unrounded MSB + ifmt_of_after_round[ifmt] = ~rounded_int_res[INT_WIDTH-2+op_mod_q2]; + end + end + end else begin : inactive_format + assign ifmt_of_after_round[ifmt] = fpnew_pkg::DONT_CARE; + end + end + + // Classification after rounding select by destination format + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = dst_is_int_q ? ifmt_of_after_round[int_fmt_q2] : fmt_of_after_round[dst_fmt_q2]; + + // ------------------------- + // FP Special case handling + // ------------------------- + logic [WIDTH-1:0] fp_special_result; + fpnew_pkg::status_t fp_special_status; + logic fp_result_is_special; + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result; + + // Special result construction + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : special_results + logic [FP_WIDTH-1:0] special_res; + special_res = info_q.is_zero + ? input_sign_q << FP_WIDTH-1 // signed zero + : {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + + // Initialize special result with ones (NaN-box) + fmt_special_result[fmt] = '1; + fmt_special_result[fmt][FP_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Detect special case from source format, I2F casts don't produce a special result + assign fp_result_is_special = ~src_is_int_q & (info_q.is_zero | + info_q.is_nan | + ~info_q.is_boxed); + + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign fp_special_status = '{NV: info_q.is_signalling, default: 1'b0}; + + // Assemble result according to destination format + assign fp_special_result = fmt_special_result[dst_fmt_q2]; // destination format + + // -------------------------- + // INT Special case handling + // -------------------------- + logic [WIDTH-1:0] int_special_result; + fpnew_pkg::status_t int_special_status; + logic int_result_is_special; + + logic [NUM_INT_FORMATS-1:0][WIDTH-1:0] ifmt_special_result; + + // Special result construction + for (genvar ifmt = 0; ifmt < int'(NUM_INT_FORMATS); ifmt++) begin : gen_special_results_int + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + + if (IntFmtConfig[ifmt]) begin : active_format + always_comb begin : special_results + automatic logic [INT_WIDTH-1:0] special_res; + + // Default is overflow to positive max, which is 2**INT_WIDTH-1 or 2**(INT_WIDTH-1)-1 + special_res[INT_WIDTH-2:0] = '1; // alone yields 2**(INT_WIDTH-1)-1 + special_res[INT_WIDTH-1] = op_mod_q2; // for unsigned casts yields 2**INT_WIDTH-1 + + // Negative special case (except for nans) tie to -max or 0 + if (input_sign_q && !info_q.is_nan) + special_res = ~special_res; + + // Initialize special result with sign-extension + ifmt_special_result[ifmt] = '{default: special_res[INT_WIDTH-1]}; + ifmt_special_result[ifmt][INT_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign ifmt_special_result[ifmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Detect special case from source format (inf, nan, overflow, nan-boxing or negative unsigned) + assign int_result_is_special = info_q.is_nan | info_q.is_inf | + of_before_round | of_after_round | ~info_q.is_boxed | + (input_sign_q & op_mod_q2 & ~rounded_int_res_zero); + + // All integer special cases are invalid + assign int_special_status = '{NV: 1'b1, default: 1'b0}; + + // Assemble result according to destination format + assign int_special_result = ifmt_special_result[int_fmt_q2]; // destination format + + // ----------------- + // Result selection + // ----------------- + fpnew_pkg::status_t int_regular_status, fp_regular_status; + + logic [WIDTH-1:0] fp_result, int_result; + fpnew_pkg::status_t fp_status, int_status; + + assign fp_regular_status.NV = src_is_int_q & (of_before_round | of_after_round); // overflow is invalid for I2F casts + assign fp_regular_status.DZ = 1'b0; // no divisions + assign fp_regular_status.OF = ~src_is_int_q & (~info_q.is_inf & (of_before_round | of_after_round)); // inf casts no OF + assign fp_regular_status.UF = uf_after_round & fp_regular_status.NX; + assign fp_regular_status.NX = src_is_int_q ? (| fp_round_sticky_bits) // overflow is invalid in i2f + : (| fp_round_sticky_bits) | (~info_q.is_inf & (of_before_round | of_after_round)); + assign int_regular_status = '{NX: (| int_round_sticky_bits), default: 1'b0}; + + assign fp_result = fp_result_is_special ? fp_special_result : fmt_result[dst_fmt_q2]; + assign fp_status = fp_result_is_special ? fp_special_status : fp_regular_status; + assign int_result = int_result_is_special ? int_special_result : rounded_int_res; + assign int_status = int_result_is_special ? int_special_status : int_regular_status; + + // Final results for output pipeline + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + logic extension_bit; + + // Select output depending on special case detection + assign result_d = dst_is_int_q ? int_result : fp_result; + assign status_d = dst_is_int_q ? int_status : fp_status; + + // MSB of int result decides extension, otherwise NaN box + assign extension_bit = dst_is_int_q ? int_result[WIDTH-1] : 1'b1; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + logic [0:NUM_OUT_REGS] out_pipe_ext_bit_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_ext_bit_q[0] = extension_bit; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + NUM_MID_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_ext_bit_q[i+1], out_pipe_ext_bit_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = out_pipe_ext_bit_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule +// ----- 8< ----- FILE "./fpnew_classifier.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_classifier #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumOperands = 1, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat) +) ( + input logic [NumOperands-1:0][WIDTH-1:0] operands_i, + input logic [NumOperands-1:0] is_boxed_i, + output fpnew_pkg::fp_info_t [NumOperands-1:0] info_o +); + + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + + // Type definition + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // Iterate through all operands + for (genvar op = 0; op < int'(NumOperands); op++) begin : gen_num_values + + fp_t value; + logic is_boxed; + logic is_normal; + logic is_inf; + logic is_nan; + logic is_signalling; + logic is_quiet; + logic is_zero; + logic is_subnormal; + + // --------------- + // Classify Input + // --------------- + always_comb begin : classify_input + value = operands_i[op]; + is_boxed = is_boxed_i[op]; + is_normal = is_boxed && (value.exponent != '0) && (value.exponent != '1); + is_zero = is_boxed && (value.exponent == '0) && (value.mantissa == '0); + is_subnormal = is_boxed && (value.exponent == '0) && !is_zero; + is_inf = is_boxed && ((value.exponent == '1) && (value.mantissa == '0)); + is_nan = !is_boxed || ((value.exponent == '1) && (value.mantissa != '0)); + is_signalling = is_boxed && is_nan && (value.mantissa[MAN_BITS-1] == 1'b0); + is_quiet = is_nan && !is_signalling; + // Assign output for current input + info_o[op].is_normal = is_normal; + info_o[op].is_subnormal = is_subnormal; + info_o[op].is_zero = is_zero; + info_o[op].is_inf = is_inf; + info_o[op].is_nan = is_nan; + info_o[op].is_signalling = is_signalling; + info_o[op].is_quiet = is_quiet; + info_o[op].is_boxed = is_boxed; + end + end +endmodule +// ----- 8< ----- FILE "./gated_clk_cell.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module gated_clk_cell( + clk_in, + global_en, + module_en, + local_en, + external_en, + pad_yy_icg_scan_en, + clk_out +); + +input clk_in; +input global_en; +input module_en; +input local_en; +input external_en; +input pad_yy_icg_scan_en; +output clk_out; + +wire clk_en_bf_latch; +wire SE; + +assign clk_en_bf_latch = (global_en && (module_en || local_en)) || external_en ; + +// SE driven from primary input, held constant +assign SE = pad_yy_icg_scan_en; + +// // &Connect( .clk_in (clk_in), @50 +// // .SE (SE), @51 +// // .external_en (clk_en_bf_latch), @52 +// // .clk_out (clk_out) @53 +// // ) ; @54 + +assign clk_out = clk_in; + +endmodule +// ----- 8< ----- FILE "./pa_fdsu_ctrl.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_ctrl( + cp0_fpu_icg_en, + cp0_yy_clk_en, + cpurst_b, + ctrl_fdsu_ex1_sel, + ctrl_xx_ex1_cmplt_dp, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + ctrl_xx_ex2_warm_up, + ctrl_xx_ex3_warm_up, + ex1_div, + ex1_expnt_adder_op0, + ex1_of_result_lfn, + ex1_op0_id, + ex1_op0_norm, + ex1_op1_id_vld, + ex1_op1_norm, + ex1_op1_sel, + ex1_oper_id_expnt, + ex1_oper_id_expnt_f, + ex1_pipedown, + ex1_pipedown_gate, + ex1_result_sign, + ex1_rm, + ex1_save_op0, + ex1_save_op0_gate, + ex1_sqrt, + ex1_srt_skip, + ex2_expnt_adder_op0, + ex2_of, + ex2_pipe_clk, + ex2_pipedown, + ex2_potnt_of, + ex2_potnt_uf, + ex2_result_inf, + ex2_result_lfn, + ex2_rslt_denorm, + ex2_srt_expnt_rst, + ex2_srt_first_round, + ex2_uf, + ex2_uf_srt_skip, + ex3_expnt_adjust_result, + ex3_pipedown, + ex3_rslt_denorm, + fdsu_ex1_sel, + fdsu_fpu_debug_info, + fdsu_fpu_ex1_cmplt, + fdsu_fpu_ex1_cmplt_dp, + fdsu_fpu_ex1_stall, + fdsu_fpu_no_op, + fdsu_frbus_wb_vld, + fdsu_yy_div, + fdsu_yy_expnt_rst, + fdsu_yy_of, + fdsu_yy_of_rm_lfn, + fdsu_yy_op0_norm, + fdsu_yy_op1_norm, + fdsu_yy_potnt_of, + fdsu_yy_potnt_uf, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rm, + fdsu_yy_rslt_denorm, + fdsu_yy_sqrt, + fdsu_yy_uf, + fdsu_yy_wb_freg, + forever_cpuclk, + frbus_fdsu_wb_grant, + idu_fpu_ex1_dst_freg, + idu_fpu_ex1_eu_sel, + pad_yy_icg_scan_en, + rtu_xx_ex1_cancel, + rtu_xx_ex2_cancel, + rtu_yy_xx_async_flush, + rtu_yy_xx_flush, + srt_remainder_zero, + srt_sm_on +); + +// &Ports; @24 +input cp0_fpu_icg_en; +input cp0_yy_clk_en; +input cpurst_b; +input ctrl_fdsu_ex1_sel; +input ctrl_xx_ex1_cmplt_dp; +input ctrl_xx_ex1_inst_vld; +input ctrl_xx_ex1_stall; +input ctrl_xx_ex1_warm_up; +input ctrl_xx_ex2_warm_up; +input ctrl_xx_ex3_warm_up; +input ex1_div; +input [12:0] ex1_expnt_adder_op0; +input ex1_of_result_lfn; +input ex1_op0_id; +input ex1_op0_norm; +input ex1_op1_id_vld; +input ex1_op1_norm; +input [12:0] ex1_oper_id_expnt; +input ex1_result_sign; +input [2 :0] ex1_rm; +input ex1_sqrt; +input ex1_srt_skip; +input ex2_of; +input ex2_potnt_of; +input ex2_potnt_uf; +input ex2_result_inf; +input ex2_result_lfn; +input ex2_rslt_denorm; +input [9 :0] ex2_srt_expnt_rst; +input ex2_uf; +input ex2_uf_srt_skip; +input [9 :0] ex3_expnt_adjust_result; +input ex3_rslt_denorm; +input forever_cpuclk; +input frbus_fdsu_wb_grant; +input [4 :0] idu_fpu_ex1_dst_freg; +input [2 :0] idu_fpu_ex1_eu_sel; +input pad_yy_icg_scan_en; +input rtu_xx_ex1_cancel; +input rtu_xx_ex2_cancel; +input rtu_yy_xx_async_flush; +input rtu_yy_xx_flush; +input srt_remainder_zero; +output ex1_op1_sel; +output [12:0] ex1_oper_id_expnt_f; +output ex1_pipedown; +output ex1_pipedown_gate; +output ex1_save_op0; +output ex1_save_op0_gate; +output [9 :0] ex2_expnt_adder_op0; +output ex2_pipe_clk; +output ex2_pipedown; +output ex2_srt_first_round; +output ex3_pipedown; +output fdsu_ex1_sel; +output [4 :0] fdsu_fpu_debug_info; +output fdsu_fpu_ex1_cmplt; +output fdsu_fpu_ex1_cmplt_dp; +output fdsu_fpu_ex1_stall; +output fdsu_fpu_no_op; +output fdsu_frbus_wb_vld; +output fdsu_yy_div; +output [9 :0] fdsu_yy_expnt_rst; +output fdsu_yy_of; +output fdsu_yy_of_rm_lfn; +output fdsu_yy_op0_norm; +output fdsu_yy_op1_norm; +output fdsu_yy_potnt_of; +output fdsu_yy_potnt_uf; +output fdsu_yy_result_inf; +output fdsu_yy_result_lfn; +output fdsu_yy_result_sign; +output [2 :0] fdsu_yy_rm; +output fdsu_yy_rslt_denorm; +output fdsu_yy_sqrt; +output fdsu_yy_uf; +output [4 :0] fdsu_yy_wb_freg; +output srt_sm_on; + +// &Regs; @25 +reg ex2_srt_first_round; +reg [2 :0] fdsu_cur_state; +reg fdsu_div; +reg [9 :0] fdsu_expnt_rst; +reg [2 :0] fdsu_next_state; +reg fdsu_of; +reg fdsu_of_rm_lfn; +reg fdsu_potnt_of; +reg fdsu_potnt_uf; +reg fdsu_result_inf; +reg fdsu_result_lfn; +reg fdsu_result_sign; +reg [2 :0] fdsu_rm; +reg fdsu_sqrt; +reg fdsu_uf; +reg [4 :0] fdsu_wb_freg; +reg fdsu_yy_rslt_denorm; +reg [4 :0] srt_cnt; +reg [1 :0] wb_cur_state; +reg [1 :0] wb_nxt_state; + +// &Wires; @26 +wire cp0_fpu_icg_en; +wire cp0_yy_clk_en; +wire cpurst_b; +wire ctrl_fdsu_ex1_sel; +wire ctrl_fdsu_ex1_stall; +wire ctrl_fdsu_wb_vld; +wire ctrl_iter_start; +wire ctrl_iter_start_gate; +wire ctrl_pack; +wire ctrl_result_vld; +wire ctrl_round; +wire ctrl_sm_cmplt; +wire ctrl_sm_ex1; +wire ctrl_sm_idle; +wire ctrl_sm_start; +wire ctrl_sm_start_gate; +wire ctrl_srt_idle; +wire ctrl_srt_itering; +wire ctrl_wb_idle; +wire ctrl_wb_sm_cmplt; +wire ctrl_wb_sm_ex2; +wire ctrl_wb_sm_idle; +wire ctrl_wfi2; +wire ctrl_wfwb; +wire ctrl_xx_ex1_cmplt_dp; +wire ctrl_xx_ex1_inst_vld; +wire ctrl_xx_ex1_stall; +wire ctrl_xx_ex1_warm_up; +wire ctrl_xx_ex2_warm_up; +wire ctrl_xx_ex3_warm_up; +wire ex1_div; +wire [12:0] ex1_expnt_adder_op0; +wire ex1_of_result_lfn; +wire ex1_op0_id; +wire ex1_op1_id_vld; +wire ex1_op1_sel; +wire [12:0] ex1_oper_id_expnt; +wire [12:0] ex1_oper_id_expnt_f; +wire ex1_pipe_clk; +wire ex1_pipe_clk_en; +wire ex1_pipedown; +wire ex1_pipedown_gate; +wire ex1_result_sign; +wire [2 :0] ex1_rm; +wire ex1_save_op0; +wire ex1_save_op0_gate; +wire ex1_sqrt; +wire ex1_srt_skip; +wire [4 :0] ex1_wb_freg; +wire [9 :0] ex2_expnt_adder_op0; +wire ex2_of; +wire ex2_pipe_clk; +wire ex2_pipe_clk_en; +wire ex2_pipedown; +wire ex2_potnt_of; +wire ex2_potnt_uf; +wire ex2_result_inf; +wire ex2_result_lfn; +wire ex2_rslt_denorm; +wire [9 :0] ex2_srt_expnt_rst; +wire ex2_uf; +wire ex2_uf_srt_skip; +wire [9 :0] ex3_expnt_adjust_result; +wire ex3_pipedown; +wire ex3_rslt_denorm; +wire expnt_rst_clk; +wire expnt_rst_clk_en; +wire fdsu_busy; +wire fdsu_clk; +wire fdsu_clk_en; +wire fdsu_dn_stall; +wire fdsu_ex1_inst_vld; +wire fdsu_ex1_res_vld; +wire fdsu_ex1_sel; +wire fdsu_flush; +wire [4 :0] fdsu_fpu_debug_info; +wire fdsu_fpu_ex1_cmplt; +wire fdsu_fpu_ex1_cmplt_dp; +wire fdsu_fpu_ex1_stall; +wire fdsu_fpu_no_op; +wire fdsu_frbus_wb_vld; +wire fdsu_op0_norm; +wire fdsu_op1_norm; +wire fdsu_wb_grant; +wire fdsu_yy_div; +wire [9 :0] fdsu_yy_expnt_rst; +wire fdsu_yy_of; +wire fdsu_yy_of_rm_lfn; +wire fdsu_yy_op0_norm; +wire fdsu_yy_op1_norm; +wire fdsu_yy_potnt_of; +wire fdsu_yy_potnt_uf; +wire fdsu_yy_result_inf; +wire fdsu_yy_result_lfn; +wire fdsu_yy_result_sign; +wire [2 :0] fdsu_yy_rm; +wire fdsu_yy_sqrt; +wire fdsu_yy_uf; +wire [4 :0] fdsu_yy_wb_freg; +wire forever_cpuclk; +wire frbus_fdsu_wb_grant; +wire [4 :0] idu_fpu_ex1_dst_freg; +wire [2 :0] idu_fpu_ex1_eu_sel; +wire pad_yy_icg_scan_en; +wire rtu_xx_ex1_cancel; +wire rtu_xx_ex2_cancel; +wire rtu_yy_xx_async_flush; +wire rtu_yy_xx_flush; +wire [4 :0] srt_cnt_ini; +wire srt_cnt_zero; +wire srt_last_round; +wire srt_remainder_zero; +wire srt_skip; +wire srt_sm_on; + + +//========================================================== +// Input Signal +//========================================================== +assign ex1_wb_freg[4:0] = idu_fpu_ex1_dst_freg[4:0]; +assign fdsu_ex1_inst_vld = ctrl_xx_ex1_inst_vld && ctrl_fdsu_ex1_sel; +assign fdsu_ex1_sel = idu_fpu_ex1_eu_sel[2]; +// &Force("input", "idu_fpu_ex1_eu_sel"); &Force("bus", "idu_fpu_ex1_eu_sel", 2, 0); @34 + +//========================================================== +// FDSU Main State Machine +//========================================================== +assign fdsu_ex1_res_vld = fdsu_ex1_inst_vld && ex1_srt_skip; +assign fdsu_wb_grant = frbus_fdsu_wb_grant; + +assign ctrl_iter_start = ctrl_sm_start && !fdsu_dn_stall + || ctrl_wfi2; +assign ctrl_iter_start_gate = ctrl_sm_start_gate && !fdsu_dn_stall + || ctrl_wfi2; +assign ctrl_sm_start = fdsu_ex1_inst_vld && ctrl_srt_idle + && !ex1_srt_skip; +assign ctrl_sm_start_gate = fdsu_ex1_inst_vld && ctrl_srt_idle; + +assign srt_last_round = (srt_skip || + srt_remainder_zero || + srt_cnt_zero) && + ctrl_srt_itering; +assign srt_skip = ex2_of || + ex2_uf_srt_skip; +assign srt_cnt_zero = ~|srt_cnt[4:0]; +assign fdsu_dn_stall = ctrl_sm_start && ex1_op1_id_vld; + +parameter IDLE = 3'b000; +parameter WFI2 = 3'b001; +parameter ITER = 3'b010; +parameter RND = 3'b011; +parameter PACK = 3'b100; +parameter WFWB = 3'b101; + +always @ (posedge fdsu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + fdsu_cur_state[2:0] <= IDLE; + else if (fdsu_flush) + fdsu_cur_state[2:0] <= IDLE; + else + fdsu_cur_state[2:0] <= fdsu_next_state[2:0]; +end + +// &CombBeg; @76 +always @( ctrl_sm_start + or fdsu_dn_stall + or srt_last_round + or fdsu_cur_state[2:0] + or fdsu_wb_grant) +begin +case (fdsu_cur_state[2:0]) + IDLE: + begin + if (ctrl_sm_start) + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + else + fdsu_next_state[2:0] = IDLE; + end + WFI2: + fdsu_next_state[2:0] = ITER; + ITER: + begin + if (srt_last_round) + fdsu_next_state[2:0] = RND; + else + fdsu_next_state[2:0] = ITER; + end + RND: + fdsu_next_state[2:0] = PACK; + PACK: + begin + if (fdsu_wb_grant) + if (ctrl_sm_start) + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + else + fdsu_next_state[2:0] = IDLE; + else + fdsu_next_state[2:0] = WFWB; + end + WFWB: + begin + if (fdsu_wb_grant) + if (ctrl_sm_start) + if (fdsu_dn_stall) + fdsu_next_state[2:0] = WFI2; + else + fdsu_next_state[2:0] = ITER; + else + fdsu_next_state[2:0] = IDLE; + else + fdsu_next_state[2:0] = WFWB; + end + default: + fdsu_next_state[2:0] = IDLE; +endcase +// &CombEnd; @128 +end + +assign ctrl_sm_idle = fdsu_cur_state[2:0] == IDLE; +assign ctrl_wfi2 = fdsu_cur_state[2:0] == WFI2; +assign ctrl_srt_itering = fdsu_cur_state[2:0] == ITER; +assign ctrl_round = fdsu_cur_state[2:0] == RND; +assign ctrl_pack = fdsu_cur_state[2:0] == PACK; +assign ctrl_wfwb = fdsu_cur_state[2:0] == WFWB; + +assign ctrl_sm_cmplt = ctrl_pack || ctrl_wfwb; +assign ctrl_srt_idle = ctrl_sm_idle + || fdsu_wb_grant; +assign ctrl_sm_ex1 = ctrl_srt_idle || ctrl_wfi2; + +//========================================================== +// Iteration Counter +//========================================================== +always @ (posedge fdsu_clk) +begin + if (fdsu_flush) + srt_cnt[4:0] <= 5'b0; + else if (ctrl_iter_start) + srt_cnt[4:0] <= srt_cnt_ini[4:0]; + else if (ctrl_srt_itering) + srt_cnt[4:0] <= srt_cnt[4:0] - 5'b1; + else + srt_cnt[4:0] <= srt_cnt[4:0]; +end + +//srt_cnt_ini[4:0] +//For Double, initial is 5'b11100('d28), calculate 29 round +//For Single, initial is 5'b01110('d14), calculate 15 round +assign srt_cnt_ini[4:0] = 5'b01110; + +//fdsu srt first round signal +//For srt calculate special use +always @(posedge fdsu_clk or negedge cpurst_b) +begin + if(!cpurst_b) + ex2_srt_first_round <= 1'b0; + else if(fdsu_flush) + ex2_srt_first_round <= 1'b0; + else if(ex1_pipedown) + ex2_srt_first_round <= 1'b1; + else + ex2_srt_first_round <= 1'b0; +end + +//========================================================== +// Write Back State Machine +//========================================================== +parameter WB_IDLE = 2'b00, + WB_EX2 = 2'b10, + WB_CMPLT = 2'b01; + +always @ (posedge fdsu_clk or negedge cpurst_b) +begin + if (!cpurst_b) + wb_cur_state[1:0] <= WB_IDLE; + else if (fdsu_flush) + wb_cur_state[1:0] <= WB_IDLE; + else + wb_cur_state[1:0] <= wb_nxt_state[1:0]; +end + +// &CombBeg; @215 +always @( ctrl_fdsu_wb_vld + or fdsu_dn_stall + or ctrl_xx_ex1_stall + or fdsu_ex1_inst_vld + or ctrl_iter_start + or fdsu_ex1_res_vld + or wb_cur_state[1:0]) +begin + case(wb_cur_state[1:0]) + WB_IDLE: + if (fdsu_ex1_inst_vld) + if (ctrl_xx_ex1_stall || fdsu_ex1_res_vld || fdsu_dn_stall) + wb_nxt_state[1:0] = WB_IDLE; + else + wb_nxt_state[1:0] = WB_EX2; + else + wb_nxt_state[1:0] = WB_IDLE; + WB_EX2: + // if (ctrl_xx_ex2_stall) + // wb_nxt_state[1:0] = WB_EX2; + // else + if (ctrl_fdsu_wb_vld) + if (ctrl_iter_start && !ctrl_xx_ex1_stall) + wb_nxt_state[1:0] = WB_EX2; + else + wb_nxt_state[1:0] = WB_IDLE; + else + wb_nxt_state[1:0] = WB_CMPLT; + WB_CMPLT: + if (ctrl_fdsu_wb_vld) + if (ctrl_iter_start && !ctrl_xx_ex1_stall) + wb_nxt_state[1:0] = WB_EX2; + else + wb_nxt_state[1:0] = WB_IDLE; + else + wb_nxt_state[1:0] = WB_CMPLT; + default: + wb_nxt_state[1:0] = WB_IDLE; + endcase +// &CombEnd; @247 +end + +assign ctrl_wb_idle = wb_cur_state[1:0] == WB_IDLE + || wb_cur_state[1:0] == WB_CMPLT && ctrl_fdsu_wb_vld; +assign ctrl_wb_sm_idle = wb_cur_state[1:0] == WB_IDLE; +assign ctrl_wb_sm_ex2 = wb_cur_state[1:0] == WB_EX2; +assign ctrl_wb_sm_cmplt = wb_cur_state[1:0] == WB_EX2 + || wb_cur_state[1:0] == WB_CMPLT; + +assign ctrl_result_vld = ctrl_sm_cmplt && ctrl_wb_sm_cmplt; +assign ctrl_fdsu_wb_vld = ctrl_result_vld && frbus_fdsu_wb_grant; + +assign ctrl_fdsu_ex1_stall = fdsu_ex1_inst_vld && !ctrl_sm_ex1 && !ctrl_wb_idle + || fdsu_ex1_inst_vld && fdsu_dn_stall; + +//========================================================== +// Flops +//========================================================== +always @(posedge ex1_pipe_clk) +begin + if(ex1_pipedown) + begin + fdsu_wb_freg[4:0] <= ex1_wb_freg[4:0]; + fdsu_result_sign <= ex1_result_sign; + fdsu_of_rm_lfn <= ex1_of_result_lfn; + fdsu_div <= ex1_div; + fdsu_sqrt <= ex1_sqrt; + fdsu_rm[2:0] <= ex1_rm[2:0]; + end + else + begin + fdsu_wb_freg[4:0] <= fdsu_wb_freg[4:0]; + fdsu_result_sign <= fdsu_result_sign; + fdsu_of_rm_lfn <= fdsu_of_rm_lfn; + fdsu_div <= fdsu_div; + fdsu_sqrt <= fdsu_sqrt; + fdsu_rm[2:0] <= fdsu_rm[2:0]; + end +end + +// In 906 FDSU, if one op0/1 is not norm, it will not enter EX2. +assign fdsu_op0_norm = 1'b1; +assign fdsu_op1_norm = 1'b1; +// &Force("input", "ex1_op0_norm"); @337 +// &Force("input", "ex1_op1_norm"); @338 + +// fdsu_expnt_rst is used to save: +// 1. op0 denormal expnt; +// 2. op0 expnt; +// 3. result expnt. +// &Force("bus", "ex1_oper_id_expnt", 12, 0); @378 +// &Force("bus", "ex1_expnt_adder_op0", 12, 0); @379 + + +always @ (posedge expnt_rst_clk) +begin + if (ex1_save_op0) + fdsu_expnt_rst[9:0] <= ex1_oper_id_expnt[9:0]; + else if (ex1_pipedown) + fdsu_expnt_rst[9:0] <= ex1_expnt_adder_op0[9:0]; + else if (ex2_pipedown) + fdsu_expnt_rst[9:0] <= ex2_srt_expnt_rst[9:0]; + else if (ex3_pipedown) + fdsu_expnt_rst[9:0] <= ex3_expnt_adjust_result[9:0]; + else + fdsu_expnt_rst[9:0] <= fdsu_expnt_rst[9:0]; +end + +assign ex1_oper_id_expnt_f[12:0] = {3'b1, fdsu_expnt_rst[9:0]}; + +always @ (posedge expnt_rst_clk) +begin + if (ex2_pipedown) + fdsu_yy_rslt_denorm <= ex2_rslt_denorm; + else if (ex3_pipedown) + fdsu_yy_rslt_denorm <= ex3_rslt_denorm; + else + fdsu_yy_rslt_denorm <= fdsu_yy_rslt_denorm; +end +// &Force("output", "fdsu_yy_rslt_denorm"); @440 + +// EX2 signal used in EX3 & EX4 +always @ (posedge ex2_pipe_clk) +begin + if (ex2_pipedown) + begin + fdsu_result_inf <= ex2_result_inf; + fdsu_result_lfn <= ex2_result_lfn; + fdsu_of <= ex2_of; + fdsu_uf <= ex2_uf; + fdsu_potnt_of <= ex2_potnt_of; + fdsu_potnt_uf <= ex2_potnt_uf; + end + else + begin + fdsu_result_inf <= fdsu_result_inf; + fdsu_result_lfn <= fdsu_result_lfn; + fdsu_of <= fdsu_of; + fdsu_uf <= fdsu_uf; + fdsu_potnt_of <= fdsu_potnt_of; + fdsu_potnt_uf <= fdsu_potnt_uf; + end +end + +//========================================================== +// Flush +//========================================================== +assign fdsu_flush = rtu_xx_ex1_cancel && ctrl_wb_idle + || rtu_xx_ex2_cancel && ctrl_wb_sm_ex2 + || ctrl_xx_ex1_warm_up + || rtu_yy_xx_async_flush; + +//========================================================== +// ICG +//========================================================== +assign fdsu_busy = fdsu_ex1_inst_vld + || !ctrl_sm_idle + || !ctrl_wb_sm_idle; +assign fdsu_clk_en = fdsu_busy + || !ctrl_sm_idle + || rtu_yy_xx_flush; +// &Instance("gated_clk_cell", "x_fdsu_clk"); @514 +gated_clk_cell x_fdsu_clk ( + .clk_in (forever_cpuclk ), + .clk_out (fdsu_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (fdsu_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @515 +// .external_en (1'b0), @516 +// .global_en (cp0_yy_clk_en), @517 +// .module_en (cp0_fpu_icg_en), @518 +// .local_en (fdsu_clk_en), @519 +// .clk_out (fdsu_clk)); @520 + +assign ex1_pipe_clk_en = ex1_pipedown_gate; +// &Instance("gated_clk_cell","x_ex1_pipe_clk"); @523 +gated_clk_cell x_ex1_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex1_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex1_pipe_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @524 +// .clk_out (ex1_pipe_clk),//Out Clock @525 +// .external_en (1'b0), @526 +// .global_en (cp0_yy_clk_en), @527 +// .local_en (ex1_pipe_clk_en),//Local Condition @528 +// .module_en (cp0_fpu_icg_en) @529 +// ); @530 + +assign ex2_pipe_clk_en = ex2_pipedown; +// &Instance("gated_clk_cell","x_ex2_pipe_clk"); @533 +gated_clk_cell x_ex2_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex2_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex2_pipe_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @534 +// .clk_out (ex2_pipe_clk),//Out Clock @535 +// .external_en (1'b0), @536 +// .global_en (cp0_yy_clk_en), @537 +// .local_en (ex2_pipe_clk_en),//Local Condition @538 +// .module_en (cp0_fpu_icg_en) @539 +// ); @540 +// &Force("output", "ex2_pipe_clk"); @541 + +assign expnt_rst_clk_en = ex1_save_op0_gate + || ex1_pipedown_gate + || ex2_pipedown + || ex3_pipedown; +// &Instance("gated_clk_cell", "x_expnt_rst_clk"); @547 +gated_clk_cell x_expnt_rst_clk ( + .clk_in (forever_cpuclk ), + .clk_out (expnt_rst_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (expnt_rst_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect(.clk_in (forever_cpuclk), @548 +// .external_en (1'b0), @549 +// .global_en (cp0_yy_clk_en), @550 +// .module_en (cp0_fpu_icg_en), @551 +// .local_en (expnt_rst_clk_en), @552 +// .clk_out (expnt_rst_clk)); @553 + +//========================================================== +// Output Signal +//========================================================== +assign fdsu_yy_wb_freg[4:0] = fdsu_wb_freg[4:0]; +assign fdsu_yy_result_sign = fdsu_result_sign; +assign fdsu_yy_op0_norm = fdsu_op0_norm; +assign fdsu_yy_op1_norm = fdsu_op1_norm; +assign fdsu_yy_of_rm_lfn = fdsu_of_rm_lfn; +assign fdsu_yy_div = fdsu_div; +assign fdsu_yy_sqrt = fdsu_sqrt; +assign fdsu_yy_rm[2:0] = fdsu_rm[2:0]; + +assign fdsu_yy_expnt_rst[9:0] = fdsu_expnt_rst[9:0]; +assign ex2_expnt_adder_op0[9:0] = fdsu_expnt_rst[9:0]; + +assign fdsu_yy_result_inf = fdsu_result_inf; +assign fdsu_yy_result_lfn = fdsu_result_lfn; +assign fdsu_yy_of = fdsu_of; +assign fdsu_yy_uf = fdsu_uf; +assign fdsu_yy_potnt_of = fdsu_potnt_of; +assign fdsu_yy_potnt_uf = fdsu_potnt_uf; + +assign ex1_pipedown = ctrl_iter_start || ctrl_xx_ex1_warm_up; +assign ex1_pipedown_gate = ctrl_iter_start_gate || ctrl_xx_ex1_warm_up; +assign ex2_pipedown = ctrl_srt_itering && srt_last_round || ctrl_xx_ex2_warm_up; +assign ex3_pipedown = ctrl_round || ctrl_xx_ex3_warm_up; +// &Force("output", "ex1_pipedown"); @589 +// &Force("output", "ex1_pipedown_gate"); @590 +// &Force("output", "ex2_pipedown"); @591 +// &Force("output", "ex3_pipedown"); @592 + +assign srt_sm_on = ctrl_srt_itering; + +assign fdsu_fpu_ex1_cmplt = fdsu_ex1_inst_vld; +assign fdsu_fpu_ex1_cmplt_dp = ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel[2]; +assign fdsu_fpu_ex1_stall = ctrl_fdsu_ex1_stall; +assign fdsu_frbus_wb_vld = ctrl_result_vld; +// &Force("bus","idu_fpu_ex1_eu_sel",2,0); @600 +assign fdsu_fpu_no_op = !fdsu_busy; +assign ex1_op1_sel = ctrl_wfi2; +assign ex1_save_op0 = ctrl_sm_start && ex1_op0_id && ex1_op1_id_vld; +assign ex1_save_op0_gate = ctrl_sm_start_gate && ex1_op0_id && ex1_op1_id_vld; +// &Force("output", "ex1_save_op0"); @605 +// &Force("output", "ex1_save_op0_gate"); @606 + +assign fdsu_fpu_debug_info[4:0] = {wb_cur_state[1:0], fdsu_cur_state[2:0]}; + +// &ModuleEnd; @610 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_ff1.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_ff1( + fanc_shift_num, + frac_bin_val, + frac_num +); + +// &Ports; @24 +input [51:0] frac_num; +output [51:0] fanc_shift_num; +output [12:0] frac_bin_val; + +// &Regs; @25 +reg [51:0] fanc_shift_num; +reg [12:0] frac_bin_val; + +// &Wires; @26 +wire [51:0] frac_num; + + +// &CombBeg; @28 +always @( frac_num[51:0]) +begin +casez(frac_num[51:0]) + 52'b1???????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h0; + 52'b01??????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1fff; + 52'b001?????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffe; + 52'b0001????????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffd; + 52'b00001???????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffc; + 52'b000001??????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffb; + 52'b0000001?????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ffa; + 52'b00000001????????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff9; + 52'b000000001???????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff8; + 52'b0000000001??????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff7; + 52'b00000000001?????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff6; + 52'b000000000001????????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff5; + 52'b0000000000001???????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff4; + 52'b00000000000001??????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff3; + 52'b000000000000001?????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff2; + 52'b0000000000000001????????????????????????????????????: frac_bin_val[12:0] = 13'h1ff1; + 52'b00000000000000001???????????????????????????????????: frac_bin_val[12:0] = 13'h1ff0; + 52'b000000000000000001??????????????????????????????????: frac_bin_val[12:0] = 13'h1fef; + 52'b0000000000000000001?????????????????????????????????: frac_bin_val[12:0] = 13'h1fee; + 52'b00000000000000000001????????????????????????????????: frac_bin_val[12:0] = 13'h1fed; + 52'b000000000000000000001???????????????????????????????: frac_bin_val[12:0] = 13'h1fec; + 52'b0000000000000000000001??????????????????????????????: frac_bin_val[12:0] = 13'h1feb; + 52'b00000000000000000000001?????????????????????????????: frac_bin_val[12:0] = 13'h1fea; + 52'b000000000000000000000001????????????????????????????: frac_bin_val[12:0] = 13'h1fe9; + 52'b0000000000000000000000001???????????????????????????: frac_bin_val[12:0] = 13'h1fe8; + 52'b00000000000000000000000001??????????????????????????: frac_bin_val[12:0] = 13'h1fe7; + 52'b000000000000000000000000001?????????????????????????: frac_bin_val[12:0] = 13'h1fe6; + 52'b0000000000000000000000000001????????????????????????: frac_bin_val[12:0] = 13'h1fe5; + 52'b00000000000000000000000000001???????????????????????: frac_bin_val[12:0] = 13'h1fe4; + 52'b000000000000000000000000000001??????????????????????: frac_bin_val[12:0] = 13'h1fe3; + 52'b0000000000000000000000000000001?????????????????????: frac_bin_val[12:0] = 13'h1fe2; + 52'b00000000000000000000000000000001????????????????????: frac_bin_val[12:0] = 13'h1fe1; + 52'b000000000000000000000000000000001???????????????????: frac_bin_val[12:0] = 13'h1fe0; + 52'b0000000000000000000000000000000001??????????????????: frac_bin_val[12:0] = 13'h1fdf; + 52'b00000000000000000000000000000000001?????????????????: frac_bin_val[12:0] = 13'h1fde; + 52'b000000000000000000000000000000000001????????????????: frac_bin_val[12:0] = 13'h1fdd; + 52'b0000000000000000000000000000000000001???????????????: frac_bin_val[12:0] = 13'h1fdc; + 52'b00000000000000000000000000000000000001??????????????: frac_bin_val[12:0] = 13'h1fdb; + 52'b000000000000000000000000000000000000001?????????????: frac_bin_val[12:0] = 13'h1fda; + 52'b0000000000000000000000000000000000000001????????????: frac_bin_val[12:0] = 13'h1fd9; + 52'b00000000000000000000000000000000000000001???????????: frac_bin_val[12:0] = 13'h1fd8; + 52'b000000000000000000000000000000000000000001??????????: frac_bin_val[12:0] = 13'h1fd7; + 52'b0000000000000000000000000000000000000000001?????????: frac_bin_val[12:0] = 13'h1fd6; + 52'b00000000000000000000000000000000000000000001????????: frac_bin_val[12:0] = 13'h1fd5; + 52'b000000000000000000000000000000000000000000001???????: frac_bin_val[12:0] = 13'h1fd4; + 52'b0000000000000000000000000000000000000000000001??????: frac_bin_val[12:0] = 13'h1fd3; + 52'b00000000000000000000000000000000000000000000001?????: frac_bin_val[12:0] = 13'h1fd2; + 52'b000000000000000000000000000000000000000000000001????: frac_bin_val[12:0] = 13'h1fd1; + 52'b0000000000000000000000000000000000000000000000001???: frac_bin_val[12:0] = 13'h1fd0; + 52'b00000000000000000000000000000000000000000000000001??: frac_bin_val[12:0] = 13'h1fcf; + 52'b000000000000000000000000000000000000000000000000001?: frac_bin_val[12:0] = 13'h1fce; + 52'b0000000000000000000000000000000000000000000000000001: frac_bin_val[12:0] = 13'h1fcd; + 52'b0000000000000000000000000000000000000000000000000000: frac_bin_val[12:0] = 13'h1fcc; + default : frac_bin_val[12:0] = 13'h000; +endcase +// &CombEnd; @85 +end + +// &CombBeg; @87 +always @( frac_num[51:0]) +begin +casez(frac_num[51:0]) + 52'b1???????????????????????????????????????????????????: fanc_shift_num[51:0] = frac_num[51:0]; + 52'b01??????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[50:0],1'b0}; + 52'b001?????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[49:0],2'b0}; + 52'b0001????????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[48:0],3'b0}; + 52'b00001???????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[47:0],4'b0}; + 52'b000001??????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[46:0],5'b0}; + 52'b0000001?????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[45:0],6'b0}; + 52'b00000001????????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[44:0],7'b0}; + 52'b000000001???????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[43:0],8'b0}; + 52'b0000000001??????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[42:0],9'b0}; + 52'b00000000001?????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[41:0],10'b0}; + 52'b000000000001????????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[40:0],11'b0}; + 52'b0000000000001???????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[39:0],12'b0}; + 52'b00000000000001??????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[38:0],13'b0}; + 52'b000000000000001?????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[37:0],14'b0}; + 52'b0000000000000001????????????????????????????????????: fanc_shift_num[51:0] = {frac_num[36:0],15'b0}; + 52'b00000000000000001???????????????????????????????????: fanc_shift_num[51:0] = {frac_num[35:0],16'b0}; + 52'b000000000000000001??????????????????????????????????: fanc_shift_num[51:0] = {frac_num[34:0],17'b0}; + 52'b0000000000000000001?????????????????????????????????: fanc_shift_num[51:0] = {frac_num[33:0],18'b0}; + 52'b00000000000000000001????????????????????????????????: fanc_shift_num[51:0] = {frac_num[32:0],19'b0}; + 52'b000000000000000000001???????????????????????????????: fanc_shift_num[51:0] = {frac_num[31:0],20'b0}; + 52'b0000000000000000000001??????????????????????????????: fanc_shift_num[51:0] = {frac_num[30:0],21'b0}; + 52'b00000000000000000000001?????????????????????????????: fanc_shift_num[51:0] = {frac_num[29:0],22'b0}; + 52'b000000000000000000000001????????????????????????????: fanc_shift_num[51:0] = {frac_num[28:0],23'b0}; + 52'b0000000000000000000000001???????????????????????????: fanc_shift_num[51:0] = {frac_num[27:0],24'b0}; + 52'b00000000000000000000000001??????????????????????????: fanc_shift_num[51:0] = {frac_num[26:0],25'b0}; + 52'b000000000000000000000000001?????????????????????????: fanc_shift_num[51:0] = {frac_num[25:0],26'b0}; + 52'b0000000000000000000000000001????????????????????????: fanc_shift_num[51:0] = {frac_num[24:0],27'b0}; + 52'b00000000000000000000000000001???????????????????????: fanc_shift_num[51:0] = {frac_num[23:0],28'b0}; + 52'b000000000000000000000000000001??????????????????????: fanc_shift_num[51:0] = {frac_num[22:0],29'b0}; + 52'b0000000000000000000000000000001?????????????????????: fanc_shift_num[51:0] = {frac_num[21:0],30'b0}; + 52'b00000000000000000000000000000001????????????????????: fanc_shift_num[51:0] = {frac_num[20:0],31'b0}; + 52'b000000000000000000000000000000001???????????????????: fanc_shift_num[51:0] = {frac_num[19:0],32'b0}; + 52'b0000000000000000000000000000000001??????????????????: fanc_shift_num[51:0] = {frac_num[18:0],33'b0}; + 52'b00000000000000000000000000000000001?????????????????: fanc_shift_num[51:0] = {frac_num[17:0],34'b0}; + 52'b000000000000000000000000000000000001????????????????: fanc_shift_num[51:0] = {frac_num[16:0],35'b0}; + 52'b0000000000000000000000000000000000001???????????????: fanc_shift_num[51:0] = {frac_num[15:0],36'b0}; + 52'b00000000000000000000000000000000000001??????????????: fanc_shift_num[51:0] = {frac_num[14:0],37'b0}; + 52'b000000000000000000000000000000000000001?????????????: fanc_shift_num[51:0] = {frac_num[13:0],38'b0}; + 52'b0000000000000000000000000000000000000001????????????: fanc_shift_num[51:0] = {frac_num[12:0],39'b0}; + 52'b00000000000000000000000000000000000000001???????????: fanc_shift_num[51:0] = {frac_num[11:0],40'b0}; + 52'b000000000000000000000000000000000000000001??????????: fanc_shift_num[51:0] = {frac_num[10:0],41'b0}; + 52'b0000000000000000000000000000000000000000001?????????: fanc_shift_num[51:0] = {frac_num[9:0],42'b0}; + 52'b00000000000000000000000000000000000000000001????????: fanc_shift_num[51:0] = {frac_num[8:0],43'b0}; + 52'b000000000000000000000000000000000000000000001???????: fanc_shift_num[51:0] = {frac_num[7:0],44'b0}; + 52'b0000000000000000000000000000000000000000000001??????: fanc_shift_num[51:0] = {frac_num[6:0],45'b0}; + 52'b00000000000000000000000000000000000000000000001?????: fanc_shift_num[51:0] = {frac_num[5:0],46'b0}; + 52'b000000000000000000000000000000000000000000000001????: fanc_shift_num[51:0] = {frac_num[4:0],47'b0}; + 52'b0000000000000000000000000000000000000000000000001???: fanc_shift_num[51:0] = {frac_num[3:0],48'b0}; + 52'b00000000000000000000000000000000000000000000000001??: fanc_shift_num[51:0] = {frac_num[2:0],49'b0}; + 52'b000000000000000000000000000000000000000000000000001?: fanc_shift_num[51:0] = {frac_num[1:0],50'b0}; + 52'b0000000000000000000000000000000000000000000000000001: fanc_shift_num[51:0] = {frac_num[0:0],51'b0}; + 52'b0000000000000000000000000000000000000000000000000000: fanc_shift_num[51:0] = {52'b0}; + default : fanc_shift_num[51:0] = {52'b0}; +endcase +// &CombEnd; @144 +end + +// &ModuleEnd; @146 +endmodule + + +// ----- 8< ----- FILE "./pa_fdsu_pack_single.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_pack_single( + fdsu_ex4_denorm_to_tiny_frac, + fdsu_ex4_frac, + fdsu_ex4_nx, + fdsu_ex4_potnt_norm, + fdsu_ex4_result_nor, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_freg, + fdsu_yy_expnt_rst, + fdsu_yy_of, + fdsu_yy_of_rm_lfn, + fdsu_yy_potnt_of, + fdsu_yy_potnt_uf, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rslt_denorm, + fdsu_yy_uf, + fdsu_yy_wb_freg +); + +// &Ports; @24 +input fdsu_ex4_denorm_to_tiny_frac; +input [25:0] fdsu_ex4_frac; +input fdsu_ex4_nx; +input [1 :0] fdsu_ex4_potnt_norm; +input fdsu_ex4_result_nor; +input [9 :0] fdsu_yy_expnt_rst; +input fdsu_yy_of; +input fdsu_yy_of_rm_lfn; +input fdsu_yy_potnt_of; +input fdsu_yy_potnt_uf; +input fdsu_yy_result_inf; +input fdsu_yy_result_lfn; +input fdsu_yy_result_sign; +input fdsu_yy_rslt_denorm; +input fdsu_yy_uf; +input [4 :0] fdsu_yy_wb_freg; +output [31:0] fdsu_frbus_data; +output [4 :0] fdsu_frbus_fflags; +output [4 :0] fdsu_frbus_freg; + +// &Regs; @25 +reg [22:0] ex4_frac_23; +reg [31:0] ex4_result; +reg [22:0] ex4_single_denorm_frac; +reg [9 :0] expnt_add_op1; + +// &Wires; @26 +wire ex4_cor_nx; +wire ex4_cor_uf; +wire ex4_denorm_potnt_norm; +wire [31:0] ex4_denorm_result; +wire [9 :0] ex4_expnt_rst; +wire [4 :0] ex4_expt; +wire ex4_final_rst_norm; +wire [25:0] ex4_frac; +wire ex4_of_plus; +wire ex4_result_inf; +wire ex4_result_lfn; +wire ex4_rslt_denorm; +wire [31:0] ex4_rst_inf; +wire [31:0] ex4_rst_lfn; +wire ex4_rst_nor; +wire [31:0] ex4_rst_norm; +wire ex4_uf_plus; +wire fdsu_ex4_denorm_to_tiny_frac; +wire fdsu_ex4_dz; +wire [9 :0] fdsu_ex4_expnt_rst; +wire [25:0] fdsu_ex4_frac; +wire fdsu_ex4_nv; +wire fdsu_ex4_nx; +wire fdsu_ex4_of; +wire fdsu_ex4_of_rst_lfn; +wire [1 :0] fdsu_ex4_potnt_norm; +wire fdsu_ex4_potnt_of; +wire fdsu_ex4_potnt_uf; +wire fdsu_ex4_result_inf; +wire fdsu_ex4_result_lfn; +wire fdsu_ex4_result_nor; +wire fdsu_ex4_result_sign; +wire fdsu_ex4_rslt_denorm; +wire fdsu_ex4_uf; +wire [31:0] fdsu_frbus_data; +wire [4 :0] fdsu_frbus_fflags; +wire [4 :0] fdsu_frbus_freg; +wire [9 :0] fdsu_yy_expnt_rst; +wire fdsu_yy_of; +wire fdsu_yy_of_rm_lfn; +wire fdsu_yy_potnt_of; +wire fdsu_yy_potnt_uf; +wire fdsu_yy_result_inf; +wire fdsu_yy_result_lfn; +wire fdsu_yy_result_sign; +wire fdsu_yy_rslt_denorm; +wire fdsu_yy_uf; +wire [4 :0] fdsu_yy_wb_freg; + + +assign fdsu_ex4_result_sign = fdsu_yy_result_sign; +assign fdsu_ex4_of_rst_lfn = fdsu_yy_of_rm_lfn; +assign fdsu_ex4_result_inf = fdsu_yy_result_inf; +assign fdsu_ex4_result_lfn = fdsu_yy_result_lfn; +assign fdsu_ex4_of = fdsu_yy_of; +assign fdsu_ex4_uf = fdsu_yy_uf; +assign fdsu_ex4_potnt_of = fdsu_yy_potnt_of; +assign fdsu_ex4_potnt_uf = fdsu_yy_potnt_uf; +assign fdsu_ex4_nv = 1'b0; +assign fdsu_ex4_dz = 1'b0; +assign fdsu_ex4_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; +assign fdsu_ex4_rslt_denorm = fdsu_yy_rslt_denorm; +//============================EX4 STAGE===================== +assign ex4_frac[25:0] = fdsu_ex4_frac[25:0]; +//exponent adder +// &CombBeg; @43 +always @( ex4_frac[25:24]) +begin +casez(ex4_frac[25:24]) + 2'b00 : expnt_add_op1[9:0] = 10'h1ff; //the expnt sub 1 + 2'b01 : expnt_add_op1[9:0] = 10'h0; //the expnt stay the origi + 2'b1? : expnt_add_op1[9:0] = 10'h1; // the exptn add 1 + default : expnt_add_op1[9:0] = 10'b0; +endcase +// &CombEnd; @50 +end +assign ex4_expnt_rst[9:0] = fdsu_ex4_expnt_rst[9:0] + + expnt_add_op1[9:0]; + +//==========================Result Pack===================== + +// result denormal pack +// shift to the denormal number +// &CombBeg; @58 +always @( fdsu_ex4_expnt_rst[9:0] + or fdsu_ex4_denorm_to_tiny_frac + or ex4_frac[25:1]) +begin +case(fdsu_ex4_expnt_rst[9:0]) + 10'h1: ex4_single_denorm_frac[22:0] = { ex4_frac[23:1]}; //-1022 1 + 10'h0: ex4_single_denorm_frac[22:0] = { ex4_frac[24:2]}; //-1023 0 + 10'h3ff:ex4_single_denorm_frac[22:0] = { ex4_frac[25:3]}; //-1024 -1 + 10'h3fe:ex4_single_denorm_frac[22:0] = {1'b0, ex4_frac[25:4]}; //-1025 -2 + 10'h3fd:ex4_single_denorm_frac[22:0] = {2'b0, ex4_frac[25:5]}; //-1026 -3 + 10'h3fc:ex4_single_denorm_frac[22:0] = {3'b0, ex4_frac[25:6]}; //-1027 -4 + 10'h3fb:ex4_single_denorm_frac[22:0] = {4'b0, ex4_frac[25:7]}; //-1028 -5 + 10'h3fa:ex4_single_denorm_frac[22:0] = {5'b0, ex4_frac[25:8]}; //-1029 -6 + 10'h3f9:ex4_single_denorm_frac[22:0] = {6'b0, ex4_frac[25:9]}; //-1030 -7 + 10'h3f8:ex4_single_denorm_frac[22:0] = {7'b0, ex4_frac[25:10]}; //-1031 -8 + 10'h3f7:ex4_single_denorm_frac[22:0] = {8'b0, ex4_frac[25:11]}; //-1032 -9 + 10'h3f6:ex4_single_denorm_frac[22:0] = {9'b0, ex4_frac[25:12]}; //-1033 -10 + 10'h3f5:ex4_single_denorm_frac[22:0] = {10'b0,ex4_frac[25:13]}; //-1034 -11 + 10'h3f4:ex4_single_denorm_frac[22:0] = {11'b0,ex4_frac[25:14]}; //-1035 -12 + 10'h3f3:ex4_single_denorm_frac[22:0] = {12'b0,ex4_frac[25:15]}; //-1036 -13 + 10'h3f2:ex4_single_denorm_frac[22:0] = {13'b0,ex4_frac[25:16]}; // -1037 + 10'h3f1:ex4_single_denorm_frac[22:0] = {14'b0,ex4_frac[25:17]}; //-1038 + 10'h3f0:ex4_single_denorm_frac[22:0] = {15'b0,ex4_frac[25:18]}; //-1039 + 10'h3ef:ex4_single_denorm_frac[22:0] = {16'b0,ex4_frac[25:19]}; //-1040 + 10'h3ee:ex4_single_denorm_frac[22:0] = {17'b0,ex4_frac[25:20]}; //-1041 + 10'h3ed:ex4_single_denorm_frac[22:0] = {18'b0,ex4_frac[25:21]}; //-1042 + 10'h3ec:ex4_single_denorm_frac[22:0] = {19'b0,ex4_frac[25:22]}; //-1043 + 10'h3eb:ex4_single_denorm_frac[22:0] = {20'b0,ex4_frac[25:23]}; //-1044 + 10'h3ea:ex4_single_denorm_frac[22:0] = {21'b0,ex4_frac[25:24]}; //-1044 + default :ex4_single_denorm_frac[22:0] = fdsu_ex4_denorm_to_tiny_frac ? 23'b1 : 23'b0; //-1045 +endcase +// &CombEnd; @86 +end +//here when denormal number round to add1, it will become normal number +assign ex4_denorm_potnt_norm = (fdsu_ex4_potnt_norm[1] && ex4_frac[24]) || + (fdsu_ex4_potnt_norm[0] && ex4_frac[25]) ; +assign ex4_rslt_denorm = fdsu_ex4_rslt_denorm && !ex4_denorm_potnt_norm; +assign ex4_denorm_result[31:0] = {fdsu_ex4_result_sign, + 8'h0,ex4_single_denorm_frac[22:0]}; + + +//ex4 overflow/underflow plus +assign ex4_rst_nor = fdsu_ex4_result_nor; +assign ex4_of_plus = fdsu_ex4_potnt_of && + (|ex4_frac[25:24]) && + ex4_rst_nor; +assign ex4_uf_plus = fdsu_ex4_potnt_uf && + (~|ex4_frac[25:24]) && + ex4_rst_nor; +//ex4 overflow round result +assign ex4_result_lfn = (ex4_of_plus && fdsu_ex4_of_rst_lfn) || + fdsu_ex4_result_lfn; +assign ex4_result_inf = (ex4_of_plus && !fdsu_ex4_of_rst_lfn) || + fdsu_ex4_result_inf; +//Special Result Form +// result largest finity number +assign ex4_rst_lfn[31:0] = {fdsu_ex4_result_sign,8'hfe,{23{1'b1}}}; +//result infinity +assign ex4_rst_inf[31:0] = {fdsu_ex4_result_sign,8'hff,23'b0}; +//result normal +// &CombBeg; @114 +always @( ex4_frac[25:0]) +begin +casez(ex4_frac[25:24]) + 2'b00 : ex4_frac_23[22:0] = ex4_frac[22:0]; + 2'b01 : ex4_frac_23[22:0] = ex4_frac[23:1]; + 2'b1? : ex4_frac_23[22:0] = ex4_frac[24:2]; + default : ex4_frac_23[22:0] = 23'b0; +endcase +// &CombEnd; @121 +end +assign ex4_rst_norm[31:0] = {fdsu_ex4_result_sign, + ex4_expnt_rst[7:0], + ex4_frac_23[22:0]}; +assign ex4_cor_uf = (fdsu_ex4_uf || ex4_denorm_potnt_norm || ex4_uf_plus) + && fdsu_ex4_nx; +assign ex4_cor_nx = fdsu_ex4_nx + || fdsu_ex4_of + || ex4_of_plus; + +assign ex4_expt[4:0] = { + fdsu_ex4_nv, + fdsu_ex4_dz, + fdsu_ex4_of | ex4_of_plus, + ex4_cor_uf, + ex4_cor_nx}; + +assign ex4_final_rst_norm = !ex4_result_inf && + !ex4_result_lfn && + !ex4_rslt_denorm; +// &CombBeg; @141 +always @( ex4_denorm_result[31:0] + or ex4_result_lfn + or ex4_result_inf + or ex4_final_rst_norm + or ex4_rst_norm[31:0] + or ex4_rst_lfn[31:0] + or ex4_rst_inf[31:0] + or ex4_rslt_denorm) +begin +case({ex4_rslt_denorm, + ex4_result_inf, + ex4_result_lfn, + ex4_final_rst_norm}) + 4'b1000 : ex4_result[31:0] = ex4_denorm_result[31:0]; + 4'b0100 : ex4_result[31:0] = ex4_rst_inf[31:0]; + 4'b0010 : ex4_result[31:0] = ex4_rst_lfn[31:0]; + 4'b0001 : ex4_result[31:0] = ex4_rst_norm[31:0]; + default : ex4_result[31:0] = 32'b0; +endcase +// &CombEnd; @152 +end + +//========================================================== +// Result Generate +//========================================================== +assign fdsu_frbus_freg[4:0] = fdsu_yy_wb_freg[4:0]; +assign fdsu_frbus_data[31:0] = ex4_result[31:0]; +assign fdsu_frbus_fflags[4:0] = ex4_expt[4:0]; + +// &ModuleEnd; @161 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_prepare.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_prepare( + dp_xx_ex1_rm, + ex1_div, + ex1_divisor, + ex1_expnt_adder_op0, + ex1_expnt_adder_op1, + ex1_of_result_lfn, + ex1_op0_id, + ex1_op0_sign, + ex1_op1_id, + ex1_op1_id_vld, + ex1_op1_sel, + ex1_oper_id_expnt, + ex1_oper_id_expnt_f, + ex1_oper_id_frac, + ex1_oper_id_frac_f, + ex1_remainder, + ex1_result_sign, + ex1_rm, + ex1_sqrt, + fdsu_ex1_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1 +); + +// &Ports; @24 +input [2 :0] dp_xx_ex1_rm; +input ex1_op0_id; +input ex1_op1_id; +input ex1_op1_sel; +input [12:0] ex1_oper_id_expnt_f; +input [51:0] ex1_oper_id_frac_f; +input fdsu_ex1_sel; +input [9 :0] idu_fpu_ex1_func; +input [31:0] idu_fpu_ex1_srcf0; +input [31:0] idu_fpu_ex1_srcf1; +output ex1_div; +output [23:0] ex1_divisor; +output [12:0] ex1_expnt_adder_op0; +output [12:0] ex1_expnt_adder_op1; +output ex1_of_result_lfn; +output ex1_op0_sign; +output ex1_op1_id_vld; +output [12:0] ex1_oper_id_expnt; +output [51:0] ex1_oper_id_frac; +output [31:0] ex1_remainder; +output ex1_result_sign; +output [2 :0] ex1_rm; +output ex1_sqrt; + +// &Regs; @25 +reg [12:0] ex1_expnt_adder_op1; +reg ex1_of_result_lfn; + +// &Wires; @26 +wire div_sign; +wire [2 :0] dp_xx_ex1_rm; +wire ex1_div; +wire [52:0] ex1_div_noid_nor_srt_op0; +wire [52:0] ex1_div_noid_nor_srt_op1; +wire [52:0] ex1_div_nor_srt_op0; +wire [52:0] ex1_div_nor_srt_op1; +wire [12:0] ex1_div_op0_expnt; +wire [12:0] ex1_div_op1_expnt; +wire [52:0] ex1_div_srt_op0; +wire [52:0] ex1_div_srt_op1; +wire [23:0] ex1_divisor; +wire ex1_double; +wire [12:0] ex1_expnt_adder_op0; +wire ex1_op0_id; +wire ex1_op0_id_nor; +wire ex1_op0_sign; +wire ex1_op1_id; +wire ex1_op1_id_nor; +wire ex1_op1_id_vld; +wire ex1_op1_sel; +wire ex1_op1_sign; +wire [63:0] ex1_oper0; +wire [51:0] ex1_oper0_frac; +wire [12:0] ex1_oper0_id_expnt; +wire [51:0] ex1_oper0_id_frac; +wire [63:0] ex1_oper1; +wire [51:0] ex1_oper1_frac; +wire [12:0] ex1_oper1_id_expnt; +wire [51:0] ex1_oper1_id_frac; +wire [51:0] ex1_oper_frac; +wire [12:0] ex1_oper_id_expnt; +wire [12:0] ex1_oper_id_expnt_f; +wire [51:0] ex1_oper_id_frac; +wire [51:0] ex1_oper_id_frac_f; +wire [31:0] ex1_remainder; +wire ex1_result_sign; +wire [2 :0] ex1_rm; +wire ex1_single; +wire ex1_sqrt; +wire ex1_sqrt_expnt_odd; +wire ex1_sqrt_op0_expnt_0; +wire [12:0] ex1_sqrt_op1_expnt; +wire [52:0] ex1_sqrt_srt_op0; +wire fdsu_ex1_sel; +wire [9 :0] idu_fpu_ex1_func; +wire [31:0] idu_fpu_ex1_srcf0; +wire [31:0] idu_fpu_ex1_srcf1; +wire [59:0] sqrt_remainder; +wire sqrt_sign; + + +assign ex1_sqrt = idu_fpu_ex1_func[0]; +assign ex1_div = idu_fpu_ex1_func[1]; +assign ex1_oper0[63:0] = {32'b0, idu_fpu_ex1_srcf0[31:0] & {32{fdsu_ex1_sel}}}; +assign ex1_oper1[63:0] = {32'b0, idu_fpu_ex1_srcf1[31:0] & {32{fdsu_ex1_sel}}}; +assign ex1_double = 1'b0; +assign ex1_single = 1'b1; +// &Force("bus", "idu_fpu_ex1_func", 9, 0); @43 +assign ex1_op0_id_nor = ex1_op0_id; +assign ex1_op1_id_nor = ex1_op1_id; + +//Sign bit prepare +assign ex1_op0_sign = ex1_double && ex1_oper0[63] + || ex1_single && ex1_oper0[31]; +assign ex1_op1_sign = ex1_double && ex1_oper1[63] + || ex1_single && ex1_oper1[31]; +assign div_sign = ex1_op0_sign ^ ex1_op1_sign; +assign sqrt_sign = ex1_op0_sign; +assign ex1_result_sign = (ex1_div) + ? div_sign + : sqrt_sign; + +//=====================find first one======================= +// this is for the denormal number +assign ex1_oper_frac[51:0] = ex1_op1_sel ? ex1_oper1_frac[51:0] + : ex1_oper0_frac[51:0]; + +// &Instance("pa_fdsu_ff1", "x_frac_expnt"); @63 +pa_fdsu_ff1 x_frac_expnt ( + .fanc_shift_num (ex1_oper_id_frac[51:0] ), + .frac_bin_val (ex1_oper_id_expnt[12:0]), + .frac_num (ex1_oper_frac[51:0] ) +); + +// &Connect(.frac_num(ex1_oper_frac[51:0])); @64 +// &Connect(.frac_bin_val(ex1_oper_id_expnt[12:0])); @65 +// &Connect(.fanc_shift_num(ex1_oper_id_frac[51:0])); @66 +// &Force("output", "ex1_oper_id_expnt"); &Force("bus", "ex1_oper_id_expnt", 12, 0); @67 +// &Force("output", "ex1_oper_id_frac"); &Force("bus", "ex1_oper_id_frac", 51, 0); @68 + +assign ex1_oper0_id_expnt[12:0] = ex1_op1_sel ? ex1_oper_id_expnt_f[12:0] + : ex1_oper_id_expnt[12:0]; +assign ex1_oper0_id_frac[51:0] = ex1_op1_sel ? ex1_oper_id_frac_f[51:0] + : ex1_oper_id_frac[51:0]; +assign ex1_oper1_id_expnt[12:0] = ex1_oper_id_expnt[12:0]; +assign ex1_oper1_id_frac[51:0] = ex1_oper_id_frac[51:0]; + +assign ex1_oper0_frac[51:0] = {52{ex1_double}} & ex1_oper0[51:0] + | {52{ex1_single}} & {ex1_oper0[22:0],29'b0}; +assign ex1_oper1_frac[51:0] = {52{ex1_double}} & ex1_oper1[51:0] + | {52{ex1_single}} & {ex1_oper1[22:0],29'b0}; + +//=====================exponent add========================= +//exponent number 0 +assign ex1_div_op0_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper0[62:52]} + | {13{ex1_single}} & {5'b0,ex1_oper0[30:23]}; +assign ex1_expnt_adder_op0[12:0] = ex1_op0_id_nor ? ex1_oper0_id_expnt[12:0] + : ex1_div_op0_expnt[12:0]; +//exponent number 1 +assign ex1_div_op1_expnt[12:0] = {13{ex1_double}} & {2'b0,ex1_oper1[62:52]} + | {13{ex1_single}} & {5'b0,ex1_oper1[30:23]}; +assign ex1_sqrt_op1_expnt[12:0] = {13{ex1_double}} & {3'b0,{10{1'b1}}} //'d1023 + | {13{ex1_single}} & {6'b0,{7{1'b1}}}; //'d127 +// &CombBeg; @93 +always @( ex1_oper1_id_expnt[12:0] + or ex1_div + or ex1_op1_id_nor + or ex1_sqrt_op1_expnt[12:0] + or ex1_sqrt + or ex1_div_op1_expnt[12:0]) +begin +case({ex1_div,ex1_sqrt}) + 2'b10: ex1_expnt_adder_op1[12:0] = ex1_op1_id_nor ? ex1_oper1_id_expnt[12:0] + : ex1_div_op1_expnt[12:0]; + 2'b01: ex1_expnt_adder_op1[12:0] = ex1_sqrt_op1_expnt[12:0]; + default: ex1_expnt_adder_op1[12:0] = 13'b0; +endcase +// &CombEnd; @100 +end + +//ex1_sqrt_expnt_odd +//fraction will shift left by 1 +// adder_op0/1 timing is bad. +// assign ex1_sqrt_expnt_odd = ex1_expnt_adder_op0[0] ^ ex1_expnt_adder_op1[0]; + +// sqrt_odd is only used when is sqrt. +assign ex1_sqrt_op0_expnt_0 = ex1_op0_id_nor ? ex1_oper_id_expnt[0] + : ex1_div_op0_expnt[0]; +// ex1_expnt_adder_op1 is always 1'b1, so adder_op0[0] should be 0. +assign ex1_sqrt_expnt_odd = !ex1_sqrt_op0_expnt_0; + +assign ex1_rm[2:0] = dp_xx_ex1_rm[2:0]; +//RNE : Always inc 1 because round to nearest of 1.111...11 +//RTZ : Always not inc 1 +//RUP : Always not inc 1 when posetive +//RDN : Always not inc 1 when negative +//RMM : Always inc 1 because round to max magnitude +// &CombBeg; @119 +always @( ex1_rm[2:0] + or ex1_result_sign) +begin +case(ex1_rm[2:0]) + 3'b000 : ex1_of_result_lfn = 1'b0; + 3'b001 : ex1_of_result_lfn = 1'b1; + 3'b010 : ex1_of_result_lfn = !ex1_result_sign; + 3'b011 : ex1_of_result_lfn = ex1_result_sign; + 3'b100 : ex1_of_result_lfn = 1'b0; + default: ex1_of_result_lfn = 1'b0; +endcase +// &CombEnd; @128 +end + +//EX1 Remainder +//div : 1/8 <= x < 1/4 +//sqrt : 1/16 <= x < 1/4 +assign ex1_remainder[31:0] = {32{ex1_div }} & {5'b0,ex1_div_srt_op0[52:28],2'b0} | + {32{ex1_sqrt}} & sqrt_remainder[59:28]; + +//EX1 Divisor +//1/2 <= y < 1 +assign ex1_divisor[23:0] = ex1_div_srt_op1[52:29]; + +//ex1_div_srt_op0 +assign ex1_div_srt_op0[52:0] = ex1_div_nor_srt_op0[52:0]; +//ex1_div_srt_op1 +assign ex1_div_srt_op1[52:0] = ex1_div_nor_srt_op1[52:0]; +//ex1_div_nor_srt_op0 +assign ex1_div_noid_nor_srt_op0[52:0] = {53{ex1_double}} & {1'b1,ex1_oper0[51:0]} + | {53{ex1_single}} & {1'b1,ex1_oper0[22:0],29'b0}; +assign ex1_div_nor_srt_op0[52:0] = ex1_op0_id_nor ? {ex1_oper0_id_frac[51:0],1'b0} + : ex1_div_noid_nor_srt_op0[52:0]; +//ex1_div_nor_srt_op1 +assign ex1_div_noid_nor_srt_op1[52:0] = {53{ex1_double}} & {1'b1,ex1_oper1[51:0]} + | {53{ex1_single}} & {1'b1,ex1_oper1[22:0],29'b0}; +assign ex1_div_nor_srt_op1[52:0] = ex1_op1_id_nor ? {ex1_oper1_id_frac[51:0],1'b0} + : ex1_div_noid_nor_srt_op1[52:0]; +//sqrt_remainder +assign sqrt_remainder[59:0] = (ex1_sqrt_expnt_odd) + ? {5'b0,ex1_sqrt_srt_op0[52:0],2'b0} + : {6'b0,ex1_sqrt_srt_op0[52:0],1'b0}; +//ex1_sqrt_srt_op0 +assign ex1_sqrt_srt_op0[52:0] = ex1_div_srt_op0[52:0]; + +//========================Pipe to EX2======================= +//exponent register cal result +// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @173 +// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @174 +// &Force("output", "ex1_double"); @175 +// &Force("output", "ex1_expnt_adder_op0"); &Force("bus", "ex1_expnt_adder_op0", 12, 0); @177 +// &Force("output", "ex1_expnt_adder_op1"); &Force("bus", "ex1_expnt_adder_op1", 12, 0); @178 +// &Force("output", "ex1_result_sign"); @180 +// &Force("output", "ex1_div"); @181 +// &Force("output", "ex1_sqrt"); @182 +// &Force("output", "ex1_rm"); &Force("bus", "ex1_rm", 2, 0); @183 +// &Force("output", "ex1_op0_sign"); @184 + +assign ex1_op1_id_vld = ex1_op1_id_nor && ex1_div; + +// &ModuleEnd; @188 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_round_single.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_round_single( + cp0_fpu_icg_en, + cp0_yy_clk_en, + ex3_expnt_adjust_result, + ex3_frac_final_rst, + ex3_pipedown, + ex3_rslt_denorm, + fdsu_ex3_id_srt_skip, + fdsu_ex3_rem_sign, + fdsu_ex3_rem_zero, + fdsu_ex3_result_denorm_round_add_num, + fdsu_ex4_denorm_to_tiny_frac, + fdsu_ex4_nx, + fdsu_ex4_potnt_norm, + fdsu_ex4_result_nor, + fdsu_yy_expnt_rst, + fdsu_yy_result_inf, + fdsu_yy_result_lfn, + fdsu_yy_result_sign, + fdsu_yy_rm, + fdsu_yy_rslt_denorm, + forever_cpuclk, + pad_yy_icg_scan_en, + total_qt_rt_30 +); + +// &Ports; @24 +input cp0_fpu_icg_en; +input cp0_yy_clk_en; +input ex3_pipedown; +input fdsu_ex3_id_srt_skip; +input fdsu_ex3_rem_sign; +input fdsu_ex3_rem_zero; +input [23:0] fdsu_ex3_result_denorm_round_add_num; +input [9 :0] fdsu_yy_expnt_rst; +input fdsu_yy_result_inf; +input fdsu_yy_result_lfn; +input fdsu_yy_result_sign; +input [2 :0] fdsu_yy_rm; +input fdsu_yy_rslt_denorm; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input [29:0] total_qt_rt_30; +output [9 :0] ex3_expnt_adjust_result; +output [25:0] ex3_frac_final_rst; +output ex3_rslt_denorm; +output fdsu_ex4_denorm_to_tiny_frac; +output fdsu_ex4_nx; +output [1 :0] fdsu_ex4_potnt_norm; +output fdsu_ex4_result_nor; + +// &Regs; @25 +reg denorm_to_tiny_frac; +reg fdsu_ex4_denorm_to_tiny_frac; +reg fdsu_ex4_nx; +reg [1 :0] fdsu_ex4_potnt_norm; +reg fdsu_ex4_result_nor; +reg [25:0] frac_add1_op1; +reg frac_add_1; +reg frac_orig; +reg [25:0] frac_sub1_op1; +reg frac_sub_1; +reg [27:0] qt_result_single_denorm_for_round; +reg single_denorm_lst_frac; + +// &Wires; @26 +wire cp0_fpu_icg_en; +wire cp0_yy_clk_en; +wire ex3_denorm_eq; +wire ex3_denorm_gr; +wire ex3_denorm_lst_frac; +wire ex3_denorm_nx; +wire ex3_denorm_plus; +wire ex3_denorm_potnt_norm; +wire ex3_denorm_zero; +wire [9 :0] ex3_expnt_adjst; +wire [9 :0] ex3_expnt_adjust_result; +wire [25:0] ex3_frac_final_rst; +wire ex3_nx; +wire ex3_pipe_clk; +wire ex3_pipe_clk_en; +wire ex3_pipedown; +wire [1 :0] ex3_potnt_norm; +wire ex3_qt_eq; +wire ex3_qt_gr; +wire ex3_qt_sing_lo3_not0; +wire ex3_qt_sing_lo4_not0; +wire ex3_qt_zero; +wire ex3_rslt_denorm; +wire ex3_rst_eq_1; +wire ex3_rst_nor; +wire ex3_single_denorm_eq; +wire ex3_single_denorm_gr; +wire ex3_single_denorm_zero; +wire ex3_single_low_not_zero; +wire [9 :0] fdsu_ex3_expnt_rst; +wire fdsu_ex3_id_srt_skip; +wire fdsu_ex3_rem_sign; +wire fdsu_ex3_rem_zero; +wire [23:0] fdsu_ex3_result_denorm_round_add_num; +wire fdsu_ex3_result_inf; +wire fdsu_ex3_result_lfn; +wire fdsu_ex3_result_sign; +wire [2 :0] fdsu_ex3_rm; +wire fdsu_ex3_rslt_denorm; +wire [9 :0] fdsu_yy_expnt_rst; +wire fdsu_yy_result_inf; +wire fdsu_yy_result_lfn; +wire fdsu_yy_result_sign; +wire [2 :0] fdsu_yy_rm; +wire fdsu_yy_rslt_denorm; +wire forever_cpuclk; +wire [25:0] frac_add1_op1_with_denorm; +wire [25:0] frac_add1_rst; +wire frac_denorm_rdn_add_1; +wire frac_denorm_rdn_sub_1; +wire frac_denorm_rmm_add_1; +wire frac_denorm_rne_add_1; +wire frac_denorm_rtz_sub_1; +wire frac_denorm_rup_add_1; +wire frac_denorm_rup_sub_1; +wire [25:0] frac_final_rst; +wire frac_rdn_add_1; +wire frac_rdn_sub_1; +wire frac_rmm_add_1; +wire frac_rne_add_1; +wire frac_rtz_sub_1; +wire frac_rup_add_1; +wire frac_rup_sub_1; +wire [25:0] frac_sub1_op1_with_denorm; +wire [25:0] frac_sub1_rst; +wire pad_yy_icg_scan_en; +wire [29:0] total_qt_rt_30; + + +assign fdsu_ex3_result_sign = fdsu_yy_result_sign; +assign fdsu_ex3_expnt_rst[9:0] = fdsu_yy_expnt_rst[9:0]; +assign fdsu_ex3_result_inf = fdsu_yy_result_inf; +assign fdsu_ex3_result_lfn = fdsu_yy_result_lfn; +assign fdsu_ex3_rm[2:0] = fdsu_yy_rm[2:0]; +assign fdsu_ex3_rslt_denorm = fdsu_yy_rslt_denorm; +//=======================Round Rule========================= +//1/8 <= x < 1/4, 1/2 <= y < 1, => 1/8 < z < 1/2 +//q[29:0] represent the fraction part result of quotient, q[29] for 1/2 +//Thus the first "1" in 30 bit quotient will be in q[28] or q[27] +//For Single Float +//15 round to get 30 bit quotient, 23+1 bit as valid result, other for round +//if q[28] is 1, q[28:5] as 1.xxxx valid result, [4:0] for round +//if q[28] is 0, q[27:4] as 1.xxxx valid result, [3:0] for round +// &Force("bus","total_qt_rt_30",29,0); @42 +assign ex3_qt_sing_lo4_not0 = |total_qt_rt_30[3:0]; +assign ex3_qt_sing_lo3_not0 = |total_qt_rt_30[2:0]; +//the quotient round bits great than "10000"(ronnd bits 10..0) +assign ex3_qt_gr = (total_qt_rt_30[28]) + ? total_qt_rt_30[4] && ex3_qt_sing_lo4_not0 + : total_qt_rt_30[3] && ex3_qt_sing_lo3_not0; + +//the quotient round bits is equal to "10000"(ronnd bits 10..0) +assign ex3_qt_eq = (total_qt_rt_30[28]) + ? total_qt_rt_30[4] && !ex3_qt_sing_lo4_not0 + : total_qt_rt_30[3] && !ex3_qt_sing_lo3_not0; +//the quotient round bits is zero +assign ex3_qt_zero = (total_qt_rt_30[28]) + ? ~|total_qt_rt_30[4:0] + : ~|total_qt_rt_30[3:0]; +//quotient is 1.00000..00 need special dealt with in the following +assign ex3_rst_eq_1 = total_qt_rt_30[28] && ~|total_qt_rt_30[27:5]; +// for denormal result, first select the quotation num for rounding +// specially for the result e=-126 and e=-1022,the denorm depends on the +// MSB of the quotient +assign ex3_denorm_plus = !total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h382); +assign ex3_denorm_potnt_norm = total_qt_rt_30[28] && (fdsu_ex3_expnt_rst[9:0] == 10'h381); +assign ex3_rslt_denorm = ex3_denorm_plus || fdsu_ex3_rslt_denorm; +// &Force("output", "ex3_rslt_denorm"); @66 + +//denomal result, check for rounding further optimization can be done in +//future +// &CombBeg; @70 +always @( total_qt_rt_30[28:0] + or fdsu_ex3_expnt_rst[9:0]) +begin +case(fdsu_ex3_expnt_rst[9:0]) + 10'h382:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[4:0],23'b0}; //-126 1 + single_denorm_lst_frac = total_qt_rt_30[5]; + end//-1022 1 + 10'h381:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[5:0],22'b0}; //-127 0 + single_denorm_lst_frac = total_qt_rt_30[6]; + end//-1022 1 + 10'h380:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[6:0],21'b0}; //-128 -1 + single_denorm_lst_frac = total_qt_rt_30[7]; + end//-1022 1 + 10'h37f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[7:0],20'b0}; //-129 -2 + single_denorm_lst_frac = total_qt_rt_30[8]; + end//-1022 1 + 10'h37e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[8:0],19'b0}; //-130 -3 + single_denorm_lst_frac = total_qt_rt_30[9]; + end//-1022 1 + 10'h37d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[9:0],18'b0}; //-131 -4 + single_denorm_lst_frac = total_qt_rt_30[10]; + end//-1022 1 + 10'h37c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[10:0],17'b0}; //-132 -5 + single_denorm_lst_frac = total_qt_rt_30[11]; + end//-1022 1 + 10'h37b:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[11:0],16'b0}; //-133 -6 + single_denorm_lst_frac = total_qt_rt_30[12]; + end//-1022 1 + 10'h37a:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[12:0],15'b0}; //-134 -7 + single_denorm_lst_frac = total_qt_rt_30[13]; + end//-1022 1 + 10'h379:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[13:0],14'b0}; //-135 -8 + single_denorm_lst_frac = total_qt_rt_30[14]; + end//-1022 1 + 10'h378:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[14:0],13'b0}; //-136 -9 + single_denorm_lst_frac = total_qt_rt_30[15]; + end//-1022 1 + 10'h377:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[15:0],12'b0}; //-137 -10 + single_denorm_lst_frac = total_qt_rt_30[16]; + end//-1022 1 + 10'h376:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[16:0],11'b0}; //-138 -11 + single_denorm_lst_frac = total_qt_rt_30[17]; + end//-1022 1 + 10'h375:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[17:0],10'b0}; //-139 -12 + single_denorm_lst_frac = total_qt_rt_30[18]; + end//-1022 1 + 10'h374:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[18:0],9'b0}; //-140 -13 + single_denorm_lst_frac = total_qt_rt_30[19]; + end//-1022 1 + 10'h373:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[19:0],8'b0}; // -141 + single_denorm_lst_frac = total_qt_rt_30[20]; + end//-1022 1 + 10'h372:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[20:0],7'b0};//-142 + single_denorm_lst_frac = total_qt_rt_30[21]; + end//-1022 1 + 10'h371:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[21:0],6'b0};//-143 + single_denorm_lst_frac = total_qt_rt_30[22]; + end//-1022 1 + 10'h370:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[22:0],5'b0}; //-144 + single_denorm_lst_frac = total_qt_rt_30[23]; + end//-1022 1 + 10'h36f:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[23:0],4'b0}; //-145 + single_denorm_lst_frac = total_qt_rt_30[24]; + end//-1022 1 + 10'h36e:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[24:0],3'b0}; //-146 + single_denorm_lst_frac = total_qt_rt_30[25]; + end//-1022 1 + 10'h36d:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[25:0],2'b0}; //-147 + single_denorm_lst_frac = total_qt_rt_30[26]; + end//-1022 1 + 10'h36c:begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[26:0],1'b0}; //-148 + single_denorm_lst_frac = total_qt_rt_30[27]; + end//-1022 1 + 10'h36b: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[27:0]}; + single_denorm_lst_frac = total_qt_rt_30[28] ; + end//-1022 1 + default: begin qt_result_single_denorm_for_round[27:0] = {total_qt_rt_30[28:1]}; + single_denorm_lst_frac = 1'b0; + end//-1022 1 +endcase +// &CombEnd; @148 +end +//rounding evaluation for single denormalize number +assign ex3_single_denorm_eq = qt_result_single_denorm_for_round[27] + && !ex3_single_low_not_zero; +assign ex3_single_low_not_zero = |qt_result_single_denorm_for_round[26:0]; +assign ex3_single_denorm_gr = qt_result_single_denorm_for_round[27] + && ex3_single_low_not_zero; +assign ex3_single_denorm_zero = !qt_result_single_denorm_for_round[27] + && !ex3_single_low_not_zero; + +//rounding check fo denormalize result +assign ex3_denorm_eq = ex3_single_denorm_eq; +assign ex3_denorm_gr = ex3_single_denorm_gr; +assign ex3_denorm_zero = ex3_single_denorm_zero; +assign ex3_denorm_lst_frac = single_denorm_lst_frac; +//Different Round Mode with different rounding rule +//Here we call rounding bit as "rb", remainder as "rem" +//RNE : +// 1.+1 : rb>10000 || rb==10000 && rem>0 +// 2. 0 : Rest Condition +// 3.-1 : Never occur +//RTZ : +// 1.+1 : Never occur +// 2. 0 : Rest Condition +// 3.-1 : rb=10000 && rem<0 +//RDN : +// 1.+1 : Q>0 Never occur ; Q<0 Rest condition +// 2. 0 : Q>0 Rest condition; Q<0 Rem<0 && rb=0 +// 3.-1 : Q>0 Rem<0 && rb=0 ; Q<0 Never occur +//RUP : +// 1.+1 : Q>0 Rest Condition; Q<0 Never occur +// 2. 0 : Q>0 Rem<0 && rb=0 ; Q<0 Rest condition +// 3.-1 : Q>0 Never occur ; Q<0 Rem<0 && rb=0 +//RMM : +// 1.+1 : rb>10000 || rb==10000 && rem>0 +// 2. 0 : Rest Condition +// 3.-1 : Never occur +assign frac_rne_add_1 = ex3_qt_gr || + (ex3_qt_eq && !fdsu_ex3_rem_sign); +assign frac_rtz_sub_1 = ex3_qt_zero && fdsu_ex3_rem_sign; +assign frac_rup_add_1 = !fdsu_ex3_result_sign && + (!ex3_qt_zero || + (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); +assign frac_rup_sub_1 = fdsu_ex3_result_sign && + (ex3_qt_zero && fdsu_ex3_rem_sign); +assign frac_rdn_add_1 = fdsu_ex3_result_sign && + (!ex3_qt_zero || + (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); +assign frac_rdn_sub_1 = !fdsu_ex3_result_sign && + (ex3_qt_zero && fdsu_ex3_rem_sign); +assign frac_rmm_add_1 = ex3_qt_gr || + (ex3_qt_eq && !fdsu_ex3_rem_sign); +//denormal result +assign frac_denorm_rne_add_1 = ex3_denorm_gr || + (ex3_denorm_eq && + ((fdsu_ex3_rem_zero && + ex3_denorm_lst_frac) || + (!fdsu_ex3_rem_zero && + !fdsu_ex3_rem_sign))); +assign frac_denorm_rtz_sub_1 = ex3_denorm_zero && fdsu_ex3_rem_sign; +assign frac_denorm_rup_add_1 = !fdsu_ex3_result_sign && + (!ex3_denorm_zero || + (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); +assign frac_denorm_rup_sub_1 = fdsu_ex3_result_sign && + (ex3_denorm_zero && fdsu_ex3_rem_sign); +assign frac_denorm_rdn_add_1 = fdsu_ex3_result_sign && + (!ex3_denorm_zero || + (!fdsu_ex3_rem_sign && !fdsu_ex3_rem_zero)); +assign frac_denorm_rdn_sub_1 = !fdsu_ex3_result_sign && + (ex3_denorm_zero && fdsu_ex3_rem_sign); +assign frac_denorm_rmm_add_1 = ex3_denorm_gr || + (ex3_denorm_eq && !fdsu_ex3_rem_sign); + +//RM select +// &CombBeg; @222 +always @( fdsu_ex3_rm[2:0] + or frac_denorm_rdn_add_1 + or frac_rne_add_1 + or frac_denorm_rdn_sub_1 + or fdsu_ex3_result_sign + or frac_rup_add_1 + or frac_denorm_rup_sub_1 + or frac_rdn_sub_1 + or frac_rtz_sub_1 + or frac_rdn_add_1 + or fdsu_ex3_id_srt_skip + or frac_denorm_rtz_sub_1 + or ex3_rslt_denorm + or frac_rup_sub_1 + or frac_denorm_rmm_add_1 + or frac_denorm_rup_add_1 + or frac_denorm_rne_add_1 + or frac_rmm_add_1) +begin +case(fdsu_ex3_rm[2:0]) + 3'b000://round to nearst,ties to even + begin + frac_add_1 = ex3_rslt_denorm ? frac_denorm_rne_add_1 : frac_rne_add_1; + frac_sub_1 = 1'b0; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rne_add_1 : !frac_rne_add_1; + denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rne_add_1; + end + 3'b001:// round to 0 + begin + frac_add_1 = 1'b0; + frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rtz_sub_1 : frac_rtz_sub_1; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rtz_sub_1 : !frac_rtz_sub_1; + denorm_to_tiny_frac = 1'b0; + end + 3'b010://round to -inf + begin + frac_add_1 = ex3_rslt_denorm ? frac_denorm_rdn_add_1 : frac_rdn_add_1; + frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rdn_sub_1 : frac_rdn_sub_1; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rdn_add_1 && !frac_denorm_rdn_sub_1 + : !frac_rdn_add_1 && !frac_rdn_sub_1; + denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? fdsu_ex3_result_sign + : frac_denorm_rdn_add_1; + end + 3'b011://round to +inf + begin + frac_add_1 = ex3_rslt_denorm ? frac_denorm_rup_add_1 : frac_rup_add_1; + frac_sub_1 = ex3_rslt_denorm ? frac_denorm_rup_sub_1 : frac_rup_sub_1; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rup_add_1 && !frac_denorm_rup_sub_1 + : !frac_rup_add_1 && !frac_rup_sub_1; + denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? !fdsu_ex3_result_sign + : frac_denorm_rup_add_1; + end + 3'b100://round to nearest,ties to max magnitude + begin + frac_add_1 = ex3_rslt_denorm ? frac_denorm_rmm_add_1 : frac_rmm_add_1; + frac_sub_1 = 1'b0; + frac_orig = ex3_rslt_denorm ? !frac_denorm_rmm_add_1 : !frac_rmm_add_1; + denorm_to_tiny_frac = fdsu_ex3_id_srt_skip ? 1'b0 : frac_denorm_rmm_add_1; + end + default: + begin + frac_add_1 = 1'b0; + frac_sub_1 = 1'b0; + frac_orig = 1'b0; + denorm_to_tiny_frac = 1'b0; + end +endcase +// &CombEnd; @271 +end +//Add 1 or Sub 1 constant +// &CombBeg; @273 +always @( total_qt_rt_30[28]) +begin +case(total_qt_rt_30[28]) + 1'b0: + begin + frac_add1_op1[25:0] = {2'b0,24'b1}; + frac_sub1_op1[25:0] = {2'b11,{24{1'b1}}}; + end + 1'b1: + begin + frac_add1_op1[25:0] = {25'b1,1'b0}; + frac_sub1_op1[25:0] = {{25{1'b1}},1'b0}; + end + default: + begin + frac_add1_op1[25:0] = 26'b0; + frac_sub1_op1[25:0] = 26'b0; + end +endcase +// &CombEnd; @291 +end + +//Add 1 or Sub1 final result +//Conner case when quotient is 0.010000...00 and remainder is negative, +//The real quotient is actually 0.00fff..ff, +//The final result will need to sub 1 when +//RN : Never occur +//RP : sign of quotient is - +//RM : sign of quotient is + +assign frac_add1_rst[25:0] = {1'b0,total_qt_rt_30[28:4]} + + frac_add1_op1_with_denorm[25:0]; +assign frac_add1_op1_with_denorm[25:0] = ex3_rslt_denorm ? + {1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} : + frac_add1_op1[25:0]; +assign frac_sub1_rst[25:0] = (ex3_rst_eq_1) + ? {3'b0,{23{1'b1}}} + : {1'b0,total_qt_rt_30[28:4]} + + frac_sub1_op1_with_denorm[25:0] + {25'b0, ex3_rslt_denorm}; +assign frac_sub1_op1_with_denorm[25:0] = ex3_rslt_denorm ? + ~{1'b0,fdsu_ex3_result_denorm_round_add_num[23:0],1'b0} : + frac_sub1_op1[25:0]; +assign frac_final_rst[25:0] = (frac_add1_rst[25:0] & {26{frac_add_1}}) | + (frac_sub1_rst[25:0] & {26{frac_sub_1}}) | + ({1'b0,total_qt_rt_30[28:4]} & {26{frac_orig}}); + +//===============Pipe down signal prepare=================== +// assign ex3_rst_nor = !fdsu_ex3_result_zero && +// !fdsu_ex3_result_qnan && +// !fdsu_ex3_result_inf && +// !fdsu_ex3_result_lfn; +assign ex3_rst_nor = !fdsu_ex3_result_inf && + !fdsu_ex3_result_lfn; +assign ex3_nx = ex3_rst_nor && + (!ex3_qt_zero || !fdsu_ex3_rem_zero || ex3_denorm_nx); +assign ex3_denorm_nx = ex3_rslt_denorm && (!ex3_denorm_zero || !fdsu_ex3_rem_zero); +//Adjust expnt +//Div:Actural expnt should plus 1 when op0 is id, sub 1 when op1 id +assign ex3_expnt_adjst[9:0] = 10'h7f; + +assign ex3_expnt_adjust_result[9:0] = fdsu_ex3_expnt_rst[9:0] + + ex3_expnt_adjst[9:0]; +//this information is for the packing, which determin the result is normal +//numer or not; +assign ex3_potnt_norm[1:0] = {ex3_denorm_plus,ex3_denorm_potnt_norm}; +//=======================Pipe to EX4======================== +//gate clk +// &Instance("gated_clk_cell","x_ex3_pipe_clk"); @337 +gated_clk_cell x_ex3_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex3_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex3_pipe_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @338 +// .clk_out (ex3_pipe_clk),//Out Clock @339 +// .external_en (1'b0), @340 +// .global_en (cp0_yy_clk_en), @341 +// .local_en (ex3_pipe_clk_en),//Local Condition @342 +// .module_en (cp0_fpu_icg_en) @343 +// ); @344 +assign ex3_pipe_clk_en = ex3_pipedown; + +always @(posedge ex3_pipe_clk) +begin + if(ex3_pipedown) + begin + fdsu_ex4_result_nor <= ex3_rst_nor; + fdsu_ex4_nx <= ex3_nx; + fdsu_ex4_denorm_to_tiny_frac + <= denorm_to_tiny_frac; + fdsu_ex4_potnt_norm[1:0] <= ex3_potnt_norm[1:0]; + end + else + begin + fdsu_ex4_result_nor <= fdsu_ex4_result_nor; + fdsu_ex4_nx <= fdsu_ex4_nx; + fdsu_ex4_denorm_to_tiny_frac + <= fdsu_ex4_denorm_to_tiny_frac; + fdsu_ex4_potnt_norm[1:0] <= fdsu_ex4_potnt_norm[1:0]; + end +end + +// ex3_frac Pipedown to ex4 use srt_divisor. +assign ex3_frac_final_rst[25:0] = frac_final_rst[25:0]; +// &Force("output","fdsu_ex4_result_nor"); @397 +// &Force("output","fdsu_ex4_nx"); @398 +// &Force("output","fdsu_ex4_denorm_to_tiny_frac"); @399 +// &Force("output","fdsu_ex4_potnt_norm"); @400 + + +// &ModuleEnd; @403 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_special.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_special( + cp0_fpu_xx_dqnan, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_qnan, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + ex1_div, + ex1_op0_id, + ex1_op0_norm, + ex1_op0_sign, + ex1_op1_id, + ex1_op1_norm, + ex1_result_sign, + ex1_sqrt, + ex1_srt_skip, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign +); + +// &Ports; @24 +input cp0_fpu_xx_dqnan; +input [2:0] dp_xx_ex1_cnan; +input [2:0] dp_xx_ex1_id; +input [2:0] dp_xx_ex1_inf; +input [2:0] dp_xx_ex1_qnan; +input [2:0] dp_xx_ex1_snan; +input [2:0] dp_xx_ex1_zero; +input ex1_div; +input ex1_op0_sign; +input ex1_result_sign; +input ex1_sqrt; +output ex1_op0_id; +output ex1_op0_norm; +output ex1_op1_id; +output ex1_op1_norm; +output ex1_srt_skip; +output [4:0] fdsu_fpu_ex1_fflags; +output [7:0] fdsu_fpu_ex1_special_sel; +output [3:0] fdsu_fpu_ex1_special_sign; + +// &Regs; @25 +reg ex1_result_cnan; +reg ex1_result_qnan_op0; +reg ex1_result_qnan_op1; + +// &Wires; @26 +wire cp0_fpu_xx_dqnan; +wire [2:0] dp_xx_ex1_cnan; +wire [2:0] dp_xx_ex1_id; +wire [2:0] dp_xx_ex1_inf; +wire [2:0] dp_xx_ex1_qnan; +wire [2:0] dp_xx_ex1_snan; +wire [2:0] dp_xx_ex1_zero; +wire ex1_div; +wire ex1_div_dz; +wire ex1_div_nv; +wire ex1_div_rst_inf; +wire ex1_div_rst_qnan; +wire ex1_div_rst_zero; +wire ex1_dz; +wire [4:0] ex1_fflags; +wire ex1_nv; +wire ex1_op0_cnan; +wire ex1_op0_id; +wire ex1_op0_inf; +wire ex1_op0_is_qnan; +wire ex1_op0_is_snan; +wire ex1_op0_norm; +wire ex1_op0_qnan; +wire ex1_op0_sign; +wire ex1_op0_snan; +wire ex1_op0_tt_zero; +wire ex1_op0_zero; +wire ex1_op1_cnan; +wire ex1_op1_id; +wire ex1_op1_inf; +wire ex1_op1_is_qnan; +wire ex1_op1_is_snan; +wire ex1_op1_norm; +wire ex1_op1_qnan; +wire ex1_op1_snan; +wire ex1_op1_tt_zero; +wire ex1_op1_zero; +wire ex1_result_inf; +wire ex1_result_lfn; +wire ex1_result_qnan; +wire ex1_result_sign; +wire ex1_result_zero; +wire ex1_rst_default_qnan; +wire [7:0] ex1_special_sel; +wire [3:0] ex1_special_sign; +wire ex1_sqrt; +wire ex1_sqrt_nv; +wire ex1_sqrt_rst_inf; +wire ex1_sqrt_rst_qnan; +wire ex1_sqrt_rst_zero; +wire ex1_srt_skip; +wire [4:0] fdsu_fpu_ex1_fflags; +wire [7:0] fdsu_fpu_ex1_special_sel; +wire [3:0] fdsu_fpu_ex1_special_sign; + + +//infinity number +// &Force("bus", "dp_xx_ex1_inf", 2, 0); @29 +assign ex1_op0_inf = dp_xx_ex1_inf[0]; +assign ex1_op1_inf = dp_xx_ex1_inf[1]; + +//zero +// &Force("bus", "dp_xx_ex1_zero", 2, 0); @34 +assign ex1_op0_zero = dp_xx_ex1_zero[0]; +assign ex1_op1_zero = dp_xx_ex1_zero[1]; + +//denormalize number +// &Force("bus", "dp_xx_ex1_id", 2, 0); @39 +assign ex1_op0_id = dp_xx_ex1_id[0]; +assign ex1_op1_id = dp_xx_ex1_id[1]; + +//cNaN +// &Force("bus", "dp_xx_ex1_cnan", 2, 0); @44 +assign ex1_op0_cnan = dp_xx_ex1_cnan[0]; +assign ex1_op1_cnan = dp_xx_ex1_cnan[1]; + +//sNaN +// &Force("bus", "dp_xx_ex1_snan", 2, 0); @49 +assign ex1_op0_snan = dp_xx_ex1_snan[0]; +assign ex1_op1_snan = dp_xx_ex1_snan[1]; + +//qNaN +// &Force("bus", "dp_xx_ex1_qnan", 2, 0); @54 +assign ex1_op0_qnan = dp_xx_ex1_qnan[0]; +assign ex1_op1_qnan = dp_xx_ex1_qnan[1]; + + +//======================EX1 expt detect===================== +//ex1_id_detect +//any opration is zero +// no input denormalize exception anymore +// +//ex1_nv_detect +//div_nv +// 1.any operation is sNaN +// 2.0/0(include DN flush to zero) +// 3.inf/inf +//sqrt_nv +// 1.any operation is sNaN +// 2.operation sign is 1 && operation is not zero/qNaN +assign ex1_nv = ex1_div && ex1_div_nv || + ex1_sqrt && ex1_sqrt_nv; +//ex1_div_nv +assign ex1_div_nv = ex1_op0_snan || + ex1_op1_snan || + (ex1_op0_tt_zero && ex1_op1_tt_zero)|| + (ex1_op0_inf && ex1_op1_inf); +assign ex1_op0_tt_zero = ex1_op0_zero; +assign ex1_op1_tt_zero = ex1_op1_zero; +//ex1_sqrt_nv +assign ex1_sqrt_nv = ex1_op0_snan || + ex1_op0_sign && + (ex1_op0_norm || + ex1_op0_inf ); + +// This 'norm' also include denorm. +assign ex1_op0_norm = !ex1_op0_inf && !ex1_op0_zero && !ex1_op0_snan && !ex1_op0_qnan && !ex1_op0_cnan; +assign ex1_op1_norm = !ex1_op1_inf && !ex1_op1_zero && !ex1_op1_snan && !ex1_op1_qnan && !ex1_op1_cnan; + +//ex1_of_detect +//div_of +// 1.only detect id overflow case +//assign ex1_of = ex1_div && ex1_div_of; +//assign ex1_div_of = ex1_op1_id_fm1 && +// ex1_op0_norm && +// ex1_div_id_of; +// +////ex1_uf_detect +////div_uf +//// 1.only detect id underflow case +//assign ex1_uf = ex1_div && ex1_div_uf; +//assign ex1_div_uf = ex1_op0_id && +// ex1_op1_norm && +// ex1_div_id_uf; +//ex1_dz_detect +//div_dz +// 1.op0 is normal && op1 zero +assign ex1_dz = ex1_div && ex1_div_dz; +assign ex1_div_dz = ex1_op1_tt_zero && ex1_op0_norm; + +//===================special cal result===================== +//ex1 result is zero +//div_zero +// 1.op0 is zero && op1 is normal +// 2.op0 is zero/normal && op1 is inf +//sqrt_zero +// 1.op0 is zero +assign ex1_result_zero = ex1_div_rst_zero && ex1_div || + ex1_sqrt_rst_zero && ex1_sqrt; +assign ex1_div_rst_zero = (ex1_op0_tt_zero && ex1_op1_norm ) || + // (!ex1_expnt0_max && !ex1_op0_cnan && ex1_op1_inf); + (!ex1_op0_inf && !ex1_op0_qnan && !ex1_op0_snan && !ex1_op0_cnan && ex1_op1_inf); +assign ex1_sqrt_rst_zero = ex1_op0_tt_zero; + +//ex1 result is qNaN +//ex1_nv +//div_qnan +// 1.op0 is qnan || op1 is qnan +//sqrt_qnan +// 1.op0 is qnan +assign ex1_result_qnan = ex1_div_rst_qnan && ex1_div || + ex1_sqrt_rst_qnan && ex1_sqrt || + ex1_nv; +assign ex1_div_rst_qnan = ex1_op0_qnan || + ex1_op1_qnan; +assign ex1_sqrt_rst_qnan = ex1_op0_qnan; + +//ex1_rst_default_qnan +//0/0, inf/inf, sqrt negative should get default qNaN +assign ex1_rst_default_qnan = (ex1_div && ex1_op0_zero && ex1_op1_zero) || + (ex1_div && ex1_op0_inf && ex1_op1_inf) || + (ex1_sqrt&& ex1_op0_sign && (ex1_op0_norm || ex1_op0_inf)); + +//ex1 result is inf +//ex1_dz +// +//div_inf +// 1.op0 is inf && op1 is normal/zero +//sqrt_inf +// 1.op0 is inf +assign ex1_result_inf = ex1_div_rst_inf && ex1_div || + ex1_sqrt_rst_inf && ex1_sqrt || + ex1_dz ; +// assign ex1_div_rst_inf = ex1_op0_inf && !ex1_expnt1_max && !ex1_op1_cnan; +assign ex1_div_rst_inf = ex1_op0_inf && !ex1_op1_inf && !ex1_op1_qnan && !ex1_op1_snan && !ex1_op1_cnan; +assign ex1_sqrt_rst_inf = ex1_op0_inf && !ex1_op0_sign; + +//ex1 result is lfn +//ex1_of && round result toward not inc 1 +assign ex1_result_lfn = 1'b0; + +//Default_qnan/Standard_qnan Select +assign ex1_op0_is_snan = ex1_op0_snan; +assign ex1_op1_is_snan = ex1_op1_snan && ex1_div; +assign ex1_op0_is_qnan = ex1_op0_qnan; +assign ex1_op1_is_qnan = ex1_op1_qnan && ex1_div; + +// &CombBeg; @169 +always @( ex1_op0_is_snan + or ex1_op0_cnan + or ex1_result_qnan + or ex1_op0_is_qnan + or ex1_rst_default_qnan + or cp0_fpu_xx_dqnan + or ex1_op1_cnan + or ex1_op1_is_qnan + or ex1_op1_is_snan) +begin +if(ex1_rst_default_qnan) +begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan; +end +else if(ex1_op0_is_snan && cp0_fpu_xx_dqnan) +begin + ex1_result_qnan_op0 = ex1_result_qnan; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = 1'b0; +end +else if(ex1_op1_is_snan && cp0_fpu_xx_dqnan) +begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = ex1_result_qnan; + ex1_result_cnan = 1'b0; +end +else if(ex1_op0_is_qnan && cp0_fpu_xx_dqnan) +begin + ex1_result_qnan_op0 = ex1_result_qnan && !ex1_op0_cnan; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan && ex1_op0_cnan; +end +else if(ex1_op1_is_qnan && cp0_fpu_xx_dqnan) +begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = ex1_result_qnan && !ex1_op1_cnan; + ex1_result_cnan = ex1_result_qnan && ex1_op1_cnan; +end +else +begin + ex1_result_qnan_op0 = 1'b0; + ex1_result_qnan_op1 = 1'b0; + ex1_result_cnan = ex1_result_qnan; +end +// &CombEnd; @206 +end + + +//Special result should skip SRT logic +assign ex1_srt_skip = ex1_result_zero || + ex1_result_qnan || + ex1_result_lfn || + ex1_result_inf; +// fflags: +// NV, DZ, OF, UF, NX +assign ex1_fflags[4:0] = {ex1_nv, ex1_dz, 3'b0}; +// Special Sel[7:0]: +// qnan_src2, qnan_src1, qnan_src0, cnan, lfn, inf, zero, src2 +assign ex1_special_sel[7:0] = {1'b0, ex1_result_qnan_op1, ex1_result_qnan_op0, + ex1_result_cnan, ex1_result_lfn, ex1_result_inf, + ex1_result_zero, 1'b0}; +// Special Sign[3:0] +// lfn, inf, zero, src2 +assign ex1_special_sign[3:0] = {ex1_result_sign, ex1_result_sign, ex1_result_sign, 1'b0}; + +//========================================================== +// Output Signal +//========================================================== +assign fdsu_fpu_ex1_fflags[4:0] = ex1_fflags[4:0]; +assign fdsu_fpu_ex1_special_sel[7:0] = ex1_special_sel[7:0]; +assign fdsu_fpu_ex1_special_sign[3:0] = ex1_special_sign[3:0]; + +// &Force("output", "ex1_op0_norm"); @233 +// &Force("output", "ex1_op1_norm"); @234 + +// &ModuleEnd; @236 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_srt_single.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_srt_single( + cp0_fpu_icg_en, + cp0_yy_clk_en, + ex1_divisor, + ex1_expnt_adder_op1, + ex1_oper_id_frac, + ex1_oper_id_frac_f, + ex1_pipedown, + ex1_pipedown_gate, + ex1_remainder, + ex1_save_op0, + ex1_save_op0_gate, + ex2_expnt_adder_op0, + ex2_of, + ex2_pipe_clk, + ex2_pipedown, + ex2_potnt_of, + ex2_potnt_uf, + ex2_result_inf, + ex2_result_lfn, + ex2_rslt_denorm, + ex2_srt_expnt_rst, + ex2_srt_first_round, + ex2_uf, + ex2_uf_srt_skip, + ex3_frac_final_rst, + ex3_pipedown, + fdsu_ex3_id_srt_skip, + fdsu_ex3_rem_sign, + fdsu_ex3_rem_zero, + fdsu_ex3_result_denorm_round_add_num, + fdsu_ex4_frac, + fdsu_yy_div, + fdsu_yy_of_rm_lfn, + fdsu_yy_op0_norm, + fdsu_yy_op1_norm, + fdsu_yy_sqrt, + forever_cpuclk, + pad_yy_icg_scan_en, + srt_remainder_zero, + srt_sm_on, + total_qt_rt_30 +); + +// &Ports; @24 +input cp0_fpu_icg_en; +input cp0_yy_clk_en; +input [23:0] ex1_divisor; +input [12:0] ex1_expnt_adder_op1; +input [51:0] ex1_oper_id_frac; +input ex1_pipedown; +input ex1_pipedown_gate; +input [31:0] ex1_remainder; +input ex1_save_op0; +input ex1_save_op0_gate; +input [9 :0] ex2_expnt_adder_op0; +input ex2_pipe_clk; +input ex2_pipedown; +input ex2_srt_first_round; +input [25:0] ex3_frac_final_rst; +input ex3_pipedown; +input fdsu_yy_div; +input fdsu_yy_of_rm_lfn; +input fdsu_yy_op0_norm; +input fdsu_yy_op1_norm; +input fdsu_yy_sqrt; +input forever_cpuclk; +input pad_yy_icg_scan_en; +input srt_sm_on; +output [51:0] ex1_oper_id_frac_f; +output ex2_of; +output ex2_potnt_of; +output ex2_potnt_uf; +output ex2_result_inf; +output ex2_result_lfn; +output ex2_rslt_denorm; +output [9 :0] ex2_srt_expnt_rst; +output ex2_uf; +output ex2_uf_srt_skip; +output fdsu_ex3_id_srt_skip; +output fdsu_ex3_rem_sign; +output fdsu_ex3_rem_zero; +output [23:0] fdsu_ex3_result_denorm_round_add_num; +output [25:0] fdsu_ex4_frac; +output srt_remainder_zero; +output [29:0] total_qt_rt_30; + +// &Regs; @25 +reg [31:0] cur_rem; +reg [7 :0] digit_bound_1; +reg [7 :0] digit_bound_2; +reg [23:0] ex2_result_denorm_round_add_num; +reg fdsu_ex3_id_srt_skip; +reg fdsu_ex3_rem_sign; +reg fdsu_ex3_rem_zero; +reg [23:0] fdsu_ex3_result_denorm_round_add_num; +reg [29:0] qt_rt_const_shift_std; +reg [7 :0] qtrt_sel_rem; +reg [31:0] rem_add1_op1; +reg [31:0] rem_add2_op1; +reg [25:0] srt_divisor; +reg [31:0] srt_remainder; +reg [29:0] total_qt_rt_30; +reg [29:0] total_qt_rt_30_next; +reg [29:0] total_qt_rt_minus_30; +reg [29:0] total_qt_rt_minus_30_next; + +// &Wires; @26 +wire [7 :0] bound1_cmp_result; +wire bound1_cmp_sign; +wire [7 :0] bound2_cmp_result; +wire bound2_cmp_sign; +wire [3 :0] bound_sel; +wire cp0_fpu_icg_en; +wire cp0_yy_clk_en; +wire [31:0] cur_doub_rem_1; +wire [31:0] cur_doub_rem_2; +wire [31:0] cur_rem_1; +wire [31:0] cur_rem_2; +wire [31:0] div_qt_1_rem_add_op1; +wire [31:0] div_qt_2_rem_add_op1; +wire [31:0] div_qt_r1_rem_add_op1; +wire [31:0] div_qt_r2_rem_add_op1; +wire [23:0] ex1_divisor; +wire ex1_ex2_pipe_clk; +wire ex1_ex2_pipe_clk_en; +wire [12:0] ex1_expnt_adder_op1; +wire [51:0] ex1_oper_id_frac; +wire [51:0] ex1_oper_id_frac_f; +wire ex1_pipedown; +wire ex1_pipedown_gate; +wire [31:0] ex1_remainder; +wire ex1_save_op0; +wire ex1_save_op0_gate; +wire ex2_div_of; +wire ex2_div_uf; +wire [9 :0] ex2_expnt_adder_op0; +wire [9 :0] ex2_expnt_adder_op1; +wire ex2_expnt_of; +wire [9 :0] ex2_expnt_result; +wire ex2_expnt_uf; +wire ex2_id_nor_srt_skip; +wire ex2_of; +wire ex2_of_plus; +wire ex2_pipe_clk; +wire ex2_pipedown; +wire ex2_potnt_of; +wire ex2_potnt_of_pre; +wire ex2_potnt_uf; +wire ex2_potnt_uf_pre; +wire ex2_result_inf; +wire ex2_result_lfn; +wire ex2_rslt_denorm; +wire [9 :0] ex2_sqrt_expnt_result; +wire [9 :0] ex2_srt_expnt_rst; +wire ex2_srt_first_round; +wire ex2_uf; +wire ex2_uf_plus; +wire ex2_uf_srt_skip; +wire [25:0] ex3_frac_final_rst; +wire ex3_pipedown; +wire fdsu_ex2_div; +wire [9 :0] fdsu_ex2_expnt_rst; +wire fdsu_ex2_of_rm_lfn; +wire fdsu_ex2_op0_norm; +wire fdsu_ex2_op1_norm; +wire fdsu_ex2_result_lfn; +wire fdsu_ex2_sqrt; +wire [25:0] fdsu_ex4_frac; +wire fdsu_yy_div; +wire fdsu_yy_of_rm_lfn; +wire fdsu_yy_op0_norm; +wire fdsu_yy_op1_norm; +wire fdsu_yy_sqrt; +wire forever_cpuclk; +wire pad_yy_icg_scan_en; +wire qt_clk; +wire qt_clk_en; +wire [29:0] qt_rt_const_pre_sel_q1; +wire [29:0] qt_rt_const_pre_sel_q2; +wire [29:0] qt_rt_const_q1; +wire [29:0] qt_rt_const_q2; +wire [29:0] qt_rt_const_q3; +wire [29:0] qt_rt_const_shift_std_next; +wire [29:0] qt_rt_mins_const_pre_sel_q1; +wire [29:0] qt_rt_mins_const_pre_sel_q2; +wire rem_sign; +wire [31:0] sqrt_qt_1_rem_add_op1; +wire [31:0] sqrt_qt_2_rem_add_op1; +wire [31:0] sqrt_qt_r1_rem_add_op1; +wire [31:0] sqrt_qt_r2_rem_add_op1; +wire srt_div_clk; +wire srt_div_clk_en; +wire [31:0] srt_remainder_nxt; +wire [31:0] srt_remainder_shift; +wire srt_remainder_sign; +wire srt_remainder_zero; +wire srt_sm_on; +wire [29:0] total_qt_rt_pre_sel; + + +assign fdsu_ex2_div = fdsu_yy_div; +assign fdsu_ex2_sqrt = fdsu_yy_sqrt; +assign fdsu_ex2_op0_norm = fdsu_yy_op0_norm; +assign fdsu_ex2_op1_norm = fdsu_yy_op1_norm; +assign fdsu_ex2_of_rm_lfn = fdsu_yy_of_rm_lfn; +assign fdsu_ex2_result_lfn = 1'b0; + +//========================================================== +// EX2 Expnt Generate +//========================================================== +//expnt0 sub expnt1 +assign ex2_expnt_result[9:0] = ex2_expnt_adder_op0[9:0] - + ex2_expnt_adder_op1[9:0]; + +//===================sqrt exponent prepare================== +//sqrt exponent prepare +//afert E sub, div E by 2 +assign ex2_sqrt_expnt_result[9:0] = {ex2_expnt_result[9], + ex2_expnt_result[9:1]}; + +assign ex2_srt_expnt_rst[9:0] = (fdsu_ex2_sqrt) + ? ex2_sqrt_expnt_result[9:0] + : ex2_expnt_result[9:0]; +// &Force("output", "ex2_srt_expnt_rst"); &Force("bus", "ex2_srt_expnt_rst", 9, 0); @51 +assign fdsu_ex2_expnt_rst[9:0] = ex2_srt_expnt_rst[9:0]; + + +//====================EX2 Expt info========================= +//EX1 only detect of/uf under id condition +//EX2 will deal with other condition + +//When input is normal, overflow when E1-E2 > 128/1024 +assign ex2_expnt_of = ~fdsu_ex2_expnt_rst[9] && (fdsu_ex2_expnt_rst[8] + || (fdsu_ex2_expnt_rst[7] && + |fdsu_ex2_expnt_rst[6:0])); +//potential overflow when E1-E2 = 128/1024 +assign ex2_potnt_of_pre = ~fdsu_ex2_expnt_rst[9] && + ~fdsu_ex2_expnt_rst[8] && + fdsu_ex2_expnt_rst[7] && + ~|fdsu_ex2_expnt_rst[6:0]; +assign ex2_potnt_of = ex2_potnt_of_pre && + fdsu_ex2_op0_norm && + fdsu_ex2_op1_norm && + fdsu_ex2_div; + +//When input is normal, underflow when E1-E2 <= -127/-1023 +assign ex2_expnt_uf = fdsu_ex2_expnt_rst[9] &&(fdsu_ex2_expnt_rst[8:0] <= 9'h181); +//potential underflow when E1-E2 = -126/-1022 +assign ex2_potnt_uf_pre = &fdsu_ex2_expnt_rst[9:7] && + ~|fdsu_ex2_expnt_rst[6:2] && + fdsu_ex2_expnt_rst[1] && + !fdsu_ex2_expnt_rst[0]; +assign ex2_potnt_uf = (ex2_potnt_uf_pre && + fdsu_ex2_op0_norm && + fdsu_ex2_op1_norm && + fdsu_ex2_div) || + (ex2_potnt_uf_pre && + fdsu_ex2_op0_norm); + +//========================EX2 Overflow====================== +//ex2 overflow when +// 1.op0 & op1 both norm && expnt overflow +// 2.ex1_id_of +// &Force("output","ex2_of"); @91 +assign ex2_of = ex2_of_plus; +assign ex2_of_plus = ex2_div_of && fdsu_ex2_div; +assign ex2_div_of = fdsu_ex2_op0_norm && + fdsu_ex2_op1_norm && + ex2_expnt_of; + +//=======================EX2 Underflow====================== +//ex2 underflow when +// 1.op0 & op1 both norm && expnt underflow +// 2.ex1_id_uf +// and detect when to skip the srt, here, we have further optmization +assign ex2_uf = ex2_uf_plus; +assign ex2_uf_plus = ex2_div_uf && fdsu_ex2_div; +assign ex2_div_uf = fdsu_ex2_op0_norm && + fdsu_ex2_op1_norm && + ex2_expnt_uf; +assign ex2_id_nor_srt_skip = fdsu_ex2_expnt_rst[9] + && (fdsu_ex2_expnt_rst[8:0]<9'h16a); +assign ex2_uf_srt_skip = ex2_id_nor_srt_skip; +assign ex2_rslt_denorm = ex2_uf; +//===============ex2 round prepare for denormal round====== +// &CombBeg; @113 +always @( fdsu_ex2_expnt_rst[9:0]) +begin +case(fdsu_ex2_expnt_rst[9:0]) + 10'h382:ex2_result_denorm_round_add_num[23:0] = 24'h1; //-126 1 + 10'h381:ex2_result_denorm_round_add_num[23:0] = 24'h2; //-127 0 + 10'h380:ex2_result_denorm_round_add_num[23:0] = 24'h4; //-128 -1 + 10'h37f:ex2_result_denorm_round_add_num[23:0] = 24'h8; //-129 -2 + 10'h37e:ex2_result_denorm_round_add_num[23:0] = 24'h10; //-130 -3 + 10'h37d:ex2_result_denorm_round_add_num[23:0] = 24'h20; //-131 -4 + 10'h37c:ex2_result_denorm_round_add_num[23:0] = 24'h40; //-132 -5 + 10'h37b:ex2_result_denorm_round_add_num[23:0] = 24'h80; //-133 -6 + 10'h37a:ex2_result_denorm_round_add_num[23:0] = 24'h100; //-134 -7 + 10'h379:ex2_result_denorm_round_add_num[23:0] = 24'h200; //-135 -8 + 10'h378:ex2_result_denorm_round_add_num[23:0] = 24'h400; //-136 -9 + 10'h377:ex2_result_denorm_round_add_num[23:0] = 24'h800; //-137 -10 + 10'h376:ex2_result_denorm_round_add_num[23:0] = 24'h1000; //-138 -11 + 10'h375:ex2_result_denorm_round_add_num[23:0] = 24'h2000; //-139 -12 + 10'h374:ex2_result_denorm_round_add_num[23:0] = 24'h4000; //-140 -13 + 10'h373:ex2_result_denorm_round_add_num[23:0] = 24'h8000; // -141 -14 + 10'h372:ex2_result_denorm_round_add_num[23:0] = 24'h10000;//-142 -15 + 10'h371:ex2_result_denorm_round_add_num[23:0] = 24'h20000;//-143 -16 + 10'h370:ex2_result_denorm_round_add_num[23:0] = 24'h40000; //-144 -17 + 10'h36f:ex2_result_denorm_round_add_num[23:0] = 24'h80000; //-145 -18 + 10'h36e:ex2_result_denorm_round_add_num[23:0] = 24'h100000; //-146 -19 + 10'h36d:ex2_result_denorm_round_add_num[23:0] = 24'h200000; //-147 -20 + 10'h36c:ex2_result_denorm_round_add_num[23:0] = 24'h400000; //-148 -21 + 10'h36b:ex2_result_denorm_round_add_num[23:0] = 24'h800000; //-148 -22 + default: ex2_result_denorm_round_add_num[23:0] = 24'h0; // -23 +endcase +// &CombEnd; @141 +end + +//===================special result======================== +assign ex2_result_inf = ex2_of_plus && !fdsu_ex2_of_rm_lfn; +assign ex2_result_lfn = fdsu_ex2_result_lfn || + ex2_of_plus && fdsu_ex2_of_rm_lfn; + + + +//====================Pipe to EX3=========================== +always @(posedge ex1_ex2_pipe_clk) +begin + if(ex1_pipedown) + begin + fdsu_ex3_result_denorm_round_add_num[23:0] + <= {14'b0, ex1_expnt_adder_op1[9:0]}; + end + else if(ex2_pipedown) + begin + fdsu_ex3_result_denorm_round_add_num[23:0] + <= ex2_result_denorm_round_add_num[23:0]; + end + else + begin + fdsu_ex3_result_denorm_round_add_num[23:0] + <= fdsu_ex3_result_denorm_round_add_num[23:0]; + end +end +assign ex2_expnt_adder_op1 = fdsu_ex3_result_denorm_round_add_num[9:0]; +// &Force("bus", "ex1_expnt_adder_op1", 12, 0); @193 + +assign ex1_ex2_pipe_clk_en = ex1_pipedown_gate || ex2_pipedown; +// &Instance("gated_clk_cell", "x_ex1_ex2_pipe_clk"); @196 +gated_clk_cell x_ex1_ex2_pipe_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex1_ex2_pipe_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex1_ex2_pipe_clk_en), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ) +); + +// &Connect(.clk_in (forever_cpuclk), @197 +// .external_en (1'b0), @198 +// .global_en (cp0_yy_clk_en), @199 +// .module_en (cp0_fpu_icg_en), @200 +// .local_en (ex1_ex2_pipe_clk_en), @201 +// .clk_out (ex1_ex2_pipe_clk)); @202 + +always @(posedge ex2_pipe_clk) +begin + if(ex2_pipedown) + begin + fdsu_ex3_rem_sign <= srt_remainder_sign; + fdsu_ex3_rem_zero <= srt_remainder_zero; + fdsu_ex3_id_srt_skip <= ex2_id_nor_srt_skip; + end + else + begin + fdsu_ex3_rem_sign <= fdsu_ex3_rem_sign; + fdsu_ex3_rem_zero <= fdsu_ex3_rem_zero; + fdsu_ex3_id_srt_skip <= fdsu_ex3_id_srt_skip; + end +end + +// &Force("output","fdsu_ex3_rem_sign"); @243 +// &Force("output","fdsu_ex3_rem_zero"); @244 +// &Force("output","fdsu_ex3_result_denorm_round_add_num"); @245 +// &Force("output","fdsu_ex3_id_srt_skip"); @246 + +//========================================================== +// SRT Remainder & Divisor for Quotient/Root Generate +//========================================================== + +//===================Remainder Generate===================== +//gate clk +// &Instance("gated_clk_cell","x_srt_rem_clk"); +// // &Connect( .clk_in (forever_cpuclk), @255 +// // .clk_out (srt_rem_clk),//Out Clock @256 +// // .external_en (1'b0), @257 +// // .global_en (cp0_yy_clk_en), @258 +// // .local_en (srt_rem_clk_en),//Local Condition @259 +// // .module_en (cp0_fpu_icg_en) @260 +// // ); @261 +// assign srt_rem_clk_en = ex1_pipedown || +// srt_sm_on; + +always @(posedge qt_clk) +begin + if (ex1_pipedown) + srt_remainder[31:0] <= ex1_remainder[31:0]; + else if (srt_sm_on) + srt_remainder[31:0] <= srt_remainder_nxt[31:0]; + else + srt_remainder[31:0] <= srt_remainder[31:0]; +end + +//=====================Divisor Generate===================== +//gate clk +// &Instance("gated_clk_cell","x_srt_div_clk"); @291 +gated_clk_cell x_srt_div_clk ( + .clk_in (forever_cpuclk ), + .clk_out (srt_div_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (srt_div_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @292 +// .clk_out (srt_div_clk),//Out Clock @293 +// .external_en (1'b0), @294 +// .global_en (cp0_yy_clk_en), @295 +// .local_en (srt_div_clk_en),//Local Condition @296 +// .module_en (cp0_fpu_icg_en) @297 +// ); @298 +assign srt_div_clk_en = ex1_pipedown_gate + || ex1_save_op0_gate + || ex3_pipedown; +// final_rst saved in srt_divisor. +// srt_divisor is 26 bits, final_rst is 24 bits. +always @(posedge srt_div_clk) +begin + if (ex1_save_op0) + srt_divisor[25:0] <= {3'b0, {ex1_oper_id_frac[51:29]}}; + else if (ex1_pipedown) + srt_divisor[25:0] <= {2'b0, ex1_divisor[23:0]}; + else if (ex3_pipedown) + srt_divisor[25:0] <= ex3_frac_final_rst[25:0]; + else + srt_divisor[25:0] <= srt_divisor[25:0]; +end +assign ex1_oper_id_frac_f[51:0] = {srt_divisor[22:0], 29'b0}; +// &Force("bus", "ex1_oper_id_frac", 51, 0); @332 +assign fdsu_ex4_frac[25:0] = srt_divisor[25:0]; + +//=======================Bound Select======================= +//---------------------------------------+ +// K | 8 | 9 | 10| 11| 12| 13| 14|15,16| +//---------------------------------------+ +//32S1 | 7 | 7 | 8 | 9 | 9 | 10| 11| 12 | +//---------------------------------------+ +//32S2 | 25| 28| 31| 33| 36| 39| 41| 47 | +//---------------------------------------+ + +//bound_sel[3:0] +//For div, use divisor high four bit as K +//For sqrt, use 2qi high four bit as K next round and +// use 1010 as K first round +assign bound_sel[3:0] = (fdsu_ex2_div) + ? srt_divisor[23:20] + : (ex2_srt_first_round) + ? 4'b1010 + : total_qt_rt_30[28:25]; +//Select bound as look up table +// K = bound_sel[3:0] +//32S1 = digit_bound_1[7:0] +//32s2 = digit_bound_2[7:0] +// &CombBeg; @357 +always @( bound_sel[3:0]) +begin +case(bound_sel[3:0]) +4'b0000: //when first interation get "10", choose k=16 + begin + digit_bound_1[7:0] = 8'b11110100;//-12 + digit_bound_2[7:0] = 8'b11010001;//-47 + end +4'b1000: + begin + digit_bound_1[7:0] = 8'b11111001;//-7 + digit_bound_2[7:0] = 8'b11100111;//-25 + end +4'b1001: + begin + digit_bound_1[7:0] = 8'b11111001;//-7 + digit_bound_2[7:0] = 8'b11100100;//-28 + end +4'b1010: + begin + digit_bound_1[7:0] = 8'b11111000;//-8 + digit_bound_2[7:0] = 8'b11100001;//-31 + end +4'b1011: + begin + digit_bound_1[7:0] = 8'b11110111;//-9 + digit_bound_2[7:0] = 8'b11011111;//-33 + end +4'b1100: + begin + digit_bound_1[7:0] = 8'b11110111;//-9 + digit_bound_2[7:0] = 8'b11011100;//-36 + end +4'b1101: + begin + digit_bound_1[7:0] = 8'b11110110;//-10 + digit_bound_2[7:0] = 8'b11011001;//-39 + end +4'b1110: + begin + digit_bound_1[7:0] = 8'b11110101;//-11 + digit_bound_2[7:0] = 8'b11010111;//-41 + end +4'b1111: + begin + digit_bound_1[7:0] = 8'b11110100;//-12 + digit_bound_2[7:0] = 8'b11010001;//-47 + end +default: + begin + digit_bound_1[7:0] = 8'b11111001;//-7 + digit_bound_2[7:0] = 8'b11100111;//-25 + end +endcase +// &CombEnd; @410 +end + +//==============Prepare for quotient generate=============== +assign bound1_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_1[7:0]; +assign bound2_cmp_result[7:0] = qtrt_sel_rem[7:0] + digit_bound_2[7:0]; +assign bound1_cmp_sign = bound1_cmp_result[7]; +assign bound2_cmp_sign = bound2_cmp_result[7]; +assign rem_sign = srt_remainder[29]; + +//qtrt_sel_rem is use to select quotient +//Only when sqrt first round use 8R0 select quotient(special rule) +//4R0 is used to select quotient on other condition +//For negative remaider, we use ~rem not (~rem + 1) +//Because bound1 <= rem < bound2, when positive rem +// -bound2 <= rem < -bound1, when negative rem +//Thus bound1 < -rem <= bound2, when negative rem +//Thus bound1 <= -rem-1 < bound2, when negative rem +//Thus bound1 <= ~rem < bound2, when negative rem +//srt_remainder[29] used as sign bit +// &CombBeg; @429 +always @( ex2_srt_first_round + or fdsu_ex2_sqrt + or srt_remainder[29:21]) +begin +if(ex2_srt_first_round && fdsu_ex2_sqrt) + qtrt_sel_rem[7:0] = {srt_remainder[29], srt_remainder[27:21]}; +else + qtrt_sel_rem[7:0] = srt_remainder[29] ? ~srt_remainder[29:22] + : srt_remainder[29:22]; +// &CombEnd; @435 +end + +//========================================================== +// on fly round method to generate total quotient +//========================================================== +//gate clk +// &Instance("gated_clk_cell","x_qt_clk"); @441 +gated_clk_cell x_qt_clk ( + .clk_in (forever_cpuclk ), + .clk_out (qt_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (qt_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +// &Connect( .clk_in (forever_cpuclk), @442 +// .clk_out (qt_clk),//Out Clock @443 +// .external_en (1'b0), @444 +// .global_en (cp0_yy_clk_en), @445 +// .local_en (qt_clk_en),//Local Condition @446 +// .module_en (cp0_fpu_icg_en) @447 +// ); @448 +assign qt_clk_en = srt_sm_on || + ex1_pipedown_gate; + +//qt_rt_const_shift_std[29:0] is const data for on fly round +// which is used to record the times of round +// +//total_qt_rt[29:0] is total quotient +//total_qt_rt_minus[29:0] is total quotient minus +// which is used to generate quotient rapidly +always @(posedge qt_clk) +begin + if(ex1_pipedown) + begin + qt_rt_const_shift_std[29:0] <= {1'b0,1'b1,28'b0}; + total_qt_rt_30[29:0] <= 30'b0; + total_qt_rt_minus_30[29:0] <= 30'b0; + end + else if(srt_sm_on) + begin + qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std_next[29:0]; + total_qt_rt_30[29:0] <= total_qt_rt_30_next[29:0]; + total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30_next[29:0]; + end + else + begin + qt_rt_const_shift_std[29:0] <= qt_rt_const_shift_std[29:0]; + total_qt_rt_30[29:0] <= total_qt_rt_30[29:0]; + total_qt_rt_minus_30[29:0] <= total_qt_rt_minus_30[29:0]; + end +end +// &Force("output","total_qt_rt_30"); @508 + +//qt_rt_const_q1/q2/q3 for shift 1/2/3 in +assign qt_rt_const_q1[29:0] = qt_rt_const_shift_std[29:0]; +assign qt_rt_const_q2[29:0] = {qt_rt_const_shift_std[28:0],1'b0}; +assign qt_rt_const_q3[29:0] = qt_rt_const_q1[29:0] | + qt_rt_const_q2[29:0]; +//qt_rt_const update value +assign qt_rt_const_shift_std_next[29:0] = {2'b0, qt_rt_const_shift_std[29:2]}; + +//========total_qt_rt & total_qt_rt_minus update value====== +//q(i+1) is the total quotient/root after the (i+1) digit +//is calculated +// q(i+1) qm(i+1) +//d(i+1)=-2 qm(i)+2*shift qm(i)+1*shift +//d(i+1)=-1 qm(i)+3*shift qm(i)+2*shift +//d(i+1)=0 q(i) qm(i)+3*shift +//d(i+1)=1 q(i)+1*shift q(i) +//d(i+1)=2 q(i)+2*shift q(i)+1*shift +//Note: +//shift = 4^(-i-1), qm(i+1)=q(i+1)-shift + +//pre select for quotient +assign total_qt_rt_pre_sel[29:0] = (rem_sign) ? + total_qt_rt_minus_30[29:0] : + total_qt_rt_30[29:0]; +//when the quotient is 2 or -2 +assign qt_rt_const_pre_sel_q2[29:0] = qt_rt_const_q2[29:0]; +assign qt_rt_mins_const_pre_sel_q2[29:0] = qt_rt_const_q1[29:0]; +//when the quotient is 1 or -1 +assign qt_rt_const_pre_sel_q1[29:0] = (rem_sign) ? + qt_rt_const_q3[29:0] ://-1 + qt_rt_const_q1[29:0]; //1 +assign qt_rt_mins_const_pre_sel_q1[29:0] = (rem_sign) ? + qt_rt_const_q2[29:0] : //-1 + 30'b0; + +//After bound compare, the final selection +// &CombBeg; @546 +always @( qt_rt_const_q3[29:0] + or qt_rt_mins_const_pre_sel_q1[29:0] + or bound1_cmp_sign + or total_qt_rt_30[29:0] + or qt_rt_mins_const_pre_sel_q2[29:0] + or total_qt_rt_minus_30[29:0] + or bound2_cmp_sign + or qt_rt_const_pre_sel_q2[29:0] + or qt_rt_const_pre_sel_q1[29:0] + or total_qt_rt_pre_sel[29:0]) +begin +casez({bound1_cmp_sign,bound2_cmp_sign}) + 2'b00:// the quotient is -2 or 2 + begin + total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | + qt_rt_const_pre_sel_q2[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | + qt_rt_mins_const_pre_sel_q2[29:0]; + end + 2'b01:// quotient is -1 or 1 + begin + total_qt_rt_30_next[29:0] = total_qt_rt_pre_sel[29:0] | + qt_rt_const_pre_sel_q1[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_pre_sel[29:0] | + qt_rt_mins_const_pre_sel_q1[29:0]; + end + 2'b1?: // quotient is 0 + begin + total_qt_rt_30_next[29:0] = total_qt_rt_30[29:0]; + total_qt_rt_minus_30_next[29:0] = total_qt_rt_minus_30[29:0] | + qt_rt_const_q3[29:0]; + end + default: + begin + total_qt_rt_30_next[29:0] = 30'b0; + total_qt_rt_minus_30_next[29:0] = 30'b0; + end +endcase +// &CombEnd; @574 +end + +//========================================================== +// on fly round method to generate cur remainder +//========================================================== +//Division emainder add value +//Quoit 1 +assign div_qt_1_rem_add_op1[31:0] = ~{3'b0,srt_divisor[23:0],5'b0}; +//Quoit 2 +assign div_qt_2_rem_add_op1[31:0] = ~{2'b0,srt_divisor[23:0],6'b0}; +//Quoit -1 +assign div_qt_r1_rem_add_op1[31:0] = {3'b0,srt_divisor[23:0],5'b0}; +//Quoit -2 +assign div_qt_r2_rem_add_op1[31:0] = {2'b0,srt_divisor[23:0],6'b0}; + +//Sqrt remainder add value op1 +//Quoit 1 +assign sqrt_qt_1_rem_add_op1[31:0] = ~({2'b0,total_qt_rt_30[29:0]} | + {3'b0,qt_rt_const_q1[29:1]}); +//Quoit 2 +assign sqrt_qt_2_rem_add_op1[31:0] = ~({1'b0,total_qt_rt_30[29:0],1'b0} | + {1'b0,qt_rt_const_q1[29:0],1'b0}); +//Quoit -1 +assign sqrt_qt_r1_rem_add_op1[31:0] = {2'b0,total_qt_rt_minus_30[29:0]} | + {1'b0,qt_rt_const_q1[29:0],1'b0} | + {2'b0,qt_rt_const_q1[29:0]} | + {3'b0,qt_rt_const_q1[29:1]}; +//Quoit -2 +assign sqrt_qt_r2_rem_add_op1[31:0] = {1'b0, + total_qt_rt_minus_30[29:0],1'b0} | + {qt_rt_const_q1[29:0],2'b0} | + {1'b0,qt_rt_const_q1[29:0],1'b0}; +//Remainder Adder select logic +// &CombBeg; @607 +always @( div_qt_2_rem_add_op1[31:0] + or sqrt_qt_r2_rem_add_op1[31:0] + or sqrt_qt_r1_rem_add_op1[31:0] + or rem_sign + or div_qt_r2_rem_add_op1[31:0] + or div_qt_1_rem_add_op1[31:0] + or sqrt_qt_2_rem_add_op1[31:0] + or fdsu_ex2_sqrt + or div_qt_r1_rem_add_op1[31:0] + or sqrt_qt_1_rem_add_op1[31:0]) +begin +case({rem_sign,fdsu_ex2_sqrt}) + 2'b01: + begin + rem_add1_op1[31:0] = sqrt_qt_1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = sqrt_qt_2_rem_add_op1[31:0]; + end + 2'b00: + begin + rem_add1_op1[31:0] = div_qt_1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = div_qt_2_rem_add_op1[31:0]; + end + 2'b11: + begin + rem_add1_op1[31:0] = sqrt_qt_r1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = sqrt_qt_r2_rem_add_op1[31:0]; + end + 2'b10: + begin + rem_add1_op1[31:0] = div_qt_r1_rem_add_op1[31:0]; + rem_add2_op1[31:0] = div_qt_r2_rem_add_op1[31:0]; + end + default : + begin + rem_add1_op1[31:0] = 32'b0; + rem_add2_op1[31:0] = 32'b0; + end + endcase +// &CombEnd; @635 +end +assign srt_remainder_shift[31:0] = {srt_remainder[31], + srt_remainder[28:0],2'b0}; +//Remainder add +assign cur_doub_rem_1[31:0] = srt_remainder_shift[31:0] + + rem_add1_op1[31:0] + + {31'b0, ~rem_sign}; +assign cur_doub_rem_2[31:0] = srt_remainder_shift[31:0] + + rem_add2_op1[31:0] + + {31'b0, ~rem_sign}; +assign cur_rem_1[31:0] = cur_doub_rem_1[31:0]; +assign cur_rem_2[31:0] = cur_doub_rem_2[31:0]; +//Generate srt remainder update value +// &CombBeg; @648 +always @( cur_rem_2[31:0] + or bound1_cmp_sign + or srt_remainder_shift[31:0] + or bound2_cmp_sign + or cur_rem_1[31:0]) +begin +case({bound1_cmp_sign,bound2_cmp_sign}) + 2'b00: cur_rem[31:0] = cur_rem_2[31:0]; //+-2 + 2'b01: cur_rem[31:0] = cur_rem_1[31:0]; //+-1 + default: cur_rem[31:0] = srt_remainder_shift[31:0]; //0 +endcase +// &CombEnd; @654 +end +assign srt_remainder_nxt[31:0] = cur_rem[31:0]; + +//Remainder is zero signal in EX3 +assign srt_remainder_zero = ~|srt_remainder[31:0]; +// &Force("output","srt_remainder_zero"); @659 +assign srt_remainder_sign = srt_remainder[31]; + +// &Force("output", "ex2_uf"); @662 +// &ModuleEnd; @663 +endmodule + + + +// ----- 8< ----- FILE "./pa_fdsu_top.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @23 +module pa_fdsu_top( + cp0_fpu_icg_en, + cp0_fpu_xx_dqnan, + cp0_yy_clk_en, + cpurst_b, + ctrl_fdsu_ex1_sel, + ctrl_xx_ex1_cmplt_dp, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + ctrl_xx_ex2_warm_up, + ctrl_xx_ex3_warm_up, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_qnan, + dp_xx_ex1_rm, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + fdsu_fpu_debug_info, + fdsu_fpu_ex1_cmplt, + fdsu_fpu_ex1_cmplt_dp, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign, + fdsu_fpu_ex1_stall, + fdsu_fpu_no_op, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_freg, + fdsu_frbus_wb_vld, + forever_cpuclk, + frbus_fdsu_wb_grant, + idu_fpu_ex1_dst_freg, + idu_fpu_ex1_eu_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1, + pad_yy_icg_scan_en, + rtu_xx_ex1_cancel, + rtu_xx_ex2_cancel, + rtu_yy_xx_async_flush, + rtu_yy_xx_flush +); + +// &Ports; @24 +input cp0_fpu_icg_en; +input cp0_fpu_xx_dqnan; +input cp0_yy_clk_en; +input cpurst_b; +input ctrl_fdsu_ex1_sel; +input ctrl_xx_ex1_cmplt_dp; +input ctrl_xx_ex1_inst_vld; +input ctrl_xx_ex1_stall; +input ctrl_xx_ex1_warm_up; +input ctrl_xx_ex2_warm_up; +input ctrl_xx_ex3_warm_up; +input [2 :0] dp_xx_ex1_cnan; +input [2 :0] dp_xx_ex1_id; +input [2 :0] dp_xx_ex1_inf; +input [2 :0] dp_xx_ex1_qnan; +input [2 :0] dp_xx_ex1_rm; +input [2 :0] dp_xx_ex1_snan; +input [2 :0] dp_xx_ex1_zero; +input forever_cpuclk; +input frbus_fdsu_wb_grant; +input [4 :0] idu_fpu_ex1_dst_freg; +input [2 :0] idu_fpu_ex1_eu_sel; +input [9 :0] idu_fpu_ex1_func; +input [31:0] idu_fpu_ex1_srcf0; +input [31:0] idu_fpu_ex1_srcf1; +input pad_yy_icg_scan_en; +input rtu_xx_ex1_cancel; +input rtu_xx_ex2_cancel; +input rtu_yy_xx_async_flush; +input rtu_yy_xx_flush; +output [4 :0] fdsu_fpu_debug_info; +output fdsu_fpu_ex1_cmplt; +output fdsu_fpu_ex1_cmplt_dp; +output [4 :0] fdsu_fpu_ex1_fflags; +output [7 :0] fdsu_fpu_ex1_special_sel; +output [3 :0] fdsu_fpu_ex1_special_sign; +output fdsu_fpu_ex1_stall; +output fdsu_fpu_no_op; +output [31:0] fdsu_frbus_data; +output [4 :0] fdsu_frbus_fflags; +output [4 :0] fdsu_frbus_freg; +output fdsu_frbus_wb_vld; + +// &Regs; @25 + +// &Wires; @26 +wire cp0_fpu_icg_en; +wire cp0_fpu_xx_dqnan; +wire cp0_yy_clk_en; +wire cpurst_b; +wire ctrl_fdsu_ex1_sel; +wire ctrl_xx_ex1_cmplt_dp; +wire ctrl_xx_ex1_inst_vld; +wire ctrl_xx_ex1_stall; +wire ctrl_xx_ex1_warm_up; +wire ctrl_xx_ex2_warm_up; +wire ctrl_xx_ex3_warm_up; +wire [2 :0] dp_xx_ex1_cnan; +wire [2 :0] dp_xx_ex1_id; +wire [2 :0] dp_xx_ex1_inf; +wire [2 :0] dp_xx_ex1_qnan; +wire [2 :0] dp_xx_ex1_rm; +wire [2 :0] dp_xx_ex1_snan; +wire [2 :0] dp_xx_ex1_zero; +wire ex1_div; +wire [23:0] ex1_divisor; +wire [12:0] ex1_expnt_adder_op0; +wire [12:0] ex1_expnt_adder_op1; +wire ex1_of_result_lfn; +wire ex1_op0_id; +wire ex1_op0_norm; +wire ex1_op0_sign; +wire ex1_op1_id; +wire ex1_op1_id_vld; +wire ex1_op1_norm; +wire ex1_op1_sel; +wire [12:0] ex1_oper_id_expnt; +wire [12:0] ex1_oper_id_expnt_f; +wire [51:0] ex1_oper_id_frac; +wire [51:0] ex1_oper_id_frac_f; +wire ex1_pipedown; +wire ex1_pipedown_gate; +wire [31:0] ex1_remainder; +wire ex1_result_sign; +wire [2 :0] ex1_rm; +wire ex1_save_op0; +wire ex1_save_op0_gate; +wire ex1_sqrt; +wire ex1_srt_skip; +wire [9 :0] ex2_expnt_adder_op0; +wire ex2_of; +wire ex2_pipe_clk; +wire ex2_pipedown; +wire ex2_potnt_of; +wire ex2_potnt_uf; +wire ex2_result_inf; +wire ex2_result_lfn; +wire ex2_rslt_denorm; +wire [9 :0] ex2_srt_expnt_rst; +wire ex2_srt_first_round; +wire ex2_uf; +wire ex2_uf_srt_skip; +wire [9 :0] ex3_expnt_adjust_result; +wire [25:0] ex3_frac_final_rst; +wire ex3_pipedown; +wire ex3_rslt_denorm; +wire fdsu_ex1_sel; +wire fdsu_ex3_id_srt_skip; +wire fdsu_ex3_rem_sign; +wire fdsu_ex3_rem_zero; +wire [23:0] fdsu_ex3_result_denorm_round_add_num; +wire fdsu_ex4_denorm_to_tiny_frac; +wire [25:0] fdsu_ex4_frac; +wire fdsu_ex4_nx; +wire [1 :0] fdsu_ex4_potnt_norm; +wire fdsu_ex4_result_nor; +wire [4 :0] fdsu_fpu_debug_info; +wire fdsu_fpu_ex1_cmplt; +wire fdsu_fpu_ex1_cmplt_dp; +wire [4 :0] fdsu_fpu_ex1_fflags; +wire [7 :0] fdsu_fpu_ex1_special_sel; +wire [3 :0] fdsu_fpu_ex1_special_sign; +wire fdsu_fpu_ex1_stall; +wire fdsu_fpu_no_op; +wire [31:0] fdsu_frbus_data; +wire [4 :0] fdsu_frbus_fflags; +wire [4 :0] fdsu_frbus_freg; +wire fdsu_frbus_wb_vld; +wire fdsu_yy_div; +wire [9 :0] fdsu_yy_expnt_rst; +wire fdsu_yy_of; +wire fdsu_yy_of_rm_lfn; +wire fdsu_yy_op0_norm; +wire fdsu_yy_op1_norm; +wire fdsu_yy_potnt_of; +wire fdsu_yy_potnt_uf; +wire fdsu_yy_result_inf; +wire fdsu_yy_result_lfn; +wire fdsu_yy_result_sign; +wire [2 :0] fdsu_yy_rm; +wire fdsu_yy_rslt_denorm; +wire fdsu_yy_sqrt; +wire fdsu_yy_uf; +wire [4 :0] fdsu_yy_wb_freg; +wire forever_cpuclk; +wire frbus_fdsu_wb_grant; +wire [4 :0] idu_fpu_ex1_dst_freg; +wire [2 :0] idu_fpu_ex1_eu_sel; +wire [9 :0] idu_fpu_ex1_func; +wire [31:0] idu_fpu_ex1_srcf0; +wire [31:0] idu_fpu_ex1_srcf1; +wire pad_yy_icg_scan_en; +wire rtu_xx_ex1_cancel; +wire rtu_xx_ex2_cancel; +wire rtu_yy_xx_async_flush; +wire rtu_yy_xx_flush; +wire srt_remainder_zero; +wire srt_sm_on; +wire [29:0] total_qt_rt_30; + + + +// &Instance("pa_fdsu_special"); @29 +pa_fdsu_special x_pa_fdsu_special ( + .cp0_fpu_xx_dqnan (cp0_fpu_xx_dqnan ), + .dp_xx_ex1_cnan (dp_xx_ex1_cnan ), + .dp_xx_ex1_id (dp_xx_ex1_id ), + .dp_xx_ex1_inf (dp_xx_ex1_inf ), + .dp_xx_ex1_qnan (dp_xx_ex1_qnan ), + .dp_xx_ex1_snan (dp_xx_ex1_snan ), + .dp_xx_ex1_zero (dp_xx_ex1_zero ), + .ex1_div (ex1_div ), + .ex1_op0_id (ex1_op0_id ), + .ex1_op0_norm (ex1_op0_norm ), + .ex1_op0_sign (ex1_op0_sign ), + .ex1_op1_id (ex1_op1_id ), + .ex1_op1_norm (ex1_op1_norm ), + .ex1_result_sign (ex1_result_sign ), + .ex1_sqrt (ex1_sqrt ), + .ex1_srt_skip (ex1_srt_skip ), + .fdsu_fpu_ex1_fflags (fdsu_fpu_ex1_fflags ), + .fdsu_fpu_ex1_special_sel (fdsu_fpu_ex1_special_sel ), + .fdsu_fpu_ex1_special_sign (fdsu_fpu_ex1_special_sign) +); + +// &Instance("pa_fdsu_prepare"); @30 +pa_fdsu_prepare x_pa_fdsu_prepare ( + .dp_xx_ex1_rm (dp_xx_ex1_rm ), + .ex1_div (ex1_div ), + .ex1_divisor (ex1_divisor ), + .ex1_expnt_adder_op0 (ex1_expnt_adder_op0), + .ex1_expnt_adder_op1 (ex1_expnt_adder_op1), + .ex1_of_result_lfn (ex1_of_result_lfn ), + .ex1_op0_id (ex1_op0_id ), + .ex1_op0_sign (ex1_op0_sign ), + .ex1_op1_id (ex1_op1_id ), + .ex1_op1_id_vld (ex1_op1_id_vld ), + .ex1_op1_sel (ex1_op1_sel ), + .ex1_oper_id_expnt (ex1_oper_id_expnt ), + .ex1_oper_id_expnt_f (ex1_oper_id_expnt_f), + .ex1_oper_id_frac (ex1_oper_id_frac ), + .ex1_oper_id_frac_f (ex1_oper_id_frac_f ), + .ex1_remainder (ex1_remainder ), + .ex1_result_sign (ex1_result_sign ), + .ex1_rm (ex1_rm ), + .ex1_sqrt (ex1_sqrt ), + .fdsu_ex1_sel (fdsu_ex1_sel ), + .idu_fpu_ex1_func (idu_fpu_ex1_func ), + .idu_fpu_ex1_srcf0 (idu_fpu_ex1_srcf0 ), + .idu_fpu_ex1_srcf1 (idu_fpu_ex1_srcf1 ) +); + +// &Instance("pa_fdsu_srt"); @32 +// &Instance("pa_fdsu_round"); @33 +// &Instance("pa_fdsu_pack"); @34 +// &Instance("pa_fdsu_srt_single", "x_pa_fdsu_srt"); @36 +pa_fdsu_srt_single x_pa_fdsu_srt ( + .cp0_fpu_icg_en (cp0_fpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .ex1_divisor (ex1_divisor ), + .ex1_expnt_adder_op1 (ex1_expnt_adder_op1 ), + .ex1_oper_id_frac (ex1_oper_id_frac ), + .ex1_oper_id_frac_f (ex1_oper_id_frac_f ), + .ex1_pipedown (ex1_pipedown ), + .ex1_pipedown_gate (ex1_pipedown_gate ), + .ex1_remainder (ex1_remainder ), + .ex1_save_op0 (ex1_save_op0 ), + .ex1_save_op0_gate (ex1_save_op0_gate ), + .ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ), + .ex2_of (ex2_of ), + .ex2_pipe_clk (ex2_pipe_clk ), + .ex2_pipedown (ex2_pipedown ), + .ex2_potnt_of (ex2_potnt_of ), + .ex2_potnt_uf (ex2_potnt_uf ), + .ex2_result_inf (ex2_result_inf ), + .ex2_result_lfn (ex2_result_lfn ), + .ex2_rslt_denorm (ex2_rslt_denorm ), + .ex2_srt_expnt_rst (ex2_srt_expnt_rst ), + .ex2_srt_first_round (ex2_srt_first_round ), + .ex2_uf (ex2_uf ), + .ex2_uf_srt_skip (ex2_uf_srt_skip ), + .ex3_frac_final_rst (ex3_frac_final_rst ), + .ex3_pipedown (ex3_pipedown ), + .fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ), + .fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ), + .fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ), + .fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num), + .fdsu_ex4_frac (fdsu_ex4_frac ), + .fdsu_yy_div (fdsu_yy_div ), + .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), + .fdsu_yy_op0_norm (fdsu_yy_op0_norm ), + .fdsu_yy_op1_norm (fdsu_yy_op1_norm ), + .fdsu_yy_sqrt (fdsu_yy_sqrt ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .srt_remainder_zero (srt_remainder_zero ), + .srt_sm_on (srt_sm_on ), + .total_qt_rt_30 (total_qt_rt_30 ) +); + +// &Instance("pa_fdsu_round_single", "x_pa_fdsu_round"); @37 +pa_fdsu_round_single x_pa_fdsu_round ( + .cp0_fpu_icg_en (cp0_fpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .ex3_expnt_adjust_result (ex3_expnt_adjust_result ), + .ex3_frac_final_rst (ex3_frac_final_rst ), + .ex3_pipedown (ex3_pipedown ), + .ex3_rslt_denorm (ex3_rslt_denorm ), + .fdsu_ex3_id_srt_skip (fdsu_ex3_id_srt_skip ), + .fdsu_ex3_rem_sign (fdsu_ex3_rem_sign ), + .fdsu_ex3_rem_zero (fdsu_ex3_rem_zero ), + .fdsu_ex3_result_denorm_round_add_num (fdsu_ex3_result_denorm_round_add_num), + .fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac ), + .fdsu_ex4_nx (fdsu_ex4_nx ), + .fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ), + .fdsu_ex4_result_nor (fdsu_ex4_result_nor ), + .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), + .fdsu_yy_result_inf (fdsu_yy_result_inf ), + .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), + .fdsu_yy_result_sign (fdsu_yy_result_sign ), + .fdsu_yy_rm (fdsu_yy_rm ), + .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), + .forever_cpuclk (forever_cpuclk ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .total_qt_rt_30 (total_qt_rt_30 ) +); + +// &Instance("pa_fdsu_pack_single", "x_pa_fdsu_pack"); @38 +pa_fdsu_pack_single x_pa_fdsu_pack ( + .fdsu_ex4_denorm_to_tiny_frac (fdsu_ex4_denorm_to_tiny_frac), + .fdsu_ex4_frac (fdsu_ex4_frac ), + .fdsu_ex4_nx (fdsu_ex4_nx ), + .fdsu_ex4_potnt_norm (fdsu_ex4_potnt_norm ), + .fdsu_ex4_result_nor (fdsu_ex4_result_nor ), + .fdsu_frbus_data (fdsu_frbus_data ), + .fdsu_frbus_fflags (fdsu_frbus_fflags ), + .fdsu_frbus_freg (fdsu_frbus_freg ), + .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), + .fdsu_yy_of (fdsu_yy_of ), + .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), + .fdsu_yy_potnt_of (fdsu_yy_potnt_of ), + .fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ), + .fdsu_yy_result_inf (fdsu_yy_result_inf ), + .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), + .fdsu_yy_result_sign (fdsu_yy_result_sign ), + .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), + .fdsu_yy_uf (fdsu_yy_uf ), + .fdsu_yy_wb_freg (fdsu_yy_wb_freg ) +); + + +// &Instance("pa_fdsu_ctrl"); @41 +pa_fdsu_ctrl x_pa_fdsu_ctrl ( + .cp0_fpu_icg_en (cp0_fpu_icg_en ), + .cp0_yy_clk_en (cp0_yy_clk_en ), + .cpurst_b (cpurst_b ), + .ctrl_fdsu_ex1_sel (ctrl_fdsu_ex1_sel ), + .ctrl_xx_ex1_cmplt_dp (ctrl_xx_ex1_cmplt_dp ), + .ctrl_xx_ex1_inst_vld (ctrl_xx_ex1_inst_vld ), + .ctrl_xx_ex1_stall (ctrl_xx_ex1_stall ), + .ctrl_xx_ex1_warm_up (ctrl_xx_ex1_warm_up ), + .ctrl_xx_ex2_warm_up (ctrl_xx_ex2_warm_up ), + .ctrl_xx_ex3_warm_up (ctrl_xx_ex3_warm_up ), + .ex1_div (ex1_div ), + .ex1_expnt_adder_op0 (ex1_expnt_adder_op0 ), + .ex1_of_result_lfn (ex1_of_result_lfn ), + .ex1_op0_id (ex1_op0_id ), + .ex1_op0_norm (ex1_op0_norm ), + .ex1_op1_id_vld (ex1_op1_id_vld ), + .ex1_op1_norm (ex1_op1_norm ), + .ex1_op1_sel (ex1_op1_sel ), + .ex1_oper_id_expnt (ex1_oper_id_expnt ), + .ex1_oper_id_expnt_f (ex1_oper_id_expnt_f ), + .ex1_pipedown (ex1_pipedown ), + .ex1_pipedown_gate (ex1_pipedown_gate ), + .ex1_result_sign (ex1_result_sign ), + .ex1_rm (ex1_rm ), + .ex1_save_op0 (ex1_save_op0 ), + .ex1_save_op0_gate (ex1_save_op0_gate ), + .ex1_sqrt (ex1_sqrt ), + .ex1_srt_skip (ex1_srt_skip ), + .ex2_expnt_adder_op0 (ex2_expnt_adder_op0 ), + .ex2_of (ex2_of ), + .ex2_pipe_clk (ex2_pipe_clk ), + .ex2_pipedown (ex2_pipedown ), + .ex2_potnt_of (ex2_potnt_of ), + .ex2_potnt_uf (ex2_potnt_uf ), + .ex2_result_inf (ex2_result_inf ), + .ex2_result_lfn (ex2_result_lfn ), + .ex2_rslt_denorm (ex2_rslt_denorm ), + .ex2_srt_expnt_rst (ex2_srt_expnt_rst ), + .ex2_srt_first_round (ex2_srt_first_round ), + .ex2_uf (ex2_uf ), + .ex2_uf_srt_skip (ex2_uf_srt_skip ), + .ex3_expnt_adjust_result (ex3_expnt_adjust_result), + .ex3_pipedown (ex3_pipedown ), + .ex3_rslt_denorm (ex3_rslt_denorm ), + .fdsu_ex1_sel (fdsu_ex1_sel ), + .fdsu_fpu_debug_info (fdsu_fpu_debug_info ), + .fdsu_fpu_ex1_cmplt (fdsu_fpu_ex1_cmplt ), + .fdsu_fpu_ex1_cmplt_dp (fdsu_fpu_ex1_cmplt_dp ), + .fdsu_fpu_ex1_stall (fdsu_fpu_ex1_stall ), + .fdsu_fpu_no_op (fdsu_fpu_no_op ), + .fdsu_frbus_wb_vld (fdsu_frbus_wb_vld ), + .fdsu_yy_div (fdsu_yy_div ), + .fdsu_yy_expnt_rst (fdsu_yy_expnt_rst ), + .fdsu_yy_of (fdsu_yy_of ), + .fdsu_yy_of_rm_lfn (fdsu_yy_of_rm_lfn ), + .fdsu_yy_op0_norm (fdsu_yy_op0_norm ), + .fdsu_yy_op1_norm (fdsu_yy_op1_norm ), + .fdsu_yy_potnt_of (fdsu_yy_potnt_of ), + .fdsu_yy_potnt_uf (fdsu_yy_potnt_uf ), + .fdsu_yy_result_inf (fdsu_yy_result_inf ), + .fdsu_yy_result_lfn (fdsu_yy_result_lfn ), + .fdsu_yy_result_sign (fdsu_yy_result_sign ), + .fdsu_yy_rm (fdsu_yy_rm ), + .fdsu_yy_rslt_denorm (fdsu_yy_rslt_denorm ), + .fdsu_yy_sqrt (fdsu_yy_sqrt ), + .fdsu_yy_uf (fdsu_yy_uf ), + .fdsu_yy_wb_freg (fdsu_yy_wb_freg ), + .forever_cpuclk (forever_cpuclk ), + .frbus_fdsu_wb_grant (frbus_fdsu_wb_grant ), + .idu_fpu_ex1_dst_freg (idu_fpu_ex1_dst_freg ), + .idu_fpu_ex1_eu_sel (idu_fpu_ex1_eu_sel ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en ), + .rtu_xx_ex1_cancel (rtu_xx_ex1_cancel ), + .rtu_xx_ex2_cancel (rtu_xx_ex2_cancel ), + .rtu_yy_xx_async_flush (rtu_yy_xx_async_flush ), + .rtu_yy_xx_flush (rtu_yy_xx_flush ), + .srt_remainder_zero (srt_remainder_zero ), + .srt_sm_on (srt_sm_on ) +); + + + +// &ModuleEnd; @44 +endmodule + + +// ----- 8< ----- FILE "./pa_fpu_dp.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module pa_fpu_dp( + cp0_fpu_icg_en, + cp0_fpu_xx_rm, + cp0_yy_clk_en, + ctrl_xx_ex1_inst_vld, + ctrl_xx_ex1_stall, + ctrl_xx_ex1_warm_up, + dp_frbus_ex2_data, + dp_frbus_ex2_fflags, + dp_xx_ex1_cnan, + dp_xx_ex1_id, + dp_xx_ex1_inf, + dp_xx_ex1_norm, + dp_xx_ex1_qnan, + dp_xx_ex1_snan, + dp_xx_ex1_zero, + ex2_inst_wb, + fdsu_fpu_ex1_fflags, + fdsu_fpu_ex1_special_sel, + fdsu_fpu_ex1_special_sign, + forever_cpuclk, + idu_fpu_ex1_eu_sel, + idu_fpu_ex1_func, + idu_fpu_ex1_gateclk_vld, + idu_fpu_ex1_rm, + idu_fpu_ex1_srcf0, + idu_fpu_ex1_srcf1, + idu_fpu_ex1_srcf2, + pad_yy_icg_scan_en +); + +input cp0_fpu_icg_en; +input [2 :0] cp0_fpu_xx_rm; +input cp0_yy_clk_en; +input ctrl_xx_ex1_inst_vld; +input ctrl_xx_ex1_stall; +input ctrl_xx_ex1_warm_up; +input [4 :0] fdsu_fpu_ex1_fflags; +input [7 :0] fdsu_fpu_ex1_special_sel; +input [3 :0] fdsu_fpu_ex1_special_sign; +input forever_cpuclk; +input [2 :0] idu_fpu_ex1_eu_sel; +input [9 :0] idu_fpu_ex1_func; +input idu_fpu_ex1_gateclk_vld; +input [2 :0] idu_fpu_ex1_rm; +input [31:0] idu_fpu_ex1_srcf0; +input [31:0] idu_fpu_ex1_srcf1; +input [31:0] idu_fpu_ex1_srcf2; +input pad_yy_icg_scan_en; +output [31:0] dp_frbus_ex2_data; +output [4 :0] dp_frbus_ex2_fflags; +output [2 :0] dp_xx_ex1_cnan; +output [2 :0] dp_xx_ex1_id; +output [2 :0] dp_xx_ex1_inf; +output [2 :0] dp_xx_ex1_norm; +output [2 :0] dp_xx_ex1_qnan; +output [2 :0] dp_xx_ex1_snan; +output [2 :0] dp_xx_ex1_zero; +output ex2_inst_wb; + +reg [4 :0] ex1_fflags; +reg [31:0] ex1_special_data; +reg [8 :0] ex1_special_sel; +reg [3 :0] ex1_special_sign; +reg [4 :0] ex2_fflags; +reg [31:0] ex2_result; +reg [31:0] ex2_special_data; +reg [6 :0] ex2_special_sel; +reg [3 :0] ex2_special_sign; + +wire cp0_fpu_icg_en; +wire [2 :0] cp0_fpu_xx_rm; +wire cp0_yy_clk_en; +wire ctrl_xx_ex1_inst_vld; +wire ctrl_xx_ex1_stall; +wire ctrl_xx_ex1_warm_up; +wire [31:0] dp_frbus_ex2_data; +wire [4 :0] dp_frbus_ex2_fflags; +wire [2 :0] dp_xx_ex1_cnan; +wire [2 :0] dp_xx_ex1_id; +wire [2 :0] dp_xx_ex1_inf; +wire [2 :0] dp_xx_ex1_norm; +wire [2 :0] dp_xx_ex1_qnan; +wire [2 :0] dp_xx_ex1_snan; +wire [2 :0] dp_xx_ex1_zero; +wire [2 :0] ex1_decode_rm; +wire ex1_double; +wire [2 :0] ex1_eu_sel; +wire [9 :0] ex1_func; +wire [2 :0] ex1_global_rm; +wire [2 :0] ex1_rm; +wire ex1_single; +wire [31:0] ex1_special_data_final; +wire [63:0] ex1_src0; +wire [63:0] ex1_src1; +wire [63:0] ex1_src2; +wire ex1_src2_vld; +wire [2 :0] ex1_src_cnan; +wire [2 :0] ex1_src_id; +wire [2 :0] ex1_src_inf; +wire [2 :0] ex1_src_norm; +wire [2 :0] ex1_src_qnan; +wire [2 :0] ex1_src_snan; +wire [2 :0] ex1_src_zero; +wire ex2_data_clk; +wire ex2_data_clk_en; +wire ex2_inst_wb; +wire [4 :0] fdsu_fpu_ex1_fflags; +wire [7 :0] fdsu_fpu_ex1_special_sel; +wire [3 :0] fdsu_fpu_ex1_special_sign; +wire forever_cpuclk; +wire [2 :0] idu_fpu_ex1_eu_sel; +wire [9 :0] idu_fpu_ex1_func; +wire idu_fpu_ex1_gateclk_vld; +wire [2 :0] idu_fpu_ex1_rm; +wire [31:0] idu_fpu_ex1_srcf0; +wire [31:0] idu_fpu_ex1_srcf1; +wire [31:0] idu_fpu_ex1_srcf2; +wire pad_yy_icg_scan_en; + + +parameter DOUBLE_WIDTH =64; +parameter SINGLE_WIDTH =32; +parameter FUNC_WIDTH =10; +//========================================================== +// EX1 special data path +//========================================================== +assign ex1_eu_sel[2:0] = idu_fpu_ex1_eu_sel[2:0]; //3'h4 +assign ex1_func[FUNC_WIDTH-1:0] = idu_fpu_ex1_func[FUNC_WIDTH-1:0]; +assign ex1_global_rm[2:0] = cp0_fpu_xx_rm[2:0]; +assign ex1_decode_rm[2:0] = idu_fpu_ex1_rm[2:0]; + +assign ex1_rm[2:0] = (ex1_decode_rm[2:0]==3'b111) + ? ex1_global_rm[2:0] : ex1_decode_rm[2:0]; + +assign ex1_src2_vld = idu_fpu_ex1_eu_sel[1] && ex1_func[0]; + +assign ex1_src0[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf0[SINGLE_WIDTH-1:0]}; +assign ex1_src1[DOUBLE_WIDTH-1:0] = { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf1[SINGLE_WIDTH-1:0]}; +assign ex1_src2[DOUBLE_WIDTH-1:0] = ex1_src2_vld ? { {SINGLE_WIDTH{1'b1}},idu_fpu_ex1_srcf2[SINGLE_WIDTH-1:0]} + : { {SINGLE_WIDTH{1'b1}},{SINGLE_WIDTH{1'b0}} }; + +assign ex1_double = 1'b0; +assign ex1_single = 1'b1; + +//========================================================== +// EX1 special src data judge +//========================================================== +pa_fpu_src_type x_pa_fpu_ex1_srcf0_type ( + .inst_double (ex1_double ), + .inst_single (ex1_single ), + .src_cnan (ex1_src_cnan[0]), + .src_id (ex1_src_id[0] ), + .src_in (ex1_src0 ), + .src_inf (ex1_src_inf[0] ), + .src_norm (ex1_src_norm[0]), + .src_qnan (ex1_src_qnan[0]), + .src_snan (ex1_src_snan[0]), + .src_zero (ex1_src_zero[0]) +); + +pa_fpu_src_type x_pa_fpu_ex1_srcf1_type ( + .inst_double (ex1_double ), + .inst_single (ex1_single ), + .src_cnan (ex1_src_cnan[1]), + .src_id (ex1_src_id[1] ), + .src_in (ex1_src1 ), + .src_inf (ex1_src_inf[1] ), + .src_norm (ex1_src_norm[1]), + .src_qnan (ex1_src_qnan[1]), + .src_snan (ex1_src_snan[1]), + .src_zero (ex1_src_zero[1]) +); + +pa_fpu_src_type x_pa_fpu_ex1_srcf2_type ( + .inst_double (ex1_double ), + .inst_single (ex1_single ), + .src_cnan (ex1_src_cnan[2]), + .src_id (ex1_src_id[2] ), + .src_in (ex1_src2 ), + .src_inf (ex1_src_inf[2] ), + .src_norm (ex1_src_norm[2]), + .src_qnan (ex1_src_qnan[2]), + .src_snan (ex1_src_snan[2]), + .src_zero (ex1_src_zero[2]) +); + +assign dp_xx_ex1_cnan[2:0] = ex1_src_cnan[2:0]; +assign dp_xx_ex1_snan[2:0] = ex1_src_snan[2:0]; +assign dp_xx_ex1_qnan[2:0] = ex1_src_qnan[2:0]; +assign dp_xx_ex1_norm[2:0] = ex1_src_norm[2:0]; +assign dp_xx_ex1_zero[2:0] = ex1_src_zero[2:0]; +assign dp_xx_ex1_inf[2:0] = ex1_src_inf[2:0]; +assign dp_xx_ex1_id[2:0] = ex1_src_id[2:0]; + +//========================================================== +// EX1 special result judge +//========================================================== + +always @( fdsu_fpu_ex1_special_sign[3:0] + or fdsu_fpu_ex1_fflags[4:0] + or ex1_eu_sel[2:0] + or fdsu_fpu_ex1_special_sel[7:0]) +begin +case(ex1_eu_sel[2:0]) //3'h4 + 3'b100: begin//FDSU + ex1_fflags[4:0] = fdsu_fpu_ex1_fflags[4:0]; + ex1_special_sel[8:0] ={1'b0,fdsu_fpu_ex1_special_sel[7:0]}; + ex1_special_sign[3:0] = fdsu_fpu_ex1_special_sign[3:0]; + end +default: begin//FDSU + ex1_fflags[4:0] = {5{1'b0}}; + ex1_special_sel[8:0] = {9{1'b0}}; + ex1_special_sign[3:0] = {4{1'b0}}; + end +endcase +end + +always @( ex1_special_sel[8:5] + or ex1_src0[31:0] + or ex1_src1[31:0] + or ex1_src2[31:0]) +begin +case(ex1_special_sel[8:5]) + 4'b0001: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src0[SINGLE_WIDTH-1:0]; + 4'b0010: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src1[SINGLE_WIDTH-1:0]; + 4'b0100: ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; +default : ex1_special_data[SINGLE_WIDTH-1:0] = ex1_src2[SINGLE_WIDTH-1:0]; +endcase +end + +assign ex1_special_data_final[SINGLE_WIDTH-1:0] = ex1_special_data[SINGLE_WIDTH-1:0]; + +//========================================================== +// EX1-EX2 data pipedown +//========================================================== +assign ex2_data_clk_en = idu_fpu_ex1_gateclk_vld || ctrl_xx_ex1_warm_up; + +gated_clk_cell x_fpu_data_ex2_gated_clk ( + .clk_in (forever_cpuclk ), + .clk_out (ex2_data_clk ), + .external_en (1'b0 ), + .global_en (cp0_yy_clk_en ), + .local_en (ex2_data_clk_en ), + .module_en (cp0_fpu_icg_en ), + .pad_yy_icg_scan_en (pad_yy_icg_scan_en) +); + +always @(posedge ex2_data_clk) +begin + if(ctrl_xx_ex1_inst_vld && !ctrl_xx_ex1_stall || ctrl_xx_ex1_warm_up) + begin + ex2_fflags[4:0] <= ex1_fflags[4:0]; + ex2_special_sign[3:0] <= ex1_special_sign[3:0]; + ex2_special_sel[6:0] <={ex1_special_sel[8],|ex1_special_sel[7:5],ex1_special_sel[4:0]}; + ex2_special_data[SINGLE_WIDTH-1:0] <= ex1_special_data_final[SINGLE_WIDTH-1:0]; + end +end + +assign ex2_inst_wb = (|ex2_special_sel[6:0]); + +always @( ex2_special_sel[6:0] + or ex2_special_data[31:0] + or ex2_special_sign[3:0]) +begin +case(ex2_special_sel[6:0]) + 7'b0000_001: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[0],ex2_special_data[SINGLE_WIDTH-2:0]};//src2 + 7'b0000_010: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[1], {31{1'b0}} };//zero + 7'b0000_100: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[2], {8{1'b1}},{23{1'b0}} };//inf + 7'b0001_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_sign[3], {7{1'b1}},1'b0,{23{1'b1}} };//lfn + 7'b0010_000: ex2_result[SINGLE_WIDTH-1:0] = { 1'b0, {8{1'b1}},1'b1, {22{1'b0}} };//cnan + 7'b0100_000: ex2_result[SINGLE_WIDTH-1:0] = { ex2_special_data[31],{8{1'b1}}, 1'b1, ex2_special_data[21:0]};//propagate qnan + 7'b1000_000: ex2_result[SINGLE_WIDTH-1:0] = ex2_special_data[SINGLE_WIDTH-1:0]; //ex1 falu special result + default: ex2_result[SINGLE_WIDTH-1:0] = {SINGLE_WIDTH{1'b0}}; +endcase +end + +assign dp_frbus_ex2_data[SINGLE_WIDTH-1:0] = ex2_result[SINGLE_WIDTH-1:0]; +assign dp_frbus_ex2_fflags[4:0] = ex2_fflags[4:0]; + +endmodule + + + +// ----- 8< ----- FILE "./pa_fpu_frbus.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +module pa_fpu_frbus( + ctrl_frbus_ex2_wb_req, + dp_frbus_ex2_data, + dp_frbus_ex2_fflags, + fdsu_frbus_data, + fdsu_frbus_fflags, + fdsu_frbus_wb_vld, + fpu_idu_fwd_data, + fpu_idu_fwd_fflags, + fpu_idu_fwd_vld +); + +input ctrl_frbus_ex2_wb_req; +input [31:0] dp_frbus_ex2_data; +input [4 :0] dp_frbus_ex2_fflags; +input [31:0] fdsu_frbus_data; +input [4 :0] fdsu_frbus_fflags; +input fdsu_frbus_wb_vld; +output [31:0] fpu_idu_fwd_data; +output [4 :0] fpu_idu_fwd_fflags; +output fpu_idu_fwd_vld; + +reg [31:0] frbus_wb_data; +reg [4 :0] frbus_wb_fflags; + +wire ctrl_frbus_ex2_wb_req; +wire [31:0] fdsu_frbus_data; +wire [4 :0] fdsu_frbus_fflags; +wire fdsu_frbus_wb_vld; +wire [31:0] fpu_idu_fwd_data; +wire [4 :0] fpu_idu_fwd_fflags; +wire fpu_idu_fwd_vld; +wire frbus_ex2_wb_vld; +wire frbus_fdsu_wb_vld; +wire frbus_wb_vld; +wire [3 :0] frbus_source_vld; + + +//========================================================== +// Input Signal Rename +//========================================================== +assign frbus_fdsu_wb_vld = fdsu_frbus_wb_vld; +assign frbus_ex2_wb_vld = ctrl_frbus_ex2_wb_req; +assign frbus_source_vld[3:0] = {1'b0, 1'b0, frbus_ex2_wb_vld, frbus_fdsu_wb_vld}; +assign frbus_wb_vld = frbus_ex2_wb_vld | frbus_fdsu_wb_vld; + +always @( frbus_source_vld[3:0] + or fdsu_frbus_data[31:0] + or dp_frbus_ex2_data[31:0] + or fdsu_frbus_fflags[4:0] + or dp_frbus_ex2_fflags[4:0]) +begin + case(frbus_source_vld[3:0]) + 4'b0001: begin // DIV + frbus_wb_data[31:0] = fdsu_frbus_data[31:0]; + frbus_wb_fflags[4:0] = fdsu_frbus_fflags[4:0]; + end + 4'b0010: begin // EX2 + frbus_wb_data[31:0] = dp_frbus_ex2_data[31:0]; + frbus_wb_fflags[4:0] = dp_frbus_ex2_fflags[4:0]; + end + default: begin + frbus_wb_data[31:0] = {31{1'b0}}; + frbus_wb_fflags[4:0] = 5'b0; + end + endcase +end + +assign fpu_idu_fwd_vld = frbus_wb_vld; +assign fpu_idu_fwd_fflags[4:0] = frbus_wb_fflags[4:0]; +assign fpu_idu_fwd_data[31:0] = frbus_wb_data[31:0]; + +endmodule + + +// ----- 8< ----- FILE "./pa_fpu_src_type.v" ----- 8< ----- + +/*Copyright 2020-2021 T-Head Semiconductor Co., Ltd. + +Licensed under the Apache License, Version 2.0 (the "License"); +you may not use this file except in compliance with the License. +You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + +Unless required by applicable law or agreed to in writing, software +distributed under the License is distributed on an "AS IS" BASIS, +WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +See the License for the specific language governing permissions and +limitations under the License. +*/ + +// &ModuleBeg; @24 +module pa_fpu_src_type( + inst_double, + inst_single, + src_cnan, + src_id, + src_in, + src_inf, + src_norm, + src_qnan, + src_snan, + src_zero +); + +// &Ports; @25 +input inst_double; +input inst_single; +input [63:0] src_in; +output src_cnan; +output src_id; +output src_inf; +output src_norm; +output src_qnan; +output src_snan; +output src_zero; + +// &Regs; @26 + +// &Wires; @27 +wire inst_double; +wire inst_single; +wire [63:0] src; +wire src_cnan; +wire src_expn_max; +wire src_expn_zero; +wire src_frac_msb; +wire src_frac_zero; +wire src_id; +wire [63:0] src_in; +wire src_inf; +wire src_norm; +wire src_qnan; +wire src_snan; +wire src_zero; + + +// &Depend("cpu_cfig.h"); @29 +assign src[63:0] = src_in[63:0]; + +assign src_cnan = !(&src[63:32]) && inst_single; + +assign src_expn_zero = !(|src[62:52]) && inst_double || + !(|src[30:23]) && inst_single; + +assign src_expn_max = (&src[62:52]) && inst_double || + (&src[30:23]) && inst_single; + +assign src_frac_zero = !(|src[51:0]) && inst_double || + !(|src[22:0]) && inst_single; + +assign src_frac_msb = src[51] && inst_double || src[22] && inst_single; + +assign src_snan = src_expn_max && !src_frac_msb && !src_frac_zero && !src_cnan; +assign src_qnan = src_expn_max && src_frac_msb || src_cnan; +assign src_zero = src_expn_zero && src_frac_zero && !src_cnan; +assign src_id = src_expn_zero && !src_frac_zero && !src_cnan; +assign src_inf = src_expn_max && src_frac_zero && !src_cnan; +assign src_norm =!(src_expn_zero && src_frac_zero) && + ! src_expn_max && !src_cnan; + +// &Force("output","src_cnan"); @53 + +// &ModuleEnd; @55 +endmodule + + + +// ----- 8< ----- FILE "./fpnew_divsqrt_th_32.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019-2022 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Authors: Stefan Mach +// Luca Bertaccini +// Jiang Lannan +// Kexin Li + + + +module fpnew_divsqrt_th_32 #( + // FP32-only DivSqrt + // FPU configuration + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = 32, + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [1:0][WIDTH-1:0] operands_i, // 2 operands + input logic [NUM_FORMATS-1:0][1:0] is_boxed_i, // 2 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + // ---------- + // Constants + // ---------- + // Pipelines + localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 2) // Last to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = (PipeConfig == fpnew_pkg::AFTER || PipeConfig == fpnew_pkg::INSIDE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 2) // First to get distributed regs + : 0); // no regs here otherwise + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [1:0][WIDTH-1:0] operands_q; + fpnew_pkg::roundmode_e rnd_mode_q; + fpnew_pkg::operation_e op_q; + logic in_valid_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign rnd_mode_q = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign op_q = inp_pipe_op_q[NUM_INP_REGS]; + assign in_valid_q = inp_pipe_valid_q[NUM_INP_REGS]; + + // ------------ + // Control FSM + // ------------ + logic in_ready; // input handshake with upstream + logic div_op, sqrt_op; // input signalling with unit + logic unit_ready_q, unit_done; // status signals from unit instance + logic op_starting; // high in the cycle a new operation starts + logic out_valid, out_ready; // output handshake with downstream + logic hold_result; // whether to put result into hold register + logic data_is_held; // data in hold register is valid + logic unit_busy; // valid data in flight + // FSM states + typedef enum logic [1:0] {IDLE, BUSY, HOLD, UNREACHABLE} fsm_state_e; + fsm_state_e state_q, state_d; + + // Operations are gated by the FSM ready. Invalid input ops run a sqrt to not lose illegal instr. + assign div_op = in_valid_q & (op_q == fpnew_pkg::DIV) & in_ready & ~flush_i; //in_ready delete, valid independent of ready + assign sqrt_op = in_valid_q & (op_q == fpnew_pkg::SQRT) & in_ready & ~flush_i; + assign op_starting = div_op | sqrt_op; //start computing or handshake, modify tb handshake right + + logic fdsu_fpu_ex1_stall, fdsu_fpu_ex1_stall_q; + logic div_op_d, div_op_q; + logic sqrt_op_d, sqrt_op_q; + + assign div_op_d = (fdsu_fpu_ex1_stall) ? div_op : 1'b0; + assign sqrt_op_d = (fdsu_fpu_ex1_stall) ? sqrt_op : 1'b0; + + `FFL(fdsu_fpu_ex1_stall_q, fdsu_fpu_ex1_stall, 1'b1, '0) + `FFL(div_op_q, div_op_d, 1'b1, '0) + `FFL(sqrt_op_q, sqrt_op_d, 1'b1, '0) + + // FSM to safely apply and receive data from DIVSQRT unit + always_comb begin : flag_fsm + // Default assignments + in_ready = 1'b0; + out_valid = 1'b0; + hold_result = 1'b0; + data_is_held = 1'b0; + unit_busy = 1'b0; + state_d = state_q; + inp_pipe_ready[NUM_INP_REGS] = unit_ready_q; + + unique case (state_q) + // Waiting for work + IDLE: begin + // in_ready = 1'b1; // we're ready + in_ready = unit_ready_q; //*** + if (in_valid_q && unit_ready_q) begin // New work arrives + inp_pipe_ready[NUM_INP_REGS] = unit_ready_q && !fdsu_fpu_ex1_stall; + state_d = BUSY; // go into processing state + end + end + // Operation in progress + BUSY: begin + inp_pipe_ready[NUM_INP_REGS] = fdsu_fpu_ex1_stall_q; + unit_busy = 1'b1; // data in flight + // If the unit is done with processing + if (unit_done) begin + out_valid = 1'b1; // try to commit result downstream + // If downstream accepts our result + if (out_ready) begin + state_d = IDLE; // we anticipate going back to idling.. + if (in_valid_q && unit_ready_q) begin // ..unless new work comes in + in_ready = 1'b1; // we acknowledge the instruction + state_d = BUSY; // and stay busy with it + end + // Otherwise if downstream is not ready for the result + end else begin + hold_result = 1'b1; // activate the hold register + state_d = HOLD; // wait for the pipeline to take the data + end + end + end + // Waiting with valid result for downstream + HOLD: begin + unit_busy = 1'b1; // data in flight + data_is_held = 1'b1; // data in hold register is valid + out_valid = 1'b1; // try to commit result downstream + // If the result is accepted by downstream + if (out_ready) begin + state_d = IDLE; // go back to idle.. + if (in_valid_q && unit_ready_q) begin // ..unless new work comes in + in_ready = 1'b1; // acknowledge the new transaction + state_d = BUSY; // will be busy with the next instruction + end + end + end + // fall into idle state otherwise + default: state_d = IDLE; + endcase + + // Flushing overrides the other actions + if (flush_i) begin + unit_busy = 1'b0; // data is invalidated + out_valid = 1'b0; // cancel any valid data + state_d = IDLE; // go to default state + end + end + + // FSM status register (asynch active low reset) + `FF(state_q, state_d, IDLE) + + // Hold additional information while the operation is in progress + TagType result_tag_q; + AuxType result_aux_q; + logic result_mask_q; + + // Fill the registers everytime a valid operation arrives (load FF, active low asynch rst) + `FFL(result_tag_q, inp_pipe_tag_q[NUM_INP_REGS], op_starting, '0) + `FFL(result_mask_q, inp_pipe_mask_q[NUM_INP_REGS], op_starting, '0) + `FFL(result_aux_q, inp_pipe_aux_q[NUM_INP_REGS], op_starting, '0) + + // ----------------- + // DIVSQRT instance + // ----------------- + logic [WIDTH-1:0] unit_result, held_result_q; + fpnew_pkg::status_t unit_status, held_status_q; + + // thead define fdsu module's input and output + logic ctrl_fdsu_ex1_sel; + logic fdsu_fpu_ex1_cmplt; + logic [4:0] fdsu_fpu_ex1_fflags; + logic [7:0] fdsu_fpu_ex1_special_sel; + logic [3:0] fdsu_fpu_ex1_special_sign; + logic fdsu_fpu_no_op; + logic [2:0] idu_fpu_ex1_eu_sel; + logic [31:0] fdsu_frbus_data; + logic [4:0] fdsu_frbus_fflags; + logic fdsu_frbus_wb_vld; + + // dp + logic [31:0] dp_frbus_ex2_data; + logic [4:0] dp_frbus_ex2_fflags; + logic [2:0] dp_xx_ex1_cnan; + logic [2:0] dp_xx_ex1_id; + logic [2:0] dp_xx_ex1_inf; + logic [2:0] dp_xx_ex1_norm; + logic [2:0] dp_xx_ex1_qnan; + logic [2:0] dp_xx_ex1_snan; + logic [2:0] dp_xx_ex1_zero; + logic ex2_inst_wb; + logic ex2_inst_wb_vld_d, ex2_inst_wb_vld_q; + + // frbus + logic [31:0] fpu_idu_fwd_data; + logic [4:0] fpu_idu_fwd_fflags; + logic fpu_idu_fwd_vld; + + logic unit_ready_d; + + // unit_ready_q related to state machine, different under special and normal cases. + always_comb begin + if(op_starting && unit_ready_q) begin + if(ex2_inst_wb && ex2_inst_wb_vld_q) begin + unit_ready_d = 1'b1; + end else begin + unit_ready_d = 1'b0; + end + end else if(fpu_idu_fwd_vld | flush_i) begin + unit_ready_d = 1'b1; + end else begin + unit_ready_d = unit_ready_q; + end + end + + `FFL(unit_ready_q, unit_ready_d, 1'b1, 1'b1) + + // determine input of time to select operands + always_comb begin + ctrl_fdsu_ex1_sel = 1'b0; + idu_fpu_ex1_eu_sel = 3'h0; + if (op_starting) begin // time to start calculation + ctrl_fdsu_ex1_sel = 1'b1; // time to select operands + idu_fpu_ex1_eu_sel = 3'h4; // time to select operands, only idu_fpu_ex1_eu_sel_i[2] works in fdsu module + end else if (fdsu_fpu_ex1_stall_q) begin + ctrl_fdsu_ex1_sel = 1'b1; // time to select operands + idu_fpu_ex1_eu_sel = 3'h4; // time to select operands, only idu_fpu_ex1_eu_sel_i[2] works in fdsu module + end else begin + ctrl_fdsu_ex1_sel = 1'b0; + idu_fpu_ex1_eu_sel = 3'h0; + end + end + + pa_fdsu_top i_divsqrt_thead ( + .cp0_fpu_icg_en ( 1'b0 ), // input clock gate enable in gated_clk_cell, active 0. + .cp0_fpu_xx_dqnan ( 1'b0 ), // When dqnan = 0, QNAN (0x7fc00000). + .cp0_yy_clk_en ( 1'b1 ), // clock enable in gated_clk_cell, active 1. + .cpurst_b ( rst_ni ), // If negedge cpu reset, all state machines reset to IDLE. + .ctrl_fdsu_ex1_sel ( ctrl_fdsu_ex1_sel ), // select operands + .ctrl_xx_ex1_cmplt_dp ( ctrl_fdsu_ex1_sel ), // complete datapath + .ctrl_xx_ex1_inst_vld ( ctrl_fdsu_ex1_sel ), // instance valid + .ctrl_xx_ex1_stall ( fdsu_fpu_ex1_stall ), + .ctrl_xx_ex1_warm_up ( 1'b0 ), + .ctrl_xx_ex2_warm_up ( 1'b0 ), + .ctrl_xx_ex3_warm_up ( 1'b0 ), + .dp_xx_ex1_cnan ( dp_xx_ex1_cnan ), // Special input type determination + .dp_xx_ex1_id ( dp_xx_ex1_id ), + .dp_xx_ex1_inf ( dp_xx_ex1_inf ), + .dp_xx_ex1_qnan ( dp_xx_ex1_qnan ), + .dp_xx_ex1_rm ( rnd_mode_q ), // rounding mode + .dp_xx_ex1_snan ( dp_xx_ex1_snan ), + .dp_xx_ex1_zero ( dp_xx_ex1_zero ), + .fdsu_fpu_debug_info ( ), // output, not used + .fdsu_fpu_ex1_cmplt ( fdsu_fpu_ex1_cmplt ), // output, ctrl_xx_ex1_cmplt_dp && idu_fpu_ex1_eu_sel_i[2] + .fdsu_fpu_ex1_cmplt_dp ( ), // output, not used + .fdsu_fpu_ex1_fflags ( fdsu_fpu_ex1_fflags ), // output, special case fflags + .fdsu_fpu_ex1_special_sel ( fdsu_fpu_ex1_special_sel ), // output, special case type selection + .fdsu_fpu_ex1_special_sign ( fdsu_fpu_ex1_special_sign ), // output, special case sign determination + .fdsu_fpu_ex1_stall ( fdsu_fpu_ex1_stall ), // output, determine whether stall in ex1 + .fdsu_fpu_no_op ( fdsu_fpu_no_op ), // output, if Write Back SM and fdsu SM no operation, fdsu_fpu_no_op = 1; Otherwise if busy, fdsu_fpu_no_op = 0. (not used) + .fdsu_frbus_data ( fdsu_frbus_data ), // output, normal case result + .fdsu_frbus_fflags ( fdsu_frbus_fflags ), // output, normal case fflags + .fdsu_frbus_freg ( ), // output, determined by input idu_fpu_ex1_dst_freg + .fdsu_frbus_wb_vld ( fdsu_frbus_wb_vld ), // output, determine whether write back valid + .forever_cpuclk ( clk_i ), + .frbus_fdsu_wb_grant ( fdsu_frbus_wb_vld ), // input is fdsu_frbus_wb_vld + .idu_fpu_ex1_dst_freg ( 5'h0f ), // register index to write back (not used) + .idu_fpu_ex1_eu_sel ( idu_fpu_ex1_eu_sel ), // time to select operands + .idu_fpu_ex1_func ( {8'b0, div_op | div_op_q, sqrt_op | sqrt_op_q} ), + .idu_fpu_ex1_srcf0 ( operands_q[0][31:0] ), // the first operand + .idu_fpu_ex1_srcf1 ( operands_q[1][31:0] ), // the second operand + .pad_yy_icg_scan_en ( 1'b0 ), // input of core_top, set to 1'b0 from the beginning to end + .rtu_xx_ex1_cancel ( 1'b0 ), + .rtu_xx_ex2_cancel ( 1'b0 ), + .rtu_yy_xx_async_flush ( flush_i ), + .rtu_yy_xx_flush ( 1'b0 ) + ); + + pa_fpu_dp x_pa_fpu_dp ( + .cp0_fpu_icg_en ( 1'b0 ), + .cp0_fpu_xx_rm ( rnd_mode_q ), + .cp0_yy_clk_en ( 1'b1 ), + .ctrl_xx_ex1_inst_vld ( ctrl_fdsu_ex1_sel ), + .ctrl_xx_ex1_stall ( 1'b0 ), + .ctrl_xx_ex1_warm_up ( 1'b0 ), + .dp_frbus_ex2_data ( dp_frbus_ex2_data ), // output + .dp_frbus_ex2_fflags ( dp_frbus_ex2_fflags ), // output + .dp_xx_ex1_cnan ( dp_xx_ex1_cnan ), // output + .dp_xx_ex1_id ( dp_xx_ex1_id ), // output + .dp_xx_ex1_inf ( dp_xx_ex1_inf ), // output + .dp_xx_ex1_norm ( dp_xx_ex1_norm ), // output + .dp_xx_ex1_qnan ( dp_xx_ex1_qnan ), // output + .dp_xx_ex1_snan ( dp_xx_ex1_snan ), // output + .dp_xx_ex1_zero ( dp_xx_ex1_zero ), // output + .ex2_inst_wb ( ex2_inst_wb ), // output + .fdsu_fpu_ex1_fflags ( fdsu_fpu_ex1_fflags ), + .fdsu_fpu_ex1_special_sel ( fdsu_fpu_ex1_special_sel ), + .fdsu_fpu_ex1_special_sign ( fdsu_fpu_ex1_special_sign ), + .forever_cpuclk ( clk_i ), + .idu_fpu_ex1_eu_sel ( idu_fpu_ex1_eu_sel ), + .idu_fpu_ex1_func ( {8'b0, div_op, sqrt_op} ), + .idu_fpu_ex1_gateclk_vld ( fdsu_fpu_ex1_cmplt ), + .idu_fpu_ex1_rm ( rnd_mode_q ), + .idu_fpu_ex1_srcf0 ( operands_q[0][31:0] ), + .idu_fpu_ex1_srcf1 ( operands_q[1][31:0] ), + .idu_fpu_ex1_srcf2 ( '0 ), + .pad_yy_icg_scan_en ( 1'b0 ) + ); + + assign ex2_inst_wb_vld_d = ctrl_fdsu_ex1_sel; + `FF(ex2_inst_wb_vld_q, ex2_inst_wb_vld_d, '0) + + pa_fpu_frbus x_pa_fpu_frbus ( + .ctrl_frbus_ex2_wb_req ( ex2_inst_wb & ex2_inst_wb_vld_q ), + .dp_frbus_ex2_data ( dp_frbus_ex2_data ), + .dp_frbus_ex2_fflags ( dp_frbus_ex2_fflags ), + .fdsu_frbus_data ( fdsu_frbus_data ), + .fdsu_frbus_fflags ( fdsu_frbus_fflags ), + .fdsu_frbus_wb_vld ( fdsu_frbus_wb_vld ), + .fpu_idu_fwd_data ( fpu_idu_fwd_data ), // output + .fpu_idu_fwd_fflags ( fpu_idu_fwd_fflags ), // output + .fpu_idu_fwd_vld ( fpu_idu_fwd_vld ) // output + ); + + always_comb begin + unit_result[31:0] = fpu_idu_fwd_data[31:0]; + unit_status[4:0] = fpu_idu_fwd_fflags[4:0]; + unit_done = fpu_idu_fwd_vld; + end + + // The Hold register (load, no reset) + `FFLNR(held_result_q, unit_result, hold_result, clk_i) + `FFLNR(held_status_q, unit_status, hold_result, clk_i) + + // -------------- + // Output Select + // -------------- + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + // Prioritize hold register data + assign result_d = data_is_held ? held_result_q : unit_result; + assign status_d = data_is_held ? held_status_q : unit_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = result_tag_q; + assign out_pipe_mask_q[0] = result_mask_q; + assign out_pipe_aux_q[0] = result_aux_q; + assign out_pipe_valid_q[0] = out_valid; + // Input stage: Propagate pipeline ready signal to inside pipe + assign out_ready = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, unit_busy, out_pipe_valid_q}); +endmodule +// ----- 8< ----- FILE "./fpnew_fma.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + + + +module fpnew_fma #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [2:0][WIDTH-1:0] operands_i, // 3 operands + input logic [2:0] is_boxed_i, // 3 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + // ---------- + // Constants + // ---------- + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + localparam int unsigned BIAS = fpnew_pkg::bias(FpFormat); + // Precision bits 'p' include the implicit bit + localparam int unsigned PRECISION_BITS = MAN_BITS + 1; + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam int unsigned LOWER_SUM_WIDTH = 2 * PRECISION_BITS + 3; + localparam int unsigned LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + // Internal exponent width of FMA must accomodate all meaningful exponent values in order to avoid + // datapath leakage. This is either given by the exponent bits or the width of the LZC result. + // In most reasonable FP formats the internal exponent will be wider than the LZC result. + localparam int unsigned EXP_WIDTH = unsigned'(fpnew_pkg::maximum(EXP_BITS + 2, LZC_RESULT_WIDTH)); + // Shift amount width: maximum internal mantissa size is 3p+4 bits + localparam int unsigned SHIFT_AMOUNT_WIDTH = $clog2(3 * PRECISION_BITS + 5); + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][2:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][2:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + + // ----------------- + // Input processing + // ----------------- + fpnew_pkg::fp_info_t [2:0] info_q; + + // Classify input + fpnew_classifier #( + .FpFormat ( FpFormat ), + .NumOperands ( 3 ) + ) i_class_inputs ( + .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ), + .info_o ( info_q ) + ); + + fp_t operand_a, operand_b, operand_c; + fpnew_pkg::fp_info_t info_a, info_b, info_c; + + // Operation selection and operand adjustment + // | \c op_q | \c op_mod_q | Operation Adjustment + // |:--------:|:-----------:|--------------------- + // | FMADD | \c 0 | FMADD: none + // | FMADD | \c 1 | FMSUB: Invert sign of operand C + // | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A + // | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C + // | ADD | \c 0 | ADD: Set operand A to +1.0 + // | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C + // | MUL | \c 0 | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode + // | *others* | \c - | *invalid* + // \note \c op_mod_q always inverts the sign of the addend. + always_comb begin : op_select + + // Default assignments - packing-order-agnostic + operand_a = inp_pipe_operands_q[NUM_INP_REGS][0]; + operand_b = inp_pipe_operands_q[NUM_INP_REGS][1]; + operand_c = inp_pipe_operands_q[NUM_INP_REGS][2]; + info_a = info_q[0]; + info_b = info_q[1]; + info_c = info_q[2]; + + // op_mod_q inverts sign of operand C + operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::FMADD: ; // do nothing + fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product + fpnew_pkg::ADD: begin // Set multiplicand to +1 + operand_a = '{sign: 1'b0, exponent: BIAS, mantissa: '0}; + info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. + end + fpnew_pkg::MUL: begin // Set addend to +0 or -0, depending whether the rounding mode is RDN + if (inp_pipe_rnd_mode_q[NUM_INP_REGS] == fpnew_pkg::RDN) + operand_c = '{sign: 1'b0, exponent: '0, mantissa: '0}; + else + operand_c = '{sign: 1'b1, exponent: '0, mantissa: '0}; + info_c = '{is_zero: 1'b1, is_boxed: 1'b1, default: 1'b0}; //zero, boxed value. + end + default: begin // propagate don't cares + operand_a = '{default: fpnew_pkg::DONT_CARE}; + operand_b = '{default: fpnew_pkg::DONT_CARE}; + operand_c = '{default: fpnew_pkg::DONT_CARE}; + info_a = '{default: fpnew_pkg::DONT_CARE}; + info_b = '{default: fpnew_pkg::DONT_CARE}; + info_c = '{default: fpnew_pkg::DONT_CARE}; + end + endcase + end + + // --------------------- + // Input classification + // --------------------- + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + logic effective_subtraction; + logic tentative_sign; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf, info_c.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan, info_c.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling, info_c.is_signalling}); + // Effective subtraction in FMA occurs when product and addend signs differ + assign effective_subtraction = operand_a.sign ^ operand_b.sign ^ operand_c.sign; + // The tentative sign of the FMA shall be the sign of the product + assign tentative_sign = operand_a.sign ^ operand_b.sign; + + // ---------------------- + // Special case handling + // ---------------------- + fp_t special_result; + fpnew_pkg::status_t special_status; + logic result_is_special; + + always_comb begin : special_cases + // Default assignments + special_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; // canonical qNaN + special_status = '0; + result_is_special = 1'b0; + + // Handle potentially mixed nan & infinity input => important for the case where infinity and + // zero are multiplied and added to a qnan. + // RISC-V mandates raising the NV exception in these cases: + // (inf * 0) + c or (0 * inf) + c INVALID, no matter c (even quiet NaNs) + if ((info_a.is_inf && info_b.is_zero) || (info_a.is_zero && info_b.is_inf)) begin + result_is_special = 1'b1; // bypass FMA, output is the canonical qNaN + special_status.NV = 1'b1; // invalid operation + // NaN Inputs cause canonical quiet NaN at the output and maybe invalid OP + end else if (any_operand_nan) begin + result_is_special = 1'b1; // bypass FMA, output is the canonical qNaN + special_status.NV = signalling_nan; // raise the invalid operation flag if signalling + // Special cases involving infinity + end else if (any_operand_inf) begin + result_is_special = 1'b1; // bypass FMA + // Effective addition of opposite infinities (??inf - ??inf) is invalid! + if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) + special_status.NV = 1'b1; // invalid operation + // Handle cases where output will be inf because of inf product input + else if (info_a.is_inf || info_b.is_inf) begin + // Result is infinity with the sign of the product + special_result = '{sign: operand_a.sign ^ operand_b.sign, exponent: '1, mantissa: '0}; + // Handle cases where the addend is inf + end else if (info_c.is_inf) begin + // Result is inifinity with sign of the addend (= operand_c) + special_result = '{sign: operand_c.sign, exponent: '1, mantissa: '0}; + end + end + end + + // --------------------------- + // Initial exponent data path + // --------------------------- + logic signed [EXP_WIDTH-1:0] exponent_a, exponent_b, exponent_c; + logic signed [EXP_WIDTH-1:0] exponent_addend, exponent_product, exponent_difference; + logic signed [EXP_WIDTH-1:0] tentative_exponent; + + // Zero-extend exponents into signed container - implicit width extension + assign exponent_a = signed'({1'b0, operand_a.exponent}); + assign exponent_b = signed'({1'b0, operand_b.exponent}); + assign exponent_c = signed'({1'b0, operand_c.exponent}); + + // Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx) + // with Ex the encoded exponent and nx the implicit bit. Internal exponents stay biased. + assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm + // Biased product exponent is the sum of encoded exponents minus the bias. + assign exponent_product = (info_a.is_zero || info_b.is_zero) + ? 2 - signed'(BIAS) // in case the product is zero, set minimum exp. + : signed'(exponent_a + info_a.is_subnormal + + exponent_b + info_b.is_subnormal + - signed'(BIAS)); + // Exponent difference is the addend exponent minus the product exponent + assign exponent_difference = exponent_addend - exponent_product; + // The tentative exponent will be the larger of the product or addend exponent + assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product; + + // Shift amount for addend based on exponents (unsigned as only right shifts) + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt; + + always_comb begin : addend_shift_amount + // Product-anchored case, saturated shift (addend is only in the sticky bit) + if (exponent_difference <= signed'(-2 * PRECISION_BITS - 1)) + addend_shamt = 3 * PRECISION_BITS + 4; + // Addend and product will have mutual bits to add + else if (exponent_difference <= signed'(PRECISION_BITS + 2)) + addend_shamt = unsigned'(signed'(PRECISION_BITS) + 3 - exponent_difference); + // Addend-anchored case, saturated shift (product is only in the sticky bit) + else + addend_shamt = 0; + end + + // ------------------ + // Product data path + // ------------------ + logic [PRECISION_BITS-1:0] mantissa_a, mantissa_b, mantissa_c; + logic [2*PRECISION_BITS-1:0] product; // the p*p product is 2p bits wide + logic [3*PRECISION_BITS+3:0] product_shifted; // addends are 3p+4 bit wide (including G/R) + + // Add implicit bits to mantissae + assign mantissa_a = {info_a.is_normal, operand_a.mantissa}; + assign mantissa_b = {info_b.is_normal, operand_b.mantissa}; + assign mantissa_c = {info_c.is_normal, operand_c.mantissa}; + + // Mantissa multiplier (a*b) + assign product = mantissa_a * mantissa_b; + + // Product is placed into a 3p+4 bit wide vector, padded with 2 bits for round and sticky: + // | 000...000 | product | RS | + // <- p+2 -> <- 2p -> < 2> + assign product_shifted = product << 2; // constant shift + + // ----------------- + // Addend data path + // ----------------- + logic [3*PRECISION_BITS+3:0] addend_after_shift; // upper 3p+4 bits are needed to go on + logic [PRECISION_BITS-1:0] addend_sticky_bits; // up to p bit of shifted addend are sticky + logic sticky_before_add; // they are compressed into a single sticky bit + logic [3*PRECISION_BITS+3:0] addend_shifted; // addends are 3p+4 bit wide (including G/R) + logic inject_carry_in; // inject carry for subtractions if needed + + // In parallel, the addend is right-shifted according to the exponent difference. Up to p bits + // are shifted out and compressed into a sticky bit. + // BEFORE THE SHIFT: + // | mantissa_c | 000..000 | + // <- p -> <- 3p+4 -> + // AFTER THE SHIFT: + // | 000..........000 | mantissa_c | 000...............0GR | sticky bits | + // <- addend_shamt -> <- p -> <- 2p+4-addend_shamt -> <- up to p -> + assign {addend_after_shift, addend_sticky_bits} = + (mantissa_c << (3 * PRECISION_BITS + 4)) >> addend_shamt; + + assign sticky_before_add = (| addend_sticky_bits); + // assign addend_after_shift[0] = sticky_before_add; + + // In case of a subtraction, the addend is inverted + assign addend_shifted = (effective_subtraction) ? ~addend_after_shift : addend_after_shift; + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + + // ------ + // Adder + // ------ + logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry + logic sum_carry; // observe carry bit from sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic final_sign; + + //Mantissa adder (ab+c). In normal addition, it cannot overflow. + assign sum_raw = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + + // Complement negative sum (can only happen in subtraction -> overflows for positive results) + assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + + // In case of a mispredicted subtraction result, do a sign flip + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) + ? 1'b1 + : (effective_subtraction ? 1'b0 : tentative_sign); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic effective_subtraction_q; + logic signed [EXP_WIDTH-1:0] exponent_product_q; + logic signed [EXP_WIDTH-1:0] exponent_difference_q; + logic signed [EXP_WIDTH-1:0] tentative_exponent_q; + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q; + logic sticky_before_add_q; + logic [3*PRECISION_BITS+3:0] sum_q; + logic final_sign_q; + fpnew_pkg::roundmode_e rnd_mode_q; + logic result_is_special_q; + fp_t special_result_q; + fpnew_pkg::status_t special_status_q; + // Internal pipeline signals, index i holds signal after i register stages + logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; + logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; + logic [0:NUM_MID_REGS] mid_pipe_sticky_q; + logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; + logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_eff_sub_q[0] = effective_subtraction; + assign mid_pipe_exp_prod_q[0] = exponent_product; + assign mid_pipe_exp_diff_q[0] = exponent_difference; + assign mid_pipe_tent_exp_q[0] = tentative_exponent; + assign mid_pipe_add_shamt_q[0] = addend_shamt; + assign mid_pipe_sticky_q[0] = sticky_before_add; + assign mid_pipe_sum_q[0] = sum; + assign mid_pipe_final_sign_q[0] = final_sign; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_res_is_spec_q[0] = result_is_special; + assign mid_pipe_spec_res_q[0] = special_result; + assign mid_pipe_spec_stat_q[0] = special_status; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_eff_sub_q[i+1], mid_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_prod_q[i+1], mid_pipe_exp_prod_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_diff_q[i+1], mid_pipe_exp_diff_q[i], reg_ena, '0) + `FFL(mid_pipe_tent_exp_q[i+1], mid_pipe_tent_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0) + `FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0) + `FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0) + `FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_res_is_spec_q[i+1], mid_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_res_q[i+1], mid_pipe_spec_res_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_stat_q[i+1], mid_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + + // -------------- + // Normalization + // -------------- + logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched + logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes + logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count + logic lzc_zeroes; // in case only zeroes found + + logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount + logic signed [EXP_WIDTH-1:0] normalized_exponent; + + logic [3*PRECISION_BITS+4:0] sum_shifted; // result after first normalization shift + logic [PRECISION_BITS:0] final_mantissa; // final mantissa before rounding with round bit + logic [2*PRECISION_BITS+2:0] sum_sticky_bits; // remaining 2p+3 sticky bits after normalization + logic sticky_after_norm; // sticky bit after normalization + + logic signed [EXP_WIDTH-1:0] final_exponent; + + assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; + + // Leading zero counter for cancellations + lzc #( + .WIDTH ( LOWER_SUM_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( sum_lower ), + .cnt_o ( leading_zero_count ), + .empty_o ( lzc_zeroes ) + ); + + assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count}); + + // Normalization shift amount based on exponents and LZC (unsigned as only left shifts) + always_comb begin : norm_shift_amount + // Product-anchored case or cancellations require LZC + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + // Normal result (biased exponent > 0 and not a zero) + if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin + // Undo initial product shift, remove the counted zeroes + norm_shamt = PRECISION_BITS + 2 + leading_zero_count; + normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift + // Subnormal result + end else begin + // Cap the shift distance to align mantissa with minimum exponent + norm_shamt = unsigned'(signed'(PRECISION_BITS) + 2 + exponent_product_q); + normalized_exponent = 0; // subnormals encoded as 0 + end + // Addend-anchored case + end else begin + norm_shamt = addend_shamt_q; // Undo the initial shift + normalized_exponent = tentative_exponent_q; + end + end + + // Do the large normalization shift + assign sum_shifted = sum_q << norm_shamt; + + // The addend-anchored case needs a 1-bit normalization since the leading-one can be to the left + // or right of the (non-carry) MSB of the sum. + always_comb begin : small_norm + // Default assignment, discarding carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + + // The normalized sum has overflown, align right and fix exponent + if (sum_shifted[3*PRECISION_BITS+4]) begin // check the carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + // The normalized sum is normal, nothing to do + end else if (sum_shifted[3*PRECISION_BITS+3]) begin // check the sum MSB + // do nothing + // The normalized sum is still denormal, align left - unless the result is not already subnormal + end else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + // Otherwise we're denormal + end else begin + final_exponent = '0; + end + end + + // Update the sticky bit with the shifted-out bits + assign sticky_after_norm = (| {sum_sticky_bits}) | sticky_before_add_q; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic pre_round_sign; + logic [EXP_BITS-1:0] pre_round_exponent; + logic [MAN_BITS-1:0] pre_round_mantissa; + logic [EXP_BITS+MAN_BITS-1:0] pre_round_abs; // absolute value of result before rounding + logic [1:0] round_sticky_bits; + + logic of_before_round, of_after_round; // overflow + logic uf_before_round, uf_after_round; // underflow + logic result_zero; + + logic rounded_sign; + logic [EXP_BITS+MAN_BITS-1:0] rounded_abs; // absolute value of result after rounding + + // Classification before round. RISC-V mandates checking underflow AFTER rounding! + assign of_before_round = final_exponent >= 2**(EXP_BITS)-1; // infinity exponent is all ones + assign uf_before_round = final_exponent == 0; // exponent for subnormals capped to 0 + + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign pre_round_sign = final_sign_q; + assign pre_round_exponent = (of_before_round) ? 2**EXP_BITS-2 : unsigned'(final_exponent[EXP_BITS-1:0]); + assign pre_round_mantissa = (of_before_round) ? '1 : final_mantissa[MAN_BITS:1]; // bit 0 is R bit + assign pre_round_abs = {pre_round_exponent, pre_round_mantissa}; + + // In case of overflow, the round and sticky bits are set for proper rounding + assign round_sticky_bits = (of_before_round) ? 2'b11 : {final_mantissa[0], sticky_after_norm}; + + // Perform the rounding + fpnew_rounding #( + .AbsWidth ( EXP_BITS + MAN_BITS ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( pre_round_sign ), + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( effective_subtraction_q ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) + ); + + // Classification after rounding + assign uf_after_round = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal + || ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && + ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_i == fpnew_pkg::RNE) || (rnd_mode_i == fpnew_pkg::RMM))))); + assign of_after_round = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // exponent all ones + + // ----------------- + // Result selection + // ----------------- + logic [WIDTH-1:0] regular_result; + fpnew_pkg::status_t regular_status; + + // Assemble regular result + assign regular_result = {rounded_sign, rounded_abs}; + assign regular_status.NV = 1'b0; // only valid cases are handled in regular path + assign regular_status.DZ = 1'b0; // no divisions + assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF + assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + + // Final results for output pipeline + fp_t result_d; + fpnew_pkg::status_t status_d; + + // Select output depending on special case detection + assign result_d = result_is_special_q ? special_result_q : regular_result; + assign status_d = result_is_special_q ? special_status_q : regular_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + fp_t [0:NUM_OUT_REGS] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + NUM_MID_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule +// ----- 8< ----- FILE "./fpnew_fma_multi.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + + + +module fpnew_fma_multi #( + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [2:0][WIDTH-1:0] operands_i, // 3 operands + input logic [NUM_FORMATS-1:0][2:0] is_boxed_i, // 3 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, // format of the multiplicands + input fpnew_pkg::fp_format_e dst_fmt_i, // format of the addend and result + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + // ---------- + // Constants + // ---------- + // The super-format that can hold all formats + localparam fpnew_pkg::fp_encoding_t SUPER_FORMAT = fpnew_pkg::super_format(FpFmtConfig); + + localparam int unsigned SUPER_EXP_BITS = SUPER_FORMAT.exp_bits; + localparam int unsigned SUPER_MAN_BITS = SUPER_FORMAT.man_bits; + + // Precision bits 'p' include the implicit bit + localparam int unsigned PRECISION_BITS = SUPER_MAN_BITS + 1; + // The lower 2p+3 bits of the internal FMA result will be needed for leading-zero detection + localparam int unsigned LOWER_SUM_WIDTH = 2 * PRECISION_BITS + 3; + localparam int unsigned LZC_RESULT_WIDTH = $clog2(LOWER_SUM_WIDTH); + // Internal exponent width of FMA must accomodate all meaningful exponent values in order to avoid + // datapath leakage. This is either given by the exponent bits or the width of the LZC result. + // In most reasonable FP formats the internal exponent will be wider than the LZC result. + localparam int unsigned EXP_WIDTH = fpnew_pkg::maximum(SUPER_EXP_BITS + 2, LZC_RESULT_WIDTH); + // Shift amount width: maximum internal mantissa size is 3p+4 bits + localparam int unsigned SHIFT_AMOUNT_WIDTH = $clog2(3 * PRECISION_BITS + 5); + // Pipelines + localparam NUM_INP_REGS = PipeConfig == fpnew_pkg::BEFORE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 3) // Second to get distributed regs + : 0); // no regs here otherwise + localparam NUM_MID_REGS = PipeConfig == fpnew_pkg::INSIDE + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 2) / 3) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 3) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [SUPER_EXP_BITS-1:0] exponent; + logic [SUPER_MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Selected pipeline output signals as non-arrays + logic [2:0][WIDTH-1:0] operands_q; + fpnew_pkg::fp_format_e src_fmt_q; + fpnew_pkg::fp_format_e dst_fmt_q; + + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][2:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][NUM_FORMATS-1:0][2:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_src_fmt_q; + fpnew_pkg::fp_format_e [0:NUM_INP_REGS] inp_pipe_dst_fmt_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_src_fmt_q[0] = src_fmt_i; + assign inp_pipe_dst_fmt_q[0] = dst_fmt_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_src_fmt_q[i+1], inp_pipe_src_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_dst_fmt_q[i+1], inp_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign operands_q = inp_pipe_operands_q[NUM_INP_REGS]; + assign src_fmt_q = inp_pipe_src_fmt_q[NUM_INP_REGS]; + assign dst_fmt_q = inp_pipe_dst_fmt_q[NUM_INP_REGS]; + + // ----------------- + // Input processing + // ----------------- + logic [NUM_FORMATS-1:0][2:0] fmt_sign; + logic signed [NUM_FORMATS-1:0][2:0][SUPER_EXP_BITS-1:0] fmt_exponent; + logic [NUM_FORMATS-1:0][2:0][SUPER_MAN_BITS-1:0] fmt_mantissa; + + fpnew_pkg::fp_info_t [NUM_FORMATS-1:0][2:0] info_q; + + // FP Input initialization + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : fmt_init_inputs + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + logic [2:0][FP_WIDTH-1:0] trimmed_ops; + + // Classify input + fpnew_classifier #( + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .NumOperands ( 3 ) + ) i_fpnew_classifier ( + .operands_i ( trimmed_ops ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS][fmt] ), + .info_o ( info_q[fmt] ) + ); + for (genvar op = 0; op < 3; op++) begin : gen_operands + assign trimmed_ops[op] = operands_q[op][FP_WIDTH-1:0]; + assign fmt_sign[fmt][op] = operands_q[op][FP_WIDTH-1]; + assign fmt_exponent[fmt][op] = signed'({1'b0, operands_q[op][MAN_BITS+:EXP_BITS]}); + assign fmt_mantissa[fmt][op] = {info_q[fmt][op].is_normal, operands_q[op][MAN_BITS-1:0]} << + (SUPER_MAN_BITS - MAN_BITS); // move to left of mantissa + end + end else begin : inactive_format + assign info_q[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_sign[fmt] = fpnew_pkg::DONT_CARE; // format disabled + assign fmt_exponent[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + assign fmt_mantissa[fmt] = '{default: fpnew_pkg::DONT_CARE}; // format disabled + end + end + + fp_t operand_a, operand_b, operand_c; + fpnew_pkg::fp_info_t info_a, info_b, info_c; + + // Operation selection and operand adjustment + // | \c op_q | \c op_mod_q | Operation Adjustment + // |:--------:|:-----------:|--------------------- + // | FMADD | \c 0 | FMADD: none + // | FMADD | \c 1 | FMSUB: Invert sign of operand C + // | FNMSUB | \c 0 | FNMSUB: Invert sign of operand A + // | FNMSUB | \c 1 | FNMADD: Invert sign of operands A and C + // | ADD | \c 0 | ADD: Set operand A to +1.0 + // | ADD | \c 1 | SUB: Set operand A to +1.0, invert sign of operand C + // | MUL | \c 0 | MUL: Set operand C to +0.0 or -0.0 depending on the rounding mode + // | *others* | \c - | *invalid* + // \note \c op_mod_q always inverts the sign of the addend. + always_comb begin : op_select + + // Default assignments - packing-order-agnostic + operand_a = {fmt_sign[src_fmt_q][0], fmt_exponent[src_fmt_q][0], fmt_mantissa[src_fmt_q][0]}; + operand_b = {fmt_sign[src_fmt_q][1], fmt_exponent[src_fmt_q][1], fmt_mantissa[src_fmt_q][1]}; + operand_c = {fmt_sign[dst_fmt_q][2], fmt_exponent[dst_fmt_q][2], fmt_mantissa[dst_fmt_q][2]}; + info_a = info_q[src_fmt_q][0]; + info_b = info_q[src_fmt_q][1]; + info_c = info_q[dst_fmt_q][2]; + + // op_mod_q inverts sign of operand C + operand_c.sign = operand_c.sign ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::FMADD: ; // do nothing + fpnew_pkg::FNMSUB: operand_a.sign = ~operand_a.sign; // invert sign of product + fpnew_pkg::ADD: begin // Set multiplicand to +1 + operand_a = '{sign: 1'b0, exponent: fpnew_pkg::bias(src_fmt_q), mantissa: '0}; + info_a = '{is_normal: 1'b1, is_boxed: 1'b1, default: 1'b0}; //normal, boxed value. + end + fpnew_pkg::MUL: begin // Set addend to +0 or -0, depending whether the rounding mode is RDN + if (inp_pipe_rnd_mode_q[NUM_INP_REGS] == fpnew_pkg::RDN) + operand_c = '{sign: 1'b0, exponent: '0, mantissa: '0}; + else + operand_c = '{sign: 1'b1, exponent: '0, mantissa: '0}; + info_c = '{is_zero: 1'b1, is_boxed: 1'b1, default: 1'b0}; //zero, boxed value. + end + default: begin // propagate don't cares + operand_a = '{default: fpnew_pkg::DONT_CARE}; + operand_b = '{default: fpnew_pkg::DONT_CARE}; + operand_c = '{default: fpnew_pkg::DONT_CARE}; + info_a = '{default: fpnew_pkg::DONT_CARE}; + info_b = '{default: fpnew_pkg::DONT_CARE}; + info_c = '{default: fpnew_pkg::DONT_CARE}; + end + endcase + end + + // --------------------- + // Input classification + // --------------------- + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + logic effective_subtraction; + logic tentative_sign; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf, info_c.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan, info_c.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling, info_c.is_signalling}); + // Effective subtraction in FMA occurs when product and addend signs differ + assign effective_subtraction = operand_a.sign ^ operand_b.sign ^ operand_c.sign; + // The tentative sign of the FMA shall be the sign of the product + assign tentative_sign = operand_a.sign ^ operand_b.sign; + + // ---------------------- + // Special case handling + // ---------------------- + logic [WIDTH-1:0] special_result; + fpnew_pkg::status_t special_status; + logic result_is_special; + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_special_result; + fpnew_pkg::status_t [NUM_FORMATS-1:0] fmt_special_status; + logic [NUM_FORMATS-1:0] fmt_result_is_special; + + + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_special_results + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + localparam logic [EXP_BITS-1:0] QNAN_EXPONENT = '1; + localparam logic [MAN_BITS-1:0] QNAN_MANTISSA = 2**(MAN_BITS-1); + localparam logic [MAN_BITS-1:0] ZERO_MANTISSA = '0; + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : special_results + logic [FP_WIDTH-1:0] special_res; + + // Default assignment + special_res = {1'b0, QNAN_EXPONENT, QNAN_MANTISSA}; // qNaN + fmt_special_status[fmt] = '0; + fmt_result_is_special[fmt] = 1'b0; + + // Handle potentially mixed nan & infinity input => important for the case where infinity and + // zero are multiplied and added to a qnan. + // RISC-V mandates raising the NV exception in these cases: + // (inf * 0) + c or (0 * inf) + c INVALID, no matter c (even quiet NaNs) + if ((info_a.is_inf && info_b.is_zero) || (info_a.is_zero && info_b.is_inf)) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN + fmt_special_status[fmt].NV = 1'b1; // invalid operation + // NaN Inputs cause canonical quiet NaN at the output and maybe invalid OP + end else if (any_operand_nan) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA, output is the canonical qNaN + fmt_special_status[fmt].NV = signalling_nan; // raise the invalid operation flag if signalling + // Special cases involving infinity + end else if (any_operand_inf) begin + fmt_result_is_special[fmt] = 1'b1; // bypass FMA + // Effective addition of opposite infinities (??inf - ??inf) is invalid! + if ((info_a.is_inf || info_b.is_inf) && info_c.is_inf && effective_subtraction) + fmt_special_status[fmt].NV = 1'b1; // invalid operation + // Handle cases where output will be inf because of inf product input + else if (info_a.is_inf || info_b.is_inf) begin + // Result is infinity with the sign of the product + special_res = {operand_a.sign ^ operand_b.sign, QNAN_EXPONENT, ZERO_MANTISSA}; + // Handle cases where the addend is inf + end else if (info_c.is_inf) begin + // Result is inifinity with sign of the addend (= operand_c) + special_res = {operand_c.sign, QNAN_EXPONENT, ZERO_MANTISSA}; + end + end + // Initialize special result with ones (NaN-box) + fmt_special_result[fmt] = '1; + fmt_special_result[fmt][FP_WIDTH-1:0] = special_res; + end + end else begin : inactive_format + assign fmt_special_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_special_status[fmt] = '0; + assign fmt_result_is_special[fmt] = 1'b0; + end + end + + // Detect special case from source format, I2F casts don't produce a special result + assign result_is_special = fmt_result_is_special[dst_fmt_q]; // they're all the same + // Signalling input NaNs raise invalid flag, otherwise no flags set + assign special_status = fmt_special_status[dst_fmt_q]; + // Assemble result according to destination format + assign special_result = fmt_special_result[dst_fmt_q]; // destination format + + // --------------------------- + // Initial exponent data path + // --------------------------- + logic signed [EXP_WIDTH-1:0] exponent_a, exponent_b, exponent_c; + logic signed [EXP_WIDTH-1:0] exponent_addend, exponent_product, exponent_difference; + logic signed [EXP_WIDTH-1:0] tentative_exponent; + + // Zero-extend exponents into signed container - implicit width extension + assign exponent_a = signed'({1'b0, operand_a.exponent}); + assign exponent_b = signed'({1'b0, operand_b.exponent}); + assign exponent_c = signed'({1'b0, operand_c.exponent}); + + // Calculate internal exponents from encoded values. Real exponents are (ex = Ex - bias + 1 - nx) + // with Ex the encoded exponent and nx the implicit bit. Internal exponents are biased to dst fmt. + assign exponent_addend = signed'(exponent_c + $signed({1'b0, ~info_c.is_normal})); // 0 as subnorm + // Biased product exponent is the sum of encoded exponents minus the bias. + assign exponent_product = (info_a.is_zero || info_b.is_zero) // in case the product is zero, set minimum exp. + ? 2 - signed'(fpnew_pkg::bias(dst_fmt_q)) + : signed'(exponent_a + info_a.is_subnormal + + exponent_b + info_b.is_subnormal + - 2*signed'(fpnew_pkg::bias(src_fmt_q)) + + signed'(fpnew_pkg::bias(dst_fmt_q))); // rebias for dst fmt + // Exponent difference is the addend exponent minus the product exponent + assign exponent_difference = exponent_addend - exponent_product; + // The tentative exponent will be the larger of the product or addend exponent + assign tentative_exponent = (exponent_difference > 0) ? exponent_addend : exponent_product; + + // Shift amount for addend based on exponents (unsigned as only right shifts) + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt; + + always_comb begin : addend_shift_amount + // Product-anchored case, saturated shift (addend is only in the sticky bit) + if (exponent_difference <= signed'(-2 * PRECISION_BITS - 1)) + addend_shamt = 3 * PRECISION_BITS + 4; + // Addend and product will have mutual bits to add + else if (exponent_difference <= signed'(PRECISION_BITS + 2)) + addend_shamt = unsigned'(signed'(PRECISION_BITS) + 3 - exponent_difference); + // Addend-anchored case, saturated shift (product is only in the sticky bit) + else + addend_shamt = 0; + end + + // ------------------ + // Product data path + // ------------------ + logic [PRECISION_BITS-1:0] mantissa_a, mantissa_b, mantissa_c; + logic [2*PRECISION_BITS-1:0] product; // the p*p product is 2p bits wide + logic [3*PRECISION_BITS+3:0] product_shifted; // addends are 3p+4 bit wide (including G/R) + + // Add implicit bits to mantissae + assign mantissa_a = {info_a.is_normal, operand_a.mantissa}; + assign mantissa_b = {info_b.is_normal, operand_b.mantissa}; + assign mantissa_c = {info_c.is_normal, operand_c.mantissa}; + + // Mantissa multiplier (a*b) + assign product = mantissa_a * mantissa_b; + + // Product is placed into a 3p+4 bit wide vector, padded with 2 bits for round and sticky: + // | 000...000 | product | RS | + // <- p+2 -> <- 2p -> < 2> + assign product_shifted = product << 2; // constant shift + + // ----------------- + // Addend data path + // ----------------- + logic [3*PRECISION_BITS+3:0] addend_after_shift; // upper 3p+4 bits are needed to go on + logic [PRECISION_BITS-1:0] addend_sticky_bits; // up to p bit of shifted addend are sticky + logic sticky_before_add; // they are compressed into a single sticky bit + logic [3*PRECISION_BITS+3:0] addend_shifted; // addends are 3p+4 bit wide (including G/R) + logic inject_carry_in; // inject carry for subtractions if needed + + // In parallel, the addend is right-shifted according to the exponent difference. Up to p bits are + // shifted out and compressed into a sticky bit. + // BEFORE THE SHIFT: + // | mantissa_c | 000..000 | + // <- p -> <- 3p+4 -> + // AFTER THE SHIFT: + // | 000..........000 | mantissa_c | 000...............0GR | sticky bits | + // <- addend_shamt -> <- p -> <- 2p+4-addend_shamt -> <- up to p -> + assign {addend_after_shift, addend_sticky_bits} = + (mantissa_c << (3 * PRECISION_BITS + 4)) >> addend_shamt; + + assign sticky_before_add = (| addend_sticky_bits); + + // In case of a subtraction, the addend is inverted + assign addend_shifted = (effective_subtraction) ? ~addend_after_shift : addend_after_shift; + assign inject_carry_in = effective_subtraction & ~sticky_before_add; + + // ------ + // Adder + // ------ + logic [3*PRECISION_BITS+4:0] sum_raw; // added one bit for the carry + logic sum_carry; // observe carry bit from sum for sign fixing + logic [3*PRECISION_BITS+3:0] sum; // discard carry as sum won't overflow + logic final_sign; + + //Mantissa adder (ab+c). In normal addition, it cannot overflow. + assign sum_raw = product_shifted + addend_shifted + inject_carry_in; + assign sum_carry = sum_raw[3*PRECISION_BITS+4]; + + // Complement negative sum (can only happen in subtraction -> overflows for positive results) + assign sum = (effective_subtraction && ~sum_carry) ? -sum_raw : sum_raw; + + // In case of a mispredicted subtraction result, do a sign flip + assign final_sign = (effective_subtraction && (sum_carry == tentative_sign)) + ? 1'b1 + : (effective_subtraction ? 1'b0 : tentative_sign); + + // --------------- + // Internal pipeline + // --------------- + // Pipeline output signals as non-arrays + logic effective_subtraction_q; + logic signed [EXP_WIDTH-1:0] exponent_product_q; + logic signed [EXP_WIDTH-1:0] exponent_difference_q; + logic signed [EXP_WIDTH-1:0] tentative_exponent_q; + logic [SHIFT_AMOUNT_WIDTH-1:0] addend_shamt_q; + logic sticky_before_add_q; + logic [3*PRECISION_BITS+3:0] sum_q; + logic final_sign_q; + fpnew_pkg::fp_format_e dst_fmt_q2; + fpnew_pkg::roundmode_e rnd_mode_q; + logic result_is_special_q; + fp_t special_result_q; + fpnew_pkg::status_t special_status_q; + // Internal pipeline signals, index i holds signal after i register stages + logic [0:NUM_MID_REGS] mid_pipe_eff_sub_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_prod_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_exp_diff_q; + logic signed [0:NUM_MID_REGS][EXP_WIDTH-1:0] mid_pipe_tent_exp_q; + logic [0:NUM_MID_REGS][SHIFT_AMOUNT_WIDTH-1:0] mid_pipe_add_shamt_q; + logic [0:NUM_MID_REGS] mid_pipe_sticky_q; + logic [0:NUM_MID_REGS][3*PRECISION_BITS+3:0] mid_pipe_sum_q; + logic [0:NUM_MID_REGS] mid_pipe_final_sign_q; + fpnew_pkg::roundmode_e [0:NUM_MID_REGS] mid_pipe_rnd_mode_q; + fpnew_pkg::fp_format_e [0:NUM_MID_REGS] mid_pipe_dst_fmt_q; + logic [0:NUM_MID_REGS] mid_pipe_res_is_spec_q; + fp_t [0:NUM_MID_REGS] mid_pipe_spec_res_q; + fpnew_pkg::status_t [0:NUM_MID_REGS] mid_pipe_spec_stat_q; + TagType [0:NUM_MID_REGS] mid_pipe_tag_q; + logic [0:NUM_MID_REGS] mid_pipe_mask_q; + AuxType [0:NUM_MID_REGS] mid_pipe_aux_q; + logic [0:NUM_MID_REGS] mid_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_MID_REGS] mid_pipe_ready; + + // Input stage: First element of pipeline is taken from upstream logic + assign mid_pipe_eff_sub_q[0] = effective_subtraction; + assign mid_pipe_exp_prod_q[0] = exponent_product; + assign mid_pipe_exp_diff_q[0] = exponent_difference; + assign mid_pipe_tent_exp_q[0] = tentative_exponent; + assign mid_pipe_add_shamt_q[0] = addend_shamt; + assign mid_pipe_sticky_q[0] = sticky_before_add; + assign mid_pipe_sum_q[0] = sum; + assign mid_pipe_final_sign_q[0] = final_sign; + assign mid_pipe_rnd_mode_q[0] = inp_pipe_rnd_mode_q[NUM_INP_REGS]; + assign mid_pipe_dst_fmt_q[0] = dst_fmt_q; + assign mid_pipe_res_is_spec_q[0] = result_is_special; + assign mid_pipe_spec_res_q[0] = special_result; + assign mid_pipe_spec_stat_q[0] = special_status; + assign mid_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign mid_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign mid_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign mid_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to input pipe + assign inp_pipe_ready[NUM_INP_REGS] = mid_pipe_ready[0]; + + // Generate the register stages + for (genvar i = 0; i < NUM_MID_REGS; i++) begin : gen_inside_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign mid_pipe_ready[i] = mid_pipe_ready[i+1] | ~mid_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(mid_pipe_valid_q[i+1], mid_pipe_valid_q[i], mid_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (mid_pipe_ready[i] & mid_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(mid_pipe_eff_sub_q[i+1], mid_pipe_eff_sub_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_prod_q[i+1], mid_pipe_exp_prod_q[i], reg_ena, '0) + `FFL(mid_pipe_exp_diff_q[i+1], mid_pipe_exp_diff_q[i], reg_ena, '0) + `FFL(mid_pipe_tent_exp_q[i+1], mid_pipe_tent_exp_q[i], reg_ena, '0) + `FFL(mid_pipe_add_shamt_q[i+1], mid_pipe_add_shamt_q[i], reg_ena, '0) + `FFL(mid_pipe_sticky_q[i+1], mid_pipe_sticky_q[i], reg_ena, '0) + `FFL(mid_pipe_sum_q[i+1], mid_pipe_sum_q[i], reg_ena, '0) + `FFL(mid_pipe_final_sign_q[i+1], mid_pipe_final_sign_q[i], reg_ena, '0) + `FFL(mid_pipe_rnd_mode_q[i+1], mid_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(mid_pipe_dst_fmt_q[i+1], mid_pipe_dst_fmt_q[i], reg_ena, fpnew_pkg::fp_format_e'(0)) + `FFL(mid_pipe_res_is_spec_q[i+1], mid_pipe_res_is_spec_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_res_q[i+1], mid_pipe_spec_res_q[i], reg_ena, '0) + `FFL(mid_pipe_spec_stat_q[i+1], mid_pipe_spec_stat_q[i], reg_ena, '0) + `FFL(mid_pipe_tag_q[i+1], mid_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(mid_pipe_mask_q[i+1], mid_pipe_mask_q[i], reg_ena, '0) + `FFL(mid_pipe_aux_q[i+1], mid_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: assign selected pipe outputs to signals for later use + assign effective_subtraction_q = mid_pipe_eff_sub_q[NUM_MID_REGS]; + assign exponent_product_q = mid_pipe_exp_prod_q[NUM_MID_REGS]; + assign exponent_difference_q = mid_pipe_exp_diff_q[NUM_MID_REGS]; + assign tentative_exponent_q = mid_pipe_tent_exp_q[NUM_MID_REGS]; + assign addend_shamt_q = mid_pipe_add_shamt_q[NUM_MID_REGS]; + assign sticky_before_add_q = mid_pipe_sticky_q[NUM_MID_REGS]; + assign sum_q = mid_pipe_sum_q[NUM_MID_REGS]; + assign final_sign_q = mid_pipe_final_sign_q[NUM_MID_REGS]; + assign rnd_mode_q = mid_pipe_rnd_mode_q[NUM_MID_REGS]; + assign dst_fmt_q2 = mid_pipe_dst_fmt_q[NUM_MID_REGS]; + assign result_is_special_q = mid_pipe_res_is_spec_q[NUM_MID_REGS]; + assign special_result_q = mid_pipe_spec_res_q[NUM_MID_REGS]; + assign special_status_q = mid_pipe_spec_stat_q[NUM_MID_REGS]; + + // -------------- + // Normalization + // -------------- + logic [LOWER_SUM_WIDTH-1:0] sum_lower; // lower 2p+3 bits of sum are searched + logic [LZC_RESULT_WIDTH-1:0] leading_zero_count; // the number of leading zeroes + logic signed [LZC_RESULT_WIDTH:0] leading_zero_count_sgn; // signed leading-zero count + logic lzc_zeroes; // in case only zeroes found + + logic [SHIFT_AMOUNT_WIDTH-1:0] norm_shamt; // Normalization shift amount + logic signed [EXP_WIDTH-1:0] normalized_exponent; + + logic [3*PRECISION_BITS+4:0] sum_shifted; // result after first normalization shift + logic [PRECISION_BITS:0] final_mantissa; // final mantissa before rounding with round bit + logic [2*PRECISION_BITS+2:0] sum_sticky_bits; // remaining 2p+3 sticky bits after normalization + logic sticky_after_norm; // sticky bit after normalization + + logic signed [EXP_WIDTH-1:0] final_exponent; + + assign sum_lower = sum_q[LOWER_SUM_WIDTH-1:0]; + + // Leading zero counter for cancellations + lzc #( + .WIDTH ( LOWER_SUM_WIDTH ), + .MODE ( 1 ) // MODE = 1 counts leading zeroes + ) i_lzc ( + .in_i ( sum_lower ), + .cnt_o ( leading_zero_count ), + .empty_o ( lzc_zeroes ) + ); + + assign leading_zero_count_sgn = signed'({1'b0, leading_zero_count}); + + // Normalization shift amount based on exponents and LZC (unsigned as only left shifts) + always_comb begin : norm_shift_amount + // Product-anchored case or cancellations require LZC + if ((exponent_difference_q <= 0) || (effective_subtraction_q && (exponent_difference_q <= 2))) begin + // Normal result (biased exponent > 0 and not a zero) + if ((exponent_product_q - leading_zero_count_sgn + 1 >= 0) && !lzc_zeroes) begin + // Undo initial product shift, remove the counted zeroes + norm_shamt = PRECISION_BITS + 2 + leading_zero_count; + normalized_exponent = exponent_product_q - leading_zero_count_sgn + 1; // account for shift + // Subnormal result + end else begin + // Cap the shift distance to align mantissa with minimum exponent + norm_shamt = unsigned'(signed'(PRECISION_BITS + 2 + exponent_product_q)); + normalized_exponent = 0; // subnormals encoded as 0 + end + // Addend-anchored case + end else begin + norm_shamt = addend_shamt_q; // Undo the initial shift + normalized_exponent = tentative_exponent_q; + end + end + + // Do the large normalization shift + assign sum_shifted = sum_q << norm_shamt; + + // The addend-anchored case needs a 1-bit normalization since the leading-one can be to the left + // or right of the (non-carry) MSB of the sum. + always_comb begin : small_norm + // Default assignment, discarding carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted; + final_exponent = normalized_exponent; + + // The normalized sum has overflown, align right and fix exponent + if (sum_shifted[3*PRECISION_BITS+4]) begin // check the carry bit + {final_mantissa, sum_sticky_bits} = sum_shifted >> 1; + final_exponent = normalized_exponent + 1; + // The normalized sum is normal, nothing to do + end else if (sum_shifted[3*PRECISION_BITS+3]) begin // check the sum MSB + // do nothing + // The normalized sum is still denormal, align left - unless the result is not already subnormal + end else if (normalized_exponent > 1) begin + {final_mantissa, sum_sticky_bits} = sum_shifted << 1; + final_exponent = normalized_exponent - 1; + // Otherwise we're denormal + end else begin + final_exponent = '0; + end + end + + // Update the sticky bit with the shifted-out bits + assign sticky_after_norm = (| {sum_sticky_bits}) | sticky_before_add_q; + + // ---------------------------- + // Rounding and classification + // ---------------------------- + logic pre_round_sign; + logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] pre_round_abs; // absolute value of result before rounding + logic [1:0] round_sticky_bits; + + logic of_before_round, of_after_round; // overflow + logic uf_before_round, uf_after_round; // underflow + + logic [NUM_FORMATS-1:0][SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] fmt_pre_round_abs; // per format + logic [NUM_FORMATS-1:0][1:0] fmt_round_sticky_bits; + + logic [NUM_FORMATS-1:0] fmt_of_after_round; + logic [NUM_FORMATS-1:0] fmt_uf_after_round; + + logic rounded_sign; + logic [SUPER_EXP_BITS+SUPER_MAN_BITS-1:0] rounded_abs; // absolute value of result after rounding + logic result_zero; + + // Classification before round. RISC-V mandates checking underflow AFTER rounding! + assign of_before_round = final_exponent >= 2**(fpnew_pkg::exp_bits(dst_fmt_q2))-1; // infinity exponent is all ones + assign uf_before_round = final_exponent == 0; // exponent for subnormals capped to 0 + + // Pack exponent and mantissa into proper rounding form + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_res_assemble + // Set up some constants + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + logic [EXP_BITS-1:0] pre_round_exponent; + logic [MAN_BITS-1:0] pre_round_mantissa; + + if (FpFmtConfig[fmt]) begin : active_format + + assign pre_round_exponent = (of_before_round) ? 2**EXP_BITS-2 : final_exponent[EXP_BITS-1:0]; + assign pre_round_mantissa = (of_before_round) ? '1 : final_mantissa[SUPER_MAN_BITS-:MAN_BITS]; + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign fmt_pre_round_abs[fmt] = {pre_round_exponent, pre_round_mantissa}; // 0-extend + + // Round bit is after mantissa (1 in case of overflow for rounding) + assign fmt_round_sticky_bits[fmt][1] = final_mantissa[SUPER_MAN_BITS-MAN_BITS] | + of_before_round; + + // remaining bits in mantissa to sticky (1 in case of overflow for rounding) + if (MAN_BITS < SUPER_MAN_BITS) begin : narrow_sticky + assign fmt_round_sticky_bits[fmt][0] = (| final_mantissa[SUPER_MAN_BITS-MAN_BITS-1:0]) | + sticky_after_norm | of_before_round; + end else begin : normal_sticky + assign fmt_round_sticky_bits[fmt][0] = sticky_after_norm | of_before_round; + end + end else begin : inactive_format + assign fmt_pre_round_abs[fmt] = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_round_sticky_bits[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Assemble result before rounding. In case of overflow, the largest normal value is set. + assign pre_round_sign = final_sign_q; + assign pre_round_abs = fmt_pre_round_abs[dst_fmt_q2]; + + // In case of overflow, the round and sticky bits are set for proper rounding + assign round_sticky_bits = fmt_round_sticky_bits[dst_fmt_q2]; + + // Perform the rounding + fpnew_rounding #( + .AbsWidth ( SUPER_EXP_BITS + SUPER_MAN_BITS ) + ) i_fpnew_rounding ( + .abs_value_i ( pre_round_abs ), + .sign_i ( pre_round_sign ), + .round_sticky_bits_i ( round_sticky_bits ), + .rnd_mode_i ( rnd_mode_q ), + .effective_subtraction_i ( effective_subtraction_q ), + .abs_rounded_o ( rounded_abs ), + .sign_o ( rounded_sign ), + .exact_zero_o ( result_zero ) + ); + + logic [NUM_FORMATS-1:0][WIDTH-1:0] fmt_result; + + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_sign_inject + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(fpnew_pkg::fp_format_e'(fmt)); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(fpnew_pkg::fp_format_e'(fmt)); + + if (FpFmtConfig[fmt]) begin : active_format + always_comb begin : post_process + // detect of / uf + fmt_uf_after_round[fmt] = (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) // denormal + || ((pre_round_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '0) && (rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == 1) && + ((round_sticky_bits != 2'b11) || (!sum_sticky_bits[MAN_BITS*2 + 4] && ((rnd_mode_i == fpnew_pkg::RNE) || (rnd_mode_i == fpnew_pkg::RMM))))); + fmt_of_after_round[fmt] = rounded_abs[EXP_BITS+MAN_BITS-1:MAN_BITS] == '1; // inf exp. + + // Assemble regular result, nan box short ones. + fmt_result[fmt] = '1; + fmt_result[fmt][FP_WIDTH-1:0] = {rounded_sign, rounded_abs[EXP_BITS+MAN_BITS-1:0]}; + end + end else begin : inactive_format + assign fmt_uf_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_of_after_round[fmt] = fpnew_pkg::DONT_CARE; + assign fmt_result[fmt] = '{default: fpnew_pkg::DONT_CARE}; + end + end + + // Classification after rounding select by destination format + assign uf_after_round = fmt_uf_after_round[dst_fmt_q2]; + assign of_after_round = fmt_of_after_round[dst_fmt_q2]; + + + // ----------------- + // Result selection + // ----------------- + logic [WIDTH-1:0] regular_result; + fpnew_pkg::status_t regular_status; + + // Assemble regular result + assign regular_result = fmt_result[dst_fmt_q2]; + assign regular_status.NV = 1'b0; // only valid cases are handled in regular path + assign regular_status.DZ = 1'b0; // no divisions + assign regular_status.OF = of_before_round | of_after_round; // rounding can introduce overflow + assign regular_status.UF = uf_after_round & regular_status.NX; // only inexact results raise UF + assign regular_status.NX = (| round_sticky_bits) | of_before_round | of_after_round; + + // Final results for output pipeline + logic [WIDTH-1:0] result_d; + fpnew_pkg::status_t status_d; + + // Select output depending on special case detection + assign result_d = result_is_special_q ? special_result_q : regular_result; + assign status_d = result_is_special_q ? special_status_q : regular_status; + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + logic [0:NUM_OUT_REGS][WIDTH-1:0] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_tag_q[0] = mid_pipe_tag_q[NUM_MID_REGS]; + assign out_pipe_mask_q[0] = mid_pipe_mask_q[NUM_MID_REGS]; + assign out_pipe_aux_q[0] = mid_pipe_aux_q[NUM_MID_REGS]; + assign out_pipe_valid_q[0] = mid_pipe_valid_q[NUM_MID_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign mid_pipe_ready[NUM_MID_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + NUM_MID_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = 1'b1; // always NaN-Box result + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, mid_pipe_valid_q, out_pipe_valid_q}); +endmodule +// ----- 8< ----- FILE "./fpnew_noncomp.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + + + +module fpnew_noncomp #( + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter type AuxType = logic, + // Do not change + localparam int unsigned WIDTH = fpnew_pkg::fp_width(FpFormat), + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [1:0][WIDTH-1:0] operands_i, // 2 operands + input logic [1:0] is_boxed_i, // 2 operands + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input TagType tag_i, + input logic mask_i, + input AuxType aux_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output fpnew_pkg::classmask_e class_mask_o, + output logic is_class_o, + output TagType tag_o, + output logic mask_o, + output AuxType aux_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + // ---------- + // Constants + // ---------- + localparam int unsigned EXP_BITS = fpnew_pkg::exp_bits(FpFormat); + localparam int unsigned MAN_BITS = fpnew_pkg::man_bits(FpFormat); + // Pipelines + localparam NUM_INP_REGS = (PipeConfig == fpnew_pkg::BEFORE || PipeConfig == fpnew_pkg::INSIDE) + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? ((NumPipeRegs + 1) / 2) // First to get distributed regs + : 0); // no regs here otherwise + localparam NUM_OUT_REGS = PipeConfig == fpnew_pkg::AFTER + ? NumPipeRegs + : (PipeConfig == fpnew_pkg::DISTRIBUTED + ? (NumPipeRegs / 2) // Last to get distributed regs + : 0); // no regs here otherwise + + // ---------------- + // Type definition + // ---------------- + typedef struct packed { + logic sign; + logic [EXP_BITS-1:0] exponent; + logic [MAN_BITS-1:0] mantissa; + } fp_t; + + // --------------- + // Input pipeline + // --------------- + // Input pipeline signals, index i holds signal after i register stages + logic [0:NUM_INP_REGS][1:0][WIDTH-1:0] inp_pipe_operands_q; + logic [0:NUM_INP_REGS][1:0] inp_pipe_is_boxed_q; + fpnew_pkg::roundmode_e [0:NUM_INP_REGS] inp_pipe_rnd_mode_q; + fpnew_pkg::operation_e [0:NUM_INP_REGS] inp_pipe_op_q; + logic [0:NUM_INP_REGS] inp_pipe_op_mod_q; + TagType [0:NUM_INP_REGS] inp_pipe_tag_q; + logic [0:NUM_INP_REGS] inp_pipe_mask_q; + AuxType [0:NUM_INP_REGS] inp_pipe_aux_q; + logic [0:NUM_INP_REGS] inp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_INP_REGS] inp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign inp_pipe_operands_q[0] = operands_i; + assign inp_pipe_is_boxed_q[0] = is_boxed_i; + assign inp_pipe_rnd_mode_q[0] = rnd_mode_i; + assign inp_pipe_op_q[0] = op_i; + assign inp_pipe_op_mod_q[0] = op_mod_i; + assign inp_pipe_tag_q[0] = tag_i; + assign inp_pipe_mask_q[0] = mask_i; + assign inp_pipe_aux_q[0] = aux_i; + assign inp_pipe_valid_q[0] = in_valid_i; + // Input stage: Propagate pipeline ready signal to updtream circuitry + assign in_ready_o = inp_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_INP_REGS; i++) begin : gen_input_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign inp_pipe_ready[i] = inp_pipe_ready[i+1] | ~inp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(inp_pipe_valid_q[i+1], inp_pipe_valid_q[i], inp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (inp_pipe_ready[i] & inp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(inp_pipe_operands_q[i+1], inp_pipe_operands_q[i], reg_ena, '0) + `FFL(inp_pipe_is_boxed_q[i+1], inp_pipe_is_boxed_q[i], reg_ena, '0) + `FFL(inp_pipe_rnd_mode_q[i+1], inp_pipe_rnd_mode_q[i], reg_ena, fpnew_pkg::RNE) + `FFL(inp_pipe_op_q[i+1], inp_pipe_op_q[i], reg_ena, fpnew_pkg::FMADD) + `FFL(inp_pipe_op_mod_q[i+1], inp_pipe_op_mod_q[i], reg_ena, '0) + `FFL(inp_pipe_tag_q[i+1], inp_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(inp_pipe_mask_q[i+1], inp_pipe_mask_q[i], reg_ena, '0) + `FFL(inp_pipe_aux_q[i+1], inp_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + + // --------------------- + // Input classification + // --------------------- + fpnew_pkg::fp_info_t [1:0] info_q; + + // Classify input + fpnew_classifier #( + .FpFormat ( FpFormat ), + .NumOperands ( 2 ) + ) i_class_a ( + .operands_i ( inp_pipe_operands_q[NUM_INP_REGS] ), + .is_boxed_i ( inp_pipe_is_boxed_q[NUM_INP_REGS] ), + .info_o ( info_q ) + ); + + fp_t operand_a, operand_b; + fpnew_pkg::fp_info_t info_a, info_b; + + // Packing-order-agnostic assignments + assign operand_a = inp_pipe_operands_q[NUM_INP_REGS][0]; + assign operand_b = inp_pipe_operands_q[NUM_INP_REGS][1]; + assign info_a = info_q[0]; + assign info_b = info_q[1]; + + logic any_operand_inf; + logic any_operand_nan; + logic signalling_nan; + + // Reduction for special case handling + assign any_operand_inf = (| {info_a.is_inf, info_b.is_inf}); + assign any_operand_nan = (| {info_a.is_nan, info_b.is_nan}); + assign signalling_nan = (| {info_a.is_signalling, info_b.is_signalling}); + + logic operands_equal, operand_a_smaller; + + // Equality checks for zeroes too + assign operands_equal = (operand_a == operand_b) || (info_a.is_zero && info_b.is_zero); + // Invert result if non-zero signs involved (unsigned comparison) + assign operand_a_smaller = (operand_a < operand_b) ^ (operand_a.sign || operand_b.sign); + + // --------------- + // Sign Injection + // --------------- + fp_t sgnj_result; + fpnew_pkg::status_t sgnj_status; + logic sgnj_extension_bit; + + // Sign Injection - operation is encoded in rnd_mode_q: + // RNE = SGNJ, RTZ = SGNJN, RDN = SGNJX, RUP = Passthrough (no NaN-box check) + always_comb begin : sign_injections + logic sign_a, sign_b; // internal signs + // Default assignment + sgnj_result = operand_a; // result based on operand a + + // NaN-boxing check will treat invalid inputs as canonical NaNs + if (!info_a.is_boxed) sgnj_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; + + // Internal signs are treated as positive in case of non-NaN-boxed values + sign_a = operand_a.sign & info_a.is_boxed; + sign_b = operand_b.sign & info_b.is_boxed; + + // Do the sign injection based on rm field + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: sgnj_result.sign = sign_b; // SGNJ + fpnew_pkg::RTZ: sgnj_result.sign = ~sign_b; // SGNJN + fpnew_pkg::RDN: sgnj_result.sign = sign_a ^ sign_b; // SGNJX + fpnew_pkg::RUP: sgnj_result = operand_a; // passthrough + default: sgnj_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + + assign sgnj_status = '0; // sign injections never raise exceptions + + // op_mod_q enables integer sign-extension of result (for storing to integer regfile) + assign sgnj_extension_bit = inp_pipe_op_mod_q[NUM_INP_REGS] ? sgnj_result.sign : 1'b1; + + // ------------------ + // Minimum / Maximum + // ------------------ + fp_t minmax_result; + fpnew_pkg::status_t minmax_status; + logic minmax_extension_bit; + + // Minimum/Maximum - operation is encoded in rnd_mode_q: + // RNE = MIN, RTZ = MAX + always_comb begin : min_max + // Default assignment + minmax_status = '0; + + // Min/Max use quiet comparisons - only sNaN are invalid + minmax_status.NV = signalling_nan; + + // Both NaN inputs cause a NaN output + if (info_a.is_nan && info_b.is_nan) + minmax_result = '{sign: 1'b0, exponent: '1, mantissa: 2**(MAN_BITS-1)}; // canonical qNaN + // If one operand is NaN, the non-NaN operand is returned + else if (info_a.is_nan) minmax_result = operand_b; + else if (info_b.is_nan) minmax_result = operand_a; + // Otherwise decide according to the operation + else begin + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: minmax_result = operand_a_smaller ? operand_a : operand_b; // MIN + fpnew_pkg::RTZ: minmax_result = operand_a_smaller ? operand_b : operand_a; // MAX + default: minmax_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + end + + assign minmax_extension_bit = 1'b1; // NaN-box as result is always a float value + + // ------------ + // Comparisons + // ------------ + fp_t cmp_result; + fpnew_pkg::status_t cmp_status; + logic cmp_extension_bit; + + // Comparisons - operation is encoded in rnd_mode_q: + // RNE = LE, RTZ = LT, RDN = EQ + // op_mod_q inverts boolean outputs + always_comb begin : comparisons + // Default assignment + cmp_result = '0; // false + cmp_status = '0; // no flags + + // Signalling NaNs always compare as false and are illegal + if (signalling_nan) cmp_status.NV = 1'b1; // invalid operation + // Otherwise do comparisons + else begin + unique case (inp_pipe_rnd_mode_q[NUM_INP_REGS]) + fpnew_pkg::RNE: begin // Less than or equal + if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid + else cmp_result = (operand_a_smaller | operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + fpnew_pkg::RTZ: begin // Less than + if (any_operand_nan) cmp_status.NV = 1'b1; // Signalling comparison: NaNs are invalid + else cmp_result = (operand_a_smaller & ~operands_equal) ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + fpnew_pkg::RDN: begin // Equal + if (any_operand_nan) cmp_result = inp_pipe_op_mod_q[NUM_INP_REGS]; // NaN always not equal + else cmp_result = operands_equal ^ inp_pipe_op_mod_q[NUM_INP_REGS]; + end + default: cmp_result = '{default: fpnew_pkg::DONT_CARE}; // don't care + endcase + end + end + + assign cmp_extension_bit = 1'b0; // Comparisons always produce booleans in integer registers + + // --------------- + // Classification + // --------------- + fpnew_pkg::status_t class_status; + logic class_extension_bit; + fpnew_pkg::classmask_e class_mask_d; // the result is actually here + + // Classification - always return the classification mask on the dedicated port + always_comb begin : classify + if (info_a.is_normal) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGNORM : fpnew_pkg::POSNORM; + end else if (info_a.is_subnormal) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGSUBNORM : fpnew_pkg::POSSUBNORM; + end else if (info_a.is_zero) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGZERO : fpnew_pkg::POSZERO; + end else if (info_a.is_inf) begin + class_mask_d = operand_a.sign ? fpnew_pkg::NEGINF : fpnew_pkg::POSINF; + end else if (info_a.is_nan) begin + class_mask_d = info_a.is_signalling ? fpnew_pkg::SNAN : fpnew_pkg::QNAN; + end else begin + class_mask_d = fpnew_pkg::QNAN; // default value + end + end + + assign class_status = '0; // classification does not set flags + assign class_extension_bit = 1'b0; // classification always produces results in integer registers + + // ----------------- + // Result selection + // ----------------- + fp_t result_d; + fpnew_pkg::status_t status_d; + logic extension_bit_d; + logic is_class_d; + + // Select result + always_comb begin : select_result + unique case (inp_pipe_op_q[NUM_INP_REGS]) + fpnew_pkg::SGNJ: begin + result_d = sgnj_result; + status_d = sgnj_status; + extension_bit_d = sgnj_extension_bit; + end + fpnew_pkg::MINMAX: begin + result_d = minmax_result; + status_d = minmax_status; + extension_bit_d = minmax_extension_bit; + end + fpnew_pkg::CMP: begin + result_d = cmp_result; + status_d = cmp_status; + extension_bit_d = cmp_extension_bit; + end + fpnew_pkg::CLASSIFY: begin + result_d = '{default: fpnew_pkg::DONT_CARE}; // unused + status_d = class_status; + extension_bit_d = class_extension_bit; + end + default: begin + result_d = '{default: fpnew_pkg::DONT_CARE}; // dont care + status_d = '{default: fpnew_pkg::DONT_CARE}; // dont care + extension_bit_d = fpnew_pkg::DONT_CARE; // dont care + end + endcase + end + + assign is_class_d = (inp_pipe_op_q[NUM_INP_REGS] == fpnew_pkg::CLASSIFY); + + // ---------------- + // Output Pipeline + // ---------------- + // Output pipeline signals, index i holds signal after i register stages + fp_t [0:NUM_OUT_REGS] out_pipe_result_q; + fpnew_pkg::status_t [0:NUM_OUT_REGS] out_pipe_status_q; + logic [0:NUM_OUT_REGS] out_pipe_extension_bit_q; + fpnew_pkg::classmask_e [0:NUM_OUT_REGS] out_pipe_class_mask_q; + logic [0:NUM_OUT_REGS] out_pipe_is_class_q; + TagType [0:NUM_OUT_REGS] out_pipe_tag_q; + logic [0:NUM_OUT_REGS] out_pipe_mask_q; + AuxType [0:NUM_OUT_REGS] out_pipe_aux_q; + logic [0:NUM_OUT_REGS] out_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NUM_OUT_REGS] out_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign out_pipe_result_q[0] = result_d; + assign out_pipe_status_q[0] = status_d; + assign out_pipe_extension_bit_q[0] = extension_bit_d; + assign out_pipe_class_mask_q[0] = class_mask_d; + assign out_pipe_is_class_q[0] = is_class_d; + assign out_pipe_tag_q[0] = inp_pipe_tag_q[NUM_INP_REGS]; + assign out_pipe_mask_q[0] = inp_pipe_mask_q[NUM_INP_REGS]; + assign out_pipe_aux_q[0] = inp_pipe_aux_q[NUM_INP_REGS]; + assign out_pipe_valid_q[0] = inp_pipe_valid_q[NUM_INP_REGS]; + // Input stage: Propagate pipeline ready signal to inside pipe + assign inp_pipe_ready[NUM_INP_REGS] = out_pipe_ready[0]; + // Generate the register stages + for (genvar i = 0; i < NUM_OUT_REGS; i++) begin : gen_output_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign out_pipe_ready[i] = out_pipe_ready[i+1] | ~out_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(out_pipe_valid_q[i+1], out_pipe_valid_q[i], out_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (out_pipe_ready[i] & out_pipe_valid_q[i]) | reg_ena_i[NUM_INP_REGS + i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(out_pipe_result_q[i+1], out_pipe_result_q[i], reg_ena, '0) + `FFL(out_pipe_status_q[i+1], out_pipe_status_q[i], reg_ena, '0) + `FFL(out_pipe_extension_bit_q[i+1], out_pipe_extension_bit_q[i], reg_ena, '0) + `FFL(out_pipe_class_mask_q[i+1], out_pipe_class_mask_q[i], reg_ena, fpnew_pkg::QNAN) + `FFL(out_pipe_is_class_q[i+1], out_pipe_is_class_q[i], reg_ena, '0) + `FFL(out_pipe_tag_q[i+1], out_pipe_tag_q[i], reg_ena, TagType'('0)) + `FFL(out_pipe_mask_q[i+1], out_pipe_mask_q[i], reg_ena, '0) + `FFL(out_pipe_aux_q[i+1], out_pipe_aux_q[i], reg_ena, AuxType'('0)) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign out_pipe_ready[NUM_OUT_REGS] = out_ready_i; + // Output stage: assign module outputs + assign result_o = out_pipe_result_q[NUM_OUT_REGS]; + assign status_o = out_pipe_status_q[NUM_OUT_REGS]; + assign extension_bit_o = out_pipe_extension_bit_q[NUM_OUT_REGS]; + assign class_mask_o = out_pipe_class_mask_q[NUM_OUT_REGS]; + assign is_class_o = out_pipe_is_class_q[NUM_OUT_REGS]; + assign tag_o = out_pipe_tag_q[NUM_OUT_REGS]; + assign mask_o = out_pipe_mask_q[NUM_OUT_REGS]; + assign aux_o = out_pipe_aux_q[NUM_OUT_REGS]; + assign out_valid_o = out_pipe_valid_q[NUM_OUT_REGS]; + assign busy_o = (| {inp_pipe_valid_q, out_pipe_valid_q}); +endmodule +// ----- 8< ----- FILE "./fpnew_opgroup_block.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_opgroup_block #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::ADDMUL, + // FPU configuration + parameter int unsigned Width = 32, + parameter logic EnableVectors = 1'b1, + parameter logic PulpDivsqrt = 1'b1, + parameter fpnew_pkg::fmt_logic_t FpFmtMask = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtMask = '1, + parameter fpnew_pkg::fmt_unsigned_t FmtPipeRegs = '{default: 0}, + parameter fpnew_pkg::fmt_unit_types_t FmtUnitTypes = '{default: fpnew_pkg::PARALLEL}, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + // Do not change + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtMask, EnableVectors), + localparam type MaskType = logic [NUM_LANES-1:0] +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + // ---------------- + // Type Definition + // ---------------- + typedef struct packed { + logic [Width-1:0] result; + fpnew_pkg::status_t status; + logic ext_bit; + TagType tag; + } output_t; + + // Handshake signals for the slices + logic [NUM_FORMATS-1:0] fmt_in_ready, fmt_out_valid, fmt_out_ready, fmt_busy; + output_t [NUM_FORMATS-1:0] fmt_outputs; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = in_valid_i & fmt_in_ready[dst_fmt_i]; // Ready is given by selected format + + // ------------------------- + // Generate Parallel Slices + // ------------------------- + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_parallel_slices + // Some constants for this format + localparam logic ANY_MERGED = fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam logic IS_FIRST_MERGED = + fpnew_pkg::is_first_enabled_multi(fpnew_pkg::fp_format_e'(fmt), FmtUnitTypes, FpFmtMask); + + // Generate slice only if format enabled + if (FpFmtMask[fmt] && (FmtUnitTypes[fmt] == fpnew_pkg::PARALLEL)) begin : active_format + + logic in_valid; + + assign in_valid = in_valid_i & (dst_fmt_i == fmt); // enable selected format + + // Forward masks related to the right SIMD lane + localparam int unsigned INTERNAL_LANES = fpnew_pkg::num_lanes(Width, fpnew_pkg::fp_format_e'(fmt), EnableVectors); + logic [INTERNAL_LANES-1:0] mask_slice; + always_comb for (int b = 0; b < INTERNAL_LANES; b++) mask_slice[b] = simd_mask_i[(NUM_LANES/INTERNAL_LANES)*b]; + + fpnew_opgroup_fmt_slice #( + .OpGroup ( OpGroup ), + .FpFormat ( fpnew_pkg::fp_format_e'(fmt) ), + .Width ( Width ), + .EnableVectors ( EnableVectors ), + .NumPipeRegs ( FmtPipeRegs[fmt] ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) + ) i_fmt_slice ( + .clk_i, + .rst_ni, + .operands_i ( operands_i ), + .is_boxed_i ( is_boxed_i[fmt] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( mask_slice ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[fmt] ), + .flush_i, + .result_o ( fmt_outputs[fmt].result ), + .status_o ( fmt_outputs[fmt].status ), + .extension_bit_o( fmt_outputs[fmt].ext_bit ), + .tag_o ( fmt_outputs[fmt].tag ), + .out_valid_o ( fmt_out_valid[fmt] ), + .out_ready_i ( fmt_out_ready[fmt] ), + .busy_o ( fmt_busy[fmt] ), + .reg_ena_i ( '0 ) + ); + // If the format wants to use merged ops, tie off the dangling ones not used here + end else if (FpFmtMask[fmt] && ANY_MERGED && !IS_FIRST_MERGED) begin : merged_unused + + localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + // Ready is split up into formats + assign fmt_in_ready[fmt] = fmt_in_ready[int'(FMT)]; + + assign fmt_out_valid[fmt] = 1'b0; // don't emit values + assign fmt_busy[fmt] = 1'b0; // never busy + // Outputs are don't care + assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; + assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); + + // Tie off disabled formats + end else if (!FpFmtMask[fmt] || (FmtUnitTypes[fmt] == fpnew_pkg::DISABLED)) begin : disable_fmt + assign fmt_in_ready[fmt] = 1'b0; // don't accept operations + assign fmt_out_valid[fmt] = 1'b0; // don't emit values + assign fmt_busy[fmt] = 1'b0; // never busy + // Outputs are don't care + assign fmt_outputs[fmt].result = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].status = '{default: fpnew_pkg::DONT_CARE}; + assign fmt_outputs[fmt].ext_bit = fpnew_pkg::DONT_CARE; + assign fmt_outputs[fmt].tag = TagType'(fpnew_pkg::DONT_CARE); + end + end + + // ---------------------- + // Generate Merged Slice + // ---------------------- + if (fpnew_pkg::any_enabled_multi(FmtUnitTypes, FpFmtMask)) begin : gen_merged_slice + + localparam FMT = fpnew_pkg::get_first_enabled_multi(FmtUnitTypes, FpFmtMask); + localparam REG = fpnew_pkg::get_num_regs_multi(FmtPipeRegs, FmtUnitTypes, FpFmtMask); + + logic in_valid; + + assign in_valid = in_valid_i & (FmtUnitTypes[dst_fmt_i] == fpnew_pkg::MERGED); + + fpnew_opgroup_multifmt_slice #( + .OpGroup ( OpGroup ), + .Width ( Width ), + .FpFmtConfig ( FpFmtMask ), + .IntFmtConfig ( IntFmtMask ), + .EnableVectors ( EnableVectors ), + .PulpDivsqrt ( PulpDivsqrt ), + .NumPipeRegs ( REG ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ) + ) i_multifmt_slice ( + .clk_i, + .rst_ni, + .operands_i, + .is_boxed_i, + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( simd_mask_i ), + .in_valid_i ( in_valid ), + .in_ready_o ( fmt_in_ready[FMT] ), + .flush_i, + .result_o ( fmt_outputs[FMT].result ), + .status_o ( fmt_outputs[FMT].status ), + .extension_bit_o ( fmt_outputs[FMT].ext_bit ), + .tag_o ( fmt_outputs[FMT].tag ), + .out_valid_o ( fmt_out_valid[FMT] ), + .out_ready_i ( fmt_out_ready[FMT] ), + .busy_o ( fmt_busy[FMT] ), + .reg_ena_i ( '0 ) + ); + + end + + // ------------------ + // Arbitrate Outputs + // ------------------ + output_t arbiter_output; + + // Round-Robin arbiter to decide which result to use + rr_arb_tree #( + .NumIn ( NUM_FORMATS ), + .DataType ( output_t ), + .AxiVldRdy ( 1'b1 ) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ( '0 ), + .req_i ( fmt_out_valid ), + .gnt_o ( fmt_out_ready ), + .data_i ( fmt_outputs ), + .gnt_i ( out_ready_i ), + .req_o ( out_valid_o ), + .data_o ( arbiter_output ), + .idx_o ( /* unused */ ) + ); + + // Unpack output + assign result_o = arbiter_output.result; + assign status_o = arbiter_output.status; + assign extension_bit_o = arbiter_output.ext_bit; + assign tag_o = arbiter_output.tag; + + assign busy_o = (| fmt_busy); + +endmodule +// ----- 8< ----- FILE "./fpnew_opgroup_fmt_slice.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_opgroup_fmt_slice #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::ADDMUL, + parameter fpnew_pkg::fp_format_e FpFormat = fpnew_pkg::fp_format_e'(0), + // FPU configuration + parameter int unsigned Width = 32, + parameter logic EnableVectors = 1'b1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter logic ExtRegEna = 1'b0, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + // Do not change + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_LANES = fpnew_pkg::num_lanes(Width, FpFormat, EnableVectors), + localparam type MaskType = logic [NUM_LANES-1:0], + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(FpFormat); + localparam int unsigned SIMD_WIDTH = unsigned'(Width/NUM_LANES); + + + logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid; // Handshake signals for the lanes + logic vectorial_op; + + logic [NUM_LANES*FP_WIDTH-1:0] slice_result; + logic [Width-1:0] slice_regular_result, slice_class_result, slice_vec_class_result; + + fpnew_pkg::status_t [NUM_LANES-1:0] lane_status; + logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used + fpnew_pkg::classmask_e [NUM_LANES-1:0] lane_class_mask; + TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used + logic [NUM_LANES-1:0] lane_masks; + logic [NUM_LANES-1:0] lane_vectorial, lane_busy, lane_is_class; // dito + + logic result_is_vector, result_is_class; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane + assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled + + // --------------- + // Generate Lanes + // --------------- + for (genvar lane = 0; lane < int'(NUM_LANES); lane++) begin : gen_num_lanes + logic [FP_WIDTH-1:0] local_result; // lane-local results + logic local_sign; + + // Generate instances only if needed, lane 0 always generated + if ((lane == 0) || EnableVectors) begin : active_lane + logic in_valid, out_valid, out_ready; // lane-local handshake + + logic [NUM_OPERANDS-1:0][FP_WIDTH-1:0] local_operands; // lane-local operands + logic [FP_WIDTH-1:0] op_result; // lane-local results + fpnew_pkg::status_t op_status; + + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors + // Slice out the operands for this lane + always_comb begin : prepare_input + for (int i = 0; i < int'(NUM_OPERANDS); i++) begin + local_operands[i] = operands_i[i][(unsigned'(lane)+1)*FP_WIDTH-1:unsigned'(lane)*FP_WIDTH]; + end + end + + // Instantiate the operation from the selected opgroup + if (OpGroup == fpnew_pkg::ADDMUL) begin : lane_instance + fpnew_fma #( + .FpFormat ( FpFormat ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic ) + ) i_fma ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + assign lane_is_class[lane] = 1'b0; + assign lane_class_mask[lane] = fpnew_pkg::NEGINF; + end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance + // fpnew_divsqrt #( + // .FpFormat (FpFormat), + // .NumPipeRegs(NumPipeRegs), + // .PipeConfig (PipeConfig), + // .TagType (TagType), + // .AuxType (logic) + // ) i_divsqrt ( + // .clk_i, + // .rst_ni, + // .operands_i ( local_operands ), + // .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + // .rnd_mode_i, + // .op_i, + // .op_mod_i, + // .tag_i, + // .aux_i ( vectorial_op ), // Remember whether operation was vectorial + // .in_valid_i ( in_valid ), + // .in_ready_o ( lane_in_ready[lane] ), + // .flush_i, + // .result_o ( op_result ), + // .status_o ( op_status ), + // .extension_bit_o ( lane_ext_bit[lane] ), + // .tag_o ( lane_tags[lane] ), + // .aux_o ( lane_vectorial[lane] ), + // .out_valid_o ( out_valid ), + // .out_ready_i ( out_ready ), + // .busy_o ( lane_busy[lane] ), + // .reg_ena_i + // ); + // assign lane_is_class[lane] = 1'b0; + end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance + fpnew_noncomp #( + .FpFormat (FpFormat), + .NumPipeRegs(NumPipeRegs), + .PipeConfig (PipeConfig), + .TagType (TagType), + .AuxType (logic) + ) i_noncomp ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i ( is_boxed_i[NUM_OPERANDS-1:0] ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( vectorial_op ), // Remember whether operation was vectorial + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .class_mask_o ( lane_class_mask[lane] ), + .is_class_o ( lane_is_class[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_vectorial[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + end // ADD OTHER OPTIONS HERE + + // Handshakes are only done if the lane is actually used + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + + // Properly NaN-box or sign-extend the slice result if not in use + assign local_result = (lane_out_valid[lane] | ExtRegEna) ? op_result : '{default: lane_ext_bit[0]}; + assign lane_status[lane] = (lane_out_valid[lane] | ExtRegEna) ? op_status : '0; + + // Otherwise generate constant sign-extension + end else begin + assign lane_out_valid[lane] = 1'b0; // unused lane + assign lane_in_ready[lane] = 1'b0; // unused lane + assign local_result = '{default: lane_ext_bit[0]}; // sign-extend/nan box + assign lane_status[lane] = '0; + assign lane_busy[lane] = 1'b0; + assign lane_is_class[lane] = 1'b0; + end + + // Insert lane result into slice result + assign slice_result[(unsigned'(lane)+1)*FP_WIDTH-1:unsigned'(lane)*FP_WIDTH] = local_result; + + // Create Classification results + if (TrueSIMDClass && SIMD_WIDTH >= 10) begin : vectorial_true_class // true vectorial class blocks are 10bits in size + assign slice_vec_class_result[lane*SIMD_WIDTH +: 10] = lane_class_mask[lane]; + assign slice_vec_class_result[(lane+1)*SIMD_WIDTH-1 -: SIMD_WIDTH-10] = '0; + end else if ((lane+1)*8 <= Width) begin : vectorial_class // vectorial class blocks are 8bits in size + assign local_sign = (lane_class_mask[lane] == fpnew_pkg::NEGINF || + lane_class_mask[lane] == fpnew_pkg::NEGNORM || + lane_class_mask[lane] == fpnew_pkg::NEGSUBNORM || + lane_class_mask[lane] == fpnew_pkg::NEGZERO); + // Write the current block segment + assign slice_vec_class_result[(lane+1)*8-1:lane*8] = { + local_sign, // BIT 7 + ~local_sign, // BIT 6 + lane_class_mask[lane] == fpnew_pkg::QNAN, // BIT 5 + lane_class_mask[lane] == fpnew_pkg::SNAN, // BIT 4 + lane_class_mask[lane] == fpnew_pkg::POSZERO + || lane_class_mask[lane] == fpnew_pkg::NEGZERO, // BIT 3 + lane_class_mask[lane] == fpnew_pkg::POSSUBNORM + || lane_class_mask[lane] == fpnew_pkg::NEGSUBNORM, // BIT 2 + lane_class_mask[lane] == fpnew_pkg::POSNORM + || lane_class_mask[lane] == fpnew_pkg::NEGNORM, // BIT 1 + lane_class_mask[lane] == fpnew_pkg::POSINF + || lane_class_mask[lane] == fpnew_pkg::NEGINF // BIT 0 + }; + end + end + + // ------------ + // Output Side + // ------------ + assign result_is_vector = lane_vectorial[0]; + assign result_is_class = lane_is_class[0]; + + assign slice_regular_result = $signed({extension_bit_o, slice_result}); + + localparam int unsigned CLASS_VEC_BITS = (NUM_LANES*8 > Width) ? 8 * (Width / 8) : NUM_LANES*8; + + // Pad out unused vec_class bits if each classify result is on 8 bits + if (!(TrueSIMDClass && SIMD_WIDTH >= 10)) begin + if (CLASS_VEC_BITS < Width) begin : pad_vectorial_class + assign slice_vec_class_result[Width-1:CLASS_VEC_BITS] = '0; + end + end + + // localparam logic [Width-1:0] CLASS_VEC_MASK = 2**CLASS_VEC_BITS - 1; + + assign slice_class_result = result_is_vector ? slice_vec_class_result : lane_class_mask[0]; + + // Select the proper result + assign result_o = result_is_class ? slice_class_result : slice_regular_result; + + assign extension_bit_o = lane_ext_bit[0]; // upper lanes unused + assign tag_o = lane_tags[0]; // upper lanes unused + assign busy_o = (| lane_busy); + assign out_valid_o = lane_out_valid[0]; // upper lanes unused + + + // Collapse the lane status + always_comb begin : output_processing + // Collapse the status + automatic fpnew_pkg::status_t temp_status; + temp_status = '0; + for (int i = 0; i < int'(NUM_LANES); i++) + temp_status |= lane_status[i] & {5{lane_masks[i]}}; + status_o = temp_status; + end +endmodule +// ----- 8< ----- FILE "./fpnew_opgroup_multifmt_slice.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + + + +module fpnew_opgroup_multifmt_slice #( + parameter fpnew_pkg::opgroup_e OpGroup = fpnew_pkg::CONV, + parameter int unsigned Width = 64, + // FPU configuration + parameter fpnew_pkg::fmt_logic_t FpFmtConfig = '1, + parameter fpnew_pkg::ifmt_logic_t IntFmtConfig = '1, + parameter logic EnableVectors = 1'b1, + parameter logic PulpDivsqrt = 1'b1, + parameter int unsigned NumPipeRegs = 0, + parameter fpnew_pkg::pipe_config_t PipeConfig = fpnew_pkg::BEFORE, + parameter logic ExtRegEna = 1'b0, + parameter type TagType = logic, + // Do not change + localparam int unsigned NUM_OPERANDS = fpnew_pkg::num_operands(OpGroup), + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS, + localparam int unsigned NUM_SIMD_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, EnableVectors), + localparam type MaskType = logic [NUM_SIMD_LANES-1:0], + localparam int unsigned ExtRegEnaWidth = NumPipeRegs == 0 ? 1 : NumPipeRegs +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][Width-1:0] operands_i, + input logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [Width-1:0] result_o, + output fpnew_pkg::status_t status_o, + output logic extension_bit_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o, + // External register enable override + input logic [ExtRegEnaWidth-1:0] reg_ena_i +); + + if ((OpGroup == fpnew_pkg::DIVSQRT) && !PulpDivsqrt && + !((FpFmtConfig[0] == 1) && (FpFmtConfig[1:NUM_FORMATS-1] == '0))) begin + $fatal(1, "T-Head-based DivSqrt unit supported only in FP32-only configurations. \ +Set PulpDivsqrt to 1 not to use the PULP DivSqrt unit \ +or set Features.FpFmtMask to support only FP32"); + end + + localparam int unsigned MAX_FP_WIDTH = fpnew_pkg::max_fp_width(FpFmtConfig); + localparam int unsigned MAX_INT_WIDTH = fpnew_pkg::max_int_width(IntFmtConfig); + localparam int unsigned NUM_LANES = fpnew_pkg::max_num_lanes(Width, FpFmtConfig, 1'b1); + localparam int unsigned NUM_INT_FORMATS = fpnew_pkg::NUM_INT_FORMATS; + // We will send the format information along with the data + localparam int unsigned FMT_BITS = + fpnew_pkg::maximum($clog2(NUM_FORMATS), $clog2(NUM_INT_FORMATS)); + localparam int unsigned AUX_BITS = FMT_BITS + 2; // also add vectorial and integer flags + + logic [NUM_LANES-1:0] lane_in_ready, lane_out_valid, divsqrt_done, divsqrt_ready; // Handshake signals for the lanes + logic vectorial_op; + logic [FMT_BITS-1:0] dst_fmt; // destination format to pass along with operation + logic [AUX_BITS-1:0] aux_data; + + // additional flags for CONV + logic dst_fmt_is_int, dst_is_cpk; + logic [1:0] dst_vec_op; // info for vectorial results (for packing) + logic [2:0] target_aux_d; + logic is_up_cast, is_down_cast; + + logic [NUM_FORMATS-1:0][Width-1:0] fmt_slice_result; + logic [NUM_INT_FORMATS-1:0][Width-1:0] ifmt_slice_result; + + logic [Width-1:0] conv_target_d, conv_target_q; // vectorial conversions update a register + + fpnew_pkg::status_t [NUM_LANES-1:0] lane_status; + logic [NUM_LANES-1:0] lane_ext_bit; // only the first one is actually used + TagType [NUM_LANES-1:0] lane_tags; // only the first one is actually used + logic [NUM_LANES-1:0] lane_masks; + logic [NUM_LANES-1:0][AUX_BITS-1:0] lane_aux; // only the first one is actually used + logic [NUM_LANES-1:0] lane_busy; // dito + + logic result_is_vector; + logic [FMT_BITS-1:0] result_fmt; + logic result_fmt_is_int, result_is_cpk; + logic [1:0] result_vec_op; // info for vectorial results (for packing) + + logic simd_synch_rdy, simd_synch_done; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = lane_in_ready[0]; // Upstream ready is given by first lane + assign vectorial_op = vectorial_op_i & EnableVectors; // only do vectorial stuff if enabled + + // Cast-and-Pack ops are encoded in operation and modifier + assign dst_fmt_is_int = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::F2I); + assign dst_is_cpk = (OpGroup == fpnew_pkg::CONV) & (op_i == fpnew_pkg::CPKAB || + op_i == fpnew_pkg::CPKCD); + assign dst_vec_op = (OpGroup == fpnew_pkg::CONV) & {(op_i == fpnew_pkg::CPKCD), op_mod_i}; + + assign is_up_cast = (fpnew_pkg::fp_width(dst_fmt_i) > fpnew_pkg::fp_width(src_fmt_i)); + assign is_down_cast = (fpnew_pkg::fp_width(dst_fmt_i) < fpnew_pkg::fp_width(src_fmt_i)); + + // The destination format is the int format for F2I casts + assign dst_fmt = dst_fmt_is_int ? int_fmt_i : dst_fmt_i; + + // The data sent along consists of the vectorial flag and format bits + assign aux_data = {dst_fmt_is_int, vectorial_op, dst_fmt}; + assign target_aux_d = {dst_vec_op, dst_is_cpk}; + + // CONV passes one operand for assembly after the unit: opC for cpk, opB for others + if (OpGroup == fpnew_pkg::CONV) begin : conv_target + assign conv_target_d = dst_is_cpk ? operands_i[2] : operands_i[1]; + end else begin : not_conv_target + assign conv_target_d = '0; + end + + // For 2-operand units, prepare boxing info + logic [NUM_FORMATS-1:0] is_boxed_1op; + logic [NUM_FORMATS-1:0][1:0] is_boxed_2op; + + always_comb begin : boxed_2op + for (int fmt = 0; fmt < NUM_FORMATS; fmt++) begin + is_boxed_1op[fmt] = is_boxed_i[fmt][0]; + is_boxed_2op[fmt] = is_boxed_i[fmt][1:0]; + end + end + + // --------------- + // Generate Lanes + // --------------- + for (genvar lane = 0; lane < int'(NUM_LANES); lane++) begin : gen_num_lanes + localparam int unsigned LANE = unsigned'(lane); // unsigned to please the linter + // Get a mask of active formats for this lane + localparam fpnew_pkg::fmt_logic_t ACTIVE_FORMATS = + fpnew_pkg::get_lane_formats(Width, FpFmtConfig, LANE); + localparam fpnew_pkg::ifmt_logic_t ACTIVE_INT_FORMATS = + fpnew_pkg::get_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam int unsigned MAX_WIDTH = fpnew_pkg::max_fp_width(ACTIVE_FORMATS); + + // Cast-specific parameters + localparam fpnew_pkg::fmt_logic_t CONV_FORMATS = + fpnew_pkg::get_conv_lane_formats(Width, FpFmtConfig, LANE); + localparam fpnew_pkg::ifmt_logic_t CONV_INT_FORMATS = + fpnew_pkg::get_conv_lane_int_formats(Width, FpFmtConfig, IntFmtConfig, LANE); + localparam int unsigned CONV_WIDTH = fpnew_pkg::max_fp_width(CONV_FORMATS); + + // Lane parameters from Opgroup + localparam fpnew_pkg::fmt_logic_t LANE_FORMATS = (OpGroup == fpnew_pkg::CONV) + ? CONV_FORMATS : ACTIVE_FORMATS; + localparam int unsigned LANE_WIDTH = (OpGroup == fpnew_pkg::CONV) ? CONV_WIDTH : MAX_WIDTH; + + logic [LANE_WIDTH-1:0] local_result; // lane-local results + + // Generate instances only if needed, lane 0 always generated + if ((lane == 0) || EnableVectors) begin : active_lane + logic in_valid, out_valid, out_ready; // lane-local handshake + + logic [NUM_OPERANDS-1:0][LANE_WIDTH-1:0] local_operands; // lane-local oprands + logic [LANE_WIDTH-1:0] op_result; // lane-local results + fpnew_pkg::status_t op_status; + + assign in_valid = in_valid_i & ((lane == 0) | vectorial_op); // upper lanes only for vectors + + // Slice out the operands for this lane, upper bits are ignored in the unit + always_comb begin : prepare_input + for (int unsigned i = 0; i < NUM_OPERANDS; i++) begin + if (i == 2) begin + local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(dst_fmt_i); + end else begin + local_operands[i] = operands_i[i] >> LANE*fpnew_pkg::fp_width(src_fmt_i); + end + end + + // override operand 0 for some conversions + if (OpGroup == fpnew_pkg::CONV) begin + // Source is an integer + if (op_i == fpnew_pkg::I2F) begin + local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::int_width(int_fmt_i); + // vectorial F2F up casts + end else if (op_i == fpnew_pkg::F2F) begin + if (vectorial_op && op_mod_i && is_up_cast) begin // up cast with upper half + local_operands[0] = operands_i[0] >> LANE*fpnew_pkg::fp_width(src_fmt_i) + + MAX_FP_WIDTH/2; + end + // CPK + end else if (dst_is_cpk) begin + if (lane == 1) begin + local_operands[0] = operands_i[1][LANE_WIDTH-1:0]; // using opB as second argument + end + end + end + end + + // Instantiate the operation from the selected opgroup + if (OpGroup == fpnew_pkg::ADDMUL) begin : lane_instance + fpnew_fma_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_fma_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands ), + .is_boxed_i, + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + + end else if (OpGroup == fpnew_pkg::DIVSQRT) begin : lane_instance + if (!PulpDivsqrt && LANE_FORMATS[0] && (LANE_FORMATS[1:fpnew_pkg::NUM_FP_FORMATS-1] == '0)) begin + // The T-head-based DivSqrt unit is supported only in FP32-only configurations + fpnew_divsqrt_th_32 #( + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_divsqrt_multi_th ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[1:0] ), // 2 operands + .is_boxed_i ( is_boxed_2op ), // 2 operands + .rnd_mode_i, + .op_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + end else begin + fpnew_divsqrt_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_divsqrt_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[1:0] ), // 2 operands + .is_boxed_i ( is_boxed_2op ), // 2 operands + .rnd_mode_i, + .op_i, + .dst_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .vectorial_op_i ( vectorial_op ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .divsqrt_done_o ( divsqrt_done[lane] ), + .simd_synch_done_i( simd_synch_done ), + .divsqrt_ready_o ( divsqrt_ready[lane] ), + .simd_synch_rdy_i ( simd_synch_rdy ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + end + end else if (OpGroup == fpnew_pkg::NONCOMP) begin : lane_instance + + end else if (OpGroup == fpnew_pkg::CONV) begin : lane_instance + fpnew_cast_multi #( + .FpFmtConfig ( LANE_FORMATS ), + .IntFmtConfig ( CONV_INT_FORMATS ), + .NumPipeRegs ( NumPipeRegs ), + .PipeConfig ( PipeConfig ), + .TagType ( TagType ), + .AuxType ( logic [AUX_BITS-1:0] ) + ) i_fpnew_cast_multi ( + .clk_i, + .rst_ni, + .operands_i ( local_operands[0] ), + .is_boxed_i ( is_boxed_1op ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .tag_i, + .mask_i ( simd_mask_i[lane] ), + .aux_i ( aux_data ), + .in_valid_i ( in_valid ), + .in_ready_o ( lane_in_ready[lane] ), + .flush_i, + .result_o ( op_result ), + .status_o ( op_status ), + .extension_bit_o ( lane_ext_bit[lane] ), + .tag_o ( lane_tags[lane] ), + .mask_o ( lane_masks[lane] ), + .aux_o ( lane_aux[lane] ), + .out_valid_o ( out_valid ), + .out_ready_i ( out_ready ), + .busy_o ( lane_busy[lane] ), + .reg_ena_i + ); + end // ADD OTHER OPTIONS HERE + + // Handshakes are only done if the lane is actually used + assign out_ready = out_ready_i & ((lane == 0) | result_is_vector); + assign lane_out_valid[lane] = out_valid & ((lane == 0) | result_is_vector); + + // Properly NaN-box or sign-extend the slice result if not in use + assign local_result = (lane_out_valid[lane] | ExtRegEna) ? op_result : '{default: lane_ext_bit[0]}; + assign lane_status[lane] = (lane_out_valid[lane] | ExtRegEna) ? op_status : '0; + + // Otherwise generate constant sign-extension + end else begin : inactive_lane + assign lane_out_valid[lane] = 1'b0; // unused lane + assign lane_in_ready[lane] = 1'b0; // unused lane + assign lane_aux[lane] = 1'b0; // unused lane + assign lane_masks[lane] = 1'b1; // unused lane + assign lane_tags[lane] = 1'b0; // unused lane + assign divsqrt_done[lane] = 1'b0; // unused lane + assign divsqrt_ready[lane] = 1'b0; // unused lane + assign lane_ext_bit[lane] = 1'b1; // NaN-box unused lane + assign local_result = {(LANE_WIDTH){lane_ext_bit[0]}}; // sign-extend/nan box + assign lane_status[lane] = '0; + assign lane_busy[lane] = 1'b0; + end + + // Generate result packing depending on float format + for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : pack_fp_result + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + // only for active formats within the lane + if (ACTIVE_FORMATS[fmt]) begin + assign fmt_slice_result[fmt][(LANE+1)*FP_WIDTH-1:LANE*FP_WIDTH] = + local_result[FP_WIDTH-1:0]; + end else if ((LANE+1)*FP_WIDTH <= Width) begin + assign fmt_slice_result[fmt][(LANE+1)*FP_WIDTH-1:LANE*FP_WIDTH] = + '{default: lane_ext_bit[LANE]}; + end else if (LANE*FP_WIDTH < Width) begin + assign fmt_slice_result[fmt][Width-1:LANE*FP_WIDTH] = + '{default: lane_ext_bit[LANE]}; + end + end + + // Generate result packing depending on integer format + if (OpGroup == fpnew_pkg::CONV) begin : int_results_enabled + for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : pack_int_result + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + if (ACTIVE_INT_FORMATS[ifmt]) begin + assign ifmt_slice_result[ifmt][(LANE+1)*INT_WIDTH-1:LANE*INT_WIDTH] = + local_result[INT_WIDTH-1:0]; + end else if ((LANE+1)*INT_WIDTH <= Width) begin + assign ifmt_slice_result[ifmt][(LANE+1)*INT_WIDTH-1:LANE*INT_WIDTH] = '0; + end else if (LANE*INT_WIDTH < Width) begin + assign ifmt_slice_result[ifmt][Width-1:LANE*INT_WIDTH] = '0; + end + end + end + end + + // Extend slice result if needed + for (genvar fmt = 0; fmt < NUM_FORMATS; fmt++) begin : extend_fp_result + // Set up some constants + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + if (NUM_LANES*FP_WIDTH < Width) + assign fmt_slice_result[fmt][Width-1:NUM_LANES*FP_WIDTH] = '{default: lane_ext_bit[0]}; + end + + for (genvar ifmt = 0; ifmt < NUM_INT_FORMATS; ifmt++) begin : extend_or_mute_int_result + // Mute int results if unused + if (OpGroup != fpnew_pkg::CONV) begin : mute_int_result + assign ifmt_slice_result[ifmt] = '0; + + // Extend slice result if needed + end else begin : extend_int_result + // Set up some constants + localparam int unsigned INT_WIDTH = fpnew_pkg::int_width(fpnew_pkg::int_format_e'(ifmt)); + if (NUM_LANES*INT_WIDTH < Width) + assign ifmt_slice_result[ifmt][Width-1:NUM_LANES*INT_WIDTH] = '0; + end + end + + // Bypass lanes with target operand for vectorial casts + if (OpGroup == fpnew_pkg::CONV) begin : target_regs + // Bypass pipeline signals, index i holds signal after i register stages + logic [0:NumPipeRegs][Width-1:0] byp_pipe_target_q; + logic [0:NumPipeRegs][2:0] byp_pipe_aux_q; + logic [0:NumPipeRegs] byp_pipe_valid_q; + // Ready signal is combinatorial for all stages + logic [0:NumPipeRegs] byp_pipe_ready; + + // Input stage: First element of pipeline is taken from inputs + assign byp_pipe_target_q[0] = conv_target_d; + assign byp_pipe_aux_q[0] = target_aux_d; + assign byp_pipe_valid_q[0] = in_valid_i & vectorial_op; + // Generate the register stages + for (genvar i = 0; i < NumPipeRegs; i++) begin : gen_bypass_pipeline + // Internal register enable for this stage + logic reg_ena; + // Determine the ready signal of the current stage - advance the pipeline: + // 1. if the next stage is ready for our data + // 2. if the next stage only holds a bubble (not valid) -> we can pop it + assign byp_pipe_ready[i] = byp_pipe_ready[i+1] | ~byp_pipe_valid_q[i+1]; + // Valid: enabled by ready signal, synchronous clear with the flush signal + `FFLARNC(byp_pipe_valid_q[i+1], byp_pipe_valid_q[i], byp_pipe_ready[i], flush_i, 1'b0, clk_i, rst_ni) + // Enable register if pipleine ready and a valid data item is present + assign reg_ena = (byp_pipe_ready[i] & byp_pipe_valid_q[i]) | reg_ena_i[i]; + // Generate the pipeline registers within the stages, use enable-registers + `FFL(byp_pipe_target_q[i+1], byp_pipe_target_q[i], reg_ena, '0) + `FFL(byp_pipe_aux_q[i+1], byp_pipe_aux_q[i], reg_ena, '0) + end + // Output stage: Ready travels backwards from output side, driven by downstream circuitry + assign byp_pipe_ready[NumPipeRegs] = out_ready_i & result_is_vector; + // Output stage: assign module outputs + assign conv_target_q = byp_pipe_target_q[NumPipeRegs]; + + // decode the aux data + assign {result_vec_op, result_is_cpk} = byp_pipe_aux_q[NumPipeRegs]; + end else begin : no_conv + assign {result_vec_op, result_is_cpk} = '0; + assign conv_target_q = '0; + end + + if (PulpDivsqrt) begin + // Synch lanes if there is more than one + assign simd_synch_rdy = EnableVectors ? &divsqrt_ready : divsqrt_ready[0]; + assign simd_synch_done = EnableVectors ? &divsqrt_done : divsqrt_done[0]; + end else begin + // Unused (alternative divider only supported for scalar FP32 divsqrt) + assign simd_synch_rdy = '0; + assign simd_synch_done = '0; + end + + // ------------ + // Output Side + // ------------ + assign {result_fmt_is_int, result_is_vector, result_fmt} = lane_aux[0]; + + assign result_o = result_fmt_is_int + ? ifmt_slice_result[result_fmt] + : fmt_slice_result[result_fmt]; + + assign extension_bit_o = lane_ext_bit[0]; // don't care about upper ones + assign tag_o = lane_tags[0]; // don't care about upper ones + assign busy_o = (| lane_busy); + + assign out_valid_o = lane_out_valid[0]; // don't care about upper ones + + // Collapse the status + always_comb begin : output_processing + // Collapse the status + automatic fpnew_pkg::status_t temp_status; + temp_status = '0; + for (int i = 0; i < int'(NUM_LANES); i++) + temp_status |= lane_status[i] & {5{lane_masks[i]}}; + status_o = temp_status; + end + +endmodule +// ----- 8< ----- FILE "./fpnew_rounding.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_rounding #( + parameter int unsigned AbsWidth=2 // Width of the abolute value, without sign bit +) ( + // Input value + input logic [AbsWidth-1:0] abs_value_i, // absolute value without sign + input logic sign_i, + // Rounding information + input logic [1:0] round_sticky_bits_i, // round and sticky bits {RS} + input fpnew_pkg::roundmode_e rnd_mode_i, + input logic effective_subtraction_i, // sign of inputs affects rounding of zeroes + // Output value + output logic [AbsWidth-1:0] abs_rounded_o, // absolute value without sign + output logic sign_o, + // Output classification + output logic exact_zero_o // output is an exact zero +); + + logic round_up; // Rounding decision + + // Take the rounding decision according to RISC-V spec + // RoundMode | Mnemonic | Meaning + // :--------:|:--------:|:------- + // 000 | RNE | Round to Nearest, ties to Even + // 001 | RTZ | Round towards Zero + // 010 | RDN | Round Down (towards -\infty) + // 011 | RUP | Round Up (towards \infty) + // 100 | RMM | Round to Nearest, ties to Max Magnitude + // 101 | ROD | Round towards odd (this mode is not define in RISC-V FP-SPEC) + // others | | *invalid* + always_comb begin : rounding_decision + unique case (rnd_mode_i) + fpnew_pkg::RNE: // Decide accoring to round/sticky bits + unique case (round_sticky_bits_i) + 2'b00, + 2'b01: round_up = 1'b0; // < ulp/2 away, round down + 2'b10: round_up = abs_value_i[0]; // = ulp/2 away, round towards even result + 2'b11: round_up = 1'b1; // > ulp/2 away, round up + default: round_up = fpnew_pkg::DONT_CARE; + endcase + fpnew_pkg::RTZ: round_up = 1'b0; // always round down + fpnew_pkg::RDN: round_up = (| round_sticky_bits_i) ? sign_i : 1'b0; // to 0 if +, away if - + fpnew_pkg::RUP: round_up = (| round_sticky_bits_i) ? ~sign_i : 1'b0; // to 0 if -, away if + + fpnew_pkg::RMM: round_up = round_sticky_bits_i[1]; // round down if < ulp/2 away, else up + fpnew_pkg::ROD: round_up = ~abs_value_i[0] & (| round_sticky_bits_i); + default: round_up = fpnew_pkg::DONT_CARE; // propagate x + endcase + end + + // Perform the rounding, exponent change and overflow to inf happens automagically + assign abs_rounded_o = abs_value_i + round_up; + + // True zero result is a zero result without dirty round/sticky bits + assign exact_zero_o = (abs_value_i == '0) && (round_sticky_bits_i == '0); + + // In case of effective subtraction (thus signs of addition operands must have differed) and a + // true zero result, the result sign is '-' in case of RDN and '+' for other modes. + assign sign_o = (exact_zero_o && effective_subtraction_i) + ? (rnd_mode_i == fpnew_pkg::RDN) + : sign_i; + +endmodule +// ----- 8< ----- FILE "./fpnew_top.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +// Copyright 2019 ETH Zurich and University of Bologna. +// +// Copyright and related rights are licensed under the Solderpad Hardware +// License, Version 0.51 (the "License"); you may not use this file except in +// compliance with the License. You may obtain a copy of the License at +// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law +// or agreed to in writing, software, hardware and materials distributed under +// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR +// CONDITIONS OF ANY KIND, either express or implied. See the License for the +// specific language governing permissions and limitations under the License. +// +// SPDX-License-Identifier: SHL-0.51 + +// Author: Stefan Mach + +module fpnew_top #( + // FPU configuration + parameter fpnew_pkg::fpu_features_t Features = fpnew_pkg::RV64D_Xsflt, + parameter fpnew_pkg::fpu_implementation_t Implementation = fpnew_pkg::DEFAULT_NOREGS, + // PulpDivSqrt = 0 enables T-head-based DivSqrt unit. Supported only for FP32-only instances of Fpnew + parameter logic PulpDivsqrt = 1'b1, + parameter type TagType = logic, + parameter int unsigned TrueSIMDClass = 0, + parameter int unsigned EnableSIMDMask = 0, + // Do not change + localparam int unsigned NumLanes = fpnew_pkg::max_num_lanes(Features.Width, Features.FpFmtMask, Features.EnableVectors), + localparam type MaskType = logic [NumLanes-1:0], + localparam int unsigned WIDTH = Features.Width, + localparam int unsigned NUM_OPERANDS = 3 +) ( + input logic clk_i, + input logic rst_ni, + // Input signals + input logic [NUM_OPERANDS-1:0][WIDTH-1:0] operands_i, + input fpnew_pkg::roundmode_e rnd_mode_i, + input fpnew_pkg::operation_e op_i, + input logic op_mod_i, + input fpnew_pkg::fp_format_e src_fmt_i, + input fpnew_pkg::fp_format_e dst_fmt_i, + input fpnew_pkg::int_format_e int_fmt_i, + input logic vectorial_op_i, + input TagType tag_i, + input MaskType simd_mask_i, + // Input Handshake + input logic in_valid_i, + output logic in_ready_o, + input logic flush_i, + // Output signals + output logic [WIDTH-1:0] result_o, + output fpnew_pkg::status_t status_o, + output TagType tag_o, + // Output handshake + output logic out_valid_o, + input logic out_ready_i, + // Indication of valid data in flight + output logic busy_o +); + + localparam int unsigned NUM_OPGROUPS = fpnew_pkg::NUM_OPGROUPS; + localparam int unsigned NUM_FORMATS = fpnew_pkg::NUM_FP_FORMATS; + + // ---------------- + // Type Definition + // ---------------- + typedef struct packed { + logic [WIDTH-1:0] result; + fpnew_pkg::status_t status; + TagType tag; + } output_t; + + // Handshake signals for the blocks + logic [NUM_OPGROUPS-1:0] opgrp_in_ready, opgrp_out_valid, opgrp_out_ready, opgrp_ext, opgrp_busy; + output_t [NUM_OPGROUPS-1:0] opgrp_outputs; + + logic [NUM_FORMATS-1:0][NUM_OPERANDS-1:0] is_boxed; + + // ----------- + // Input Side + // ----------- + assign in_ready_o = in_valid_i & opgrp_in_ready[fpnew_pkg::get_opgroup(op_i)]; + + // NaN-boxing check + for (genvar fmt = 0; fmt < int'(NUM_FORMATS); fmt++) begin : gen_nanbox_check + localparam int unsigned FP_WIDTH = fpnew_pkg::fp_width(fpnew_pkg::fp_format_e'(fmt)); + // NaN boxing is only generated if it's enabled and needed + if (Features.EnableNanBox && (FP_WIDTH < WIDTH)) begin : check + for (genvar op = 0; op < int'(NUM_OPERANDS); op++) begin : operands + assign is_boxed[fmt][op] = (!vectorial_op_i) + ? operands_i[op][WIDTH-1:FP_WIDTH] == '1 + : 1'b1; + end + end else begin : no_check + assign is_boxed[fmt] = '1; + end + end + + // Filter out the mask if not used + MaskType simd_mask; + assign simd_mask = simd_mask_i | ~{NumLanes{logic'(EnableSIMDMask)}}; + + // ------------------------- + // Generate Operation Blocks + // ------------------------- + for (genvar opgrp = 0; opgrp < int'(NUM_OPGROUPS); opgrp++) begin : gen_operation_groups + localparam int unsigned NUM_OPS = fpnew_pkg::num_operands(fpnew_pkg::opgroup_e'(opgrp)); + + logic in_valid; + logic [NUM_FORMATS-1:0][NUM_OPS-1:0] input_boxed; + + assign in_valid = in_valid_i & (fpnew_pkg::get_opgroup(op_i) == fpnew_pkg::opgroup_e'(opgrp)); + + // slice out input boxing + always_comb begin : slice_inputs + for (int unsigned fmt = 0; fmt < NUM_FORMATS; fmt++) + input_boxed[fmt] = is_boxed[fmt][NUM_OPS-1:0]; + end + + fpnew_opgroup_block #( + .OpGroup ( fpnew_pkg::opgroup_e'(opgrp) ), + .Width ( WIDTH ), + .EnableVectors ( Features.EnableVectors ), + .PulpDivsqrt ( PulpDivsqrt ), + .FpFmtMask ( Features.FpFmtMask ), + .IntFmtMask ( Features.IntFmtMask ), + .FmtPipeRegs ( Implementation.PipeRegs[opgrp] ), + .FmtUnitTypes ( Implementation.UnitTypes[opgrp] ), + .PipeConfig ( Implementation.PipeConfig ), + .TagType ( TagType ), + .TrueSIMDClass ( TrueSIMDClass ) + ) i_opgroup_block ( + .clk_i, + .rst_ni, + .operands_i ( operands_i[NUM_OPS-1:0] ), + .is_boxed_i ( input_boxed ), + .rnd_mode_i, + .op_i, + .op_mod_i, + .src_fmt_i, + .dst_fmt_i, + .int_fmt_i, + .vectorial_op_i, + .tag_i, + .simd_mask_i ( simd_mask ), + .in_valid_i ( in_valid ), + .in_ready_o ( opgrp_in_ready[opgrp] ), + .flush_i, + .result_o ( opgrp_outputs[opgrp].result ), + .status_o ( opgrp_outputs[opgrp].status ), + .extension_bit_o ( opgrp_ext[opgrp] ), + .tag_o ( opgrp_outputs[opgrp].tag ), + .out_valid_o ( opgrp_out_valid[opgrp] ), + .out_ready_i ( opgrp_out_ready[opgrp] ), + .busy_o ( opgrp_busy[opgrp] ) + ); + end + + // ------------------ + // Arbitrate Outputs + // ------------------ + output_t arbiter_output; + + // Round-Robin arbiter to decide which result to use + rr_arb_tree #( + .NumIn ( NUM_OPGROUPS ), + .DataType ( output_t ), + .AxiVldRdy ( 1'b1 ) + ) i_arbiter ( + .clk_i, + .rst_ni, + .flush_i, + .rr_i ( '0 ), + .req_i ( opgrp_out_valid ), + .gnt_o ( opgrp_out_ready ), + .data_i ( opgrp_outputs ), + .gnt_i ( out_ready_i ), + .req_o ( out_valid_o ), + .data_o ( arbiter_output ), + .idx_o ( /* unused */ ) + ); + + // Unpack output + assign result_o = arbiter_output.result; + assign status_o = arbiter_output.status; + assign tag_o = arbiter_output.tag; + + assign busy_o = (| opgrp_busy); + +endmodule +// ----- 8< ----- FILE "./FloatCoreWrapper.sv" ----- 8< ----- + +// Generated by CIRCT firtool-1.114.0-2-g6cf2492e1 +module FloatCoreWrapper( + input logic clk_i, + input logic rst_ni, + input logic in_valid_i, + output logic in_ready_o, + input logic [32-1:0] operands_i_0, + input logic [32-1:0] operands_i_1, + input logic [32-1:0] operands_i_2, + input logic[4-1:0] op_i, + input logic op_mod_i, + input logic[2:0] rnd_mode_i, + input logic flush_i, + output logic out_valid_o, + input logic out_ready_i, + output logic[32-1:0] result_o, + output logic[4:0] status_o, + output logic busy_o); + + logic [3-1:0][32-1:0] operands_i; + assign operands_i[0] = operands_i_0; + assign operands_i[1] = operands_i_1; + assign operands_i[2] = operands_i_2; + localparam fpnew_pkg::fpu_implementation_t impl = '{ + PipeRegs: '{default: 'd3}, + UnitTypes: '{'{default: fpnew_pkg::PARALLEL}, // ADDMUL + '{default: fpnew_pkg::MERGED}, // DIVSQRT + '{default: fpnew_pkg::PARALLEL}, // NONCOMP + '{default: fpnew_pkg::MERGED}}, // CONV + PipeConfig: fpnew_pkg::DISTRIBUTED +}; + fpnew_top#( + .Features(fpnew_pkg::RV32F), + .Implementation(impl), + .PulpDivsqrt(0) + ) core( + .clk_i(clk_i), + .rst_ni(rst_ni), + .operands_i(operands_i), + .rnd_mode_i(fpnew_pkg::roundmode_e'(rnd_mode_i)), + .op_i(fpnew_pkg::operation_e'(op_i)), + .op_mod_i(op_mod_i), + .src_fmt_i(fpnew_pkg::FP32), + .dst_fmt_i(fpnew_pkg::FP32), + .int_fmt_i(fpnew_pkg::INT32), + .vectorial_op_i(1'b0), + .tag_i(1'b0), + .simd_mask_i(1'b0), + .in_valid_i(in_valid_i), + .flush_i(flush_i), + .out_ready_i(out_ready_i), + + .in_ready_o(in_ready_o), + .result_o(result_o), + .status_o(status_o), + .tag_o(), + .out_valid_o(out_valid_o), + .busy_o(busy_o) + ); +endmodule +// ----- 8< ----- FILE "./Sram_512x128.v" ----- 8< ----- + +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module Sram_512x128( + input clock, + input enable, + input write, + input [8:0] addr, + input [127:0] wdata, + input [15:0] wmask, + output [127:0] rdata +); + +/////////////////////////// +///// SRAM Selection ////// +/////////////////////////// +`ifdef USE_ASAP7 +/////////////////////////// +//////// ASAP7 SRAM //////// +/////////////////////////// + wire [127:0] nwmask; + genvar i; + generate + for (i = 0; i < 16; i++) begin + assign nwmask[8*i +: 8] = {8{wmask[i]}}; + end + endgenerate + + fakeram_512x128 u_asap7_sram ( + .rd_out(rdata), + .addr_in(addr), + .wd_in(wdata), + .we_in(write), + .ce_in(enable), + .clk(clock) + ); +`else +/////////////////////////// +////// Generic SRAM /////// +/////////////////////////// + reg [127:0] mem [0:511]; + reg [8:0] raddr; + + assign rdata = mem[raddr]; + +`ifndef SYNTHESIS + task randomMemoryAll; + for (int i = 0; i < 128; i++) begin + for (int j = 0; j < 512; j++) begin + mem[i][j] = $random; + end + end + endtask + + initial begin + randomMemoryAll; + end +`endif + + always @(posedge clock) begin + for (int i = 0; i < 16; i++) begin + if (enable & write & wmask[i]) begin + mem[addr][i*8 +: 8] <= wdata[8*i +: 8]; + end + end + + if (enable & ~write) begin + raddr <= addr; + end + end +`endif + +endmodule +// ----- 8< ----- FILE "./Sram_2048x128.v" ----- 8< ----- + +// Copyright 2024 Google LLC +// +// Licensed under the Apache License, Version 2.0 (the "License"); +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. + +module Sram_2048x128( + input clock, + input enable, + input write, + input [10:0] addr, + input [127:0] wdata, + input [15:0] wmask, + output [127:0] rdata +); + +/////////////////////////// +///// SRAM Selection ////// +/////////////////////////// +`ifdef USE_ASAP7 +/////////////////////////// +//////// ASAP7 SRAM //////// +/////////////////////////// + wire [127:0] nwmask; + genvar i; + generate + for (i = 0; i < 16; i++) begin + assign nwmask[8*i +: 8] = {8{wmask[i]}}; + end + endgenerate + + fakeram_2048x128 u_asap7_sram ( + .rd_out(rdata), + .addr_in(addr), + .wd_in(wdata), + .we_in(write), + .ce_in(enable), + .clk(clock) + ); +`else +/////////////////////////// +////// Generic SRAM /////// +/////////////////////////// + reg [127:0] mem [0:2047]; + reg [10:0] raddr; + + assign rdata = mem[raddr]; + +`ifndef SYNTHESIS + task randomMemoryAll; + for (int i = 0; i < 128; i++) begin + for (int j = 0; j < 2048; j++) begin + mem[i][j] = $random; + end + end + endtask + + initial begin + randomMemoryAll; + end +`endif + + always @(posedge clock) begin + for (int i = 0; i < 16; i++) begin + if (enable & write & wmask[i]) begin + mem[addr][i*8 +: 8] <= wdata[8*i +: 8]; + end + end + + if (enable & ~write) begin + raddr <= addr; + end + end +`endif // FFCP12_SRAM + +endmodule diff --git a/flow/platforms/asap7/lef/fakeram_2048x128.lef b/flow/platforms/asap7/lef/fakeram_2048x128.lef new file mode 100644 index 0000000000..40851b00c2 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram_2048x128.lef @@ -0,0 +1,2907 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram_2048x128 + PROPERTY width 128 ; + PROPERTY depth 2048 ; + PROPERTY banks 4 ; + FOREIGN fakeram_2048x128 0 0 ; + SYMMETRY X Y R90 ; + SIZE 66.500 BY 166.600 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.480 0.024 18.504 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.056 0.024 19.080 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.632 0.024 19.656 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.208 0.024 20.232 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.784 0.024 20.808 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.360 0.024 21.384 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.936 0.024 21.960 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.512 0.024 22.536 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.088 0.024 23.112 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.664 0.024 23.688 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.240 0.024 24.264 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.816 0.024 24.840 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.392 0.024 25.416 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.968 0.024 25.992 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.544 0.024 26.568 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.120 0.024 27.144 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.696 0.024 27.720 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.272 0.024 28.296 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.848 0.024 28.872 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.424 0.024 29.448 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.000 0.024 30.024 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.576 0.024 30.600 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.152 0.024 31.176 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.728 0.024 31.752 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.304 0.024 32.328 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.880 0.024 32.904 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.456 0.024 33.480 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.032 0.024 34.056 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.608 0.024 34.632 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.184 0.024 35.208 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.760 0.024 35.784 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.336 0.024 36.360 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.912 0.024 36.936 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.488 0.024 37.512 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.064 0.024 38.088 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 38.640 0.024 38.664 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.216 0.024 39.240 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.792 0.024 39.816 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.368 0.024 40.392 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.944 0.024 40.968 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.520 0.024 41.544 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.096 0.024 42.120 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 42.672 0.024 42.696 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.248 0.024 43.272 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 43.824 0.024 43.848 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.400 0.024 44.424 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 44.976 0.024 45.000 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 45.552 0.024 45.576 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.128 0.024 46.152 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 46.704 0.024 46.728 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.280 0.024 47.304 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 47.856 0.024 47.880 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 48.432 0.024 48.456 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.008 0.024 49.032 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 49.584 0.024 49.608 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.160 0.024 50.184 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 50.736 0.024 50.760 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.312 0.024 51.336 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 51.888 0.024 51.912 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 52.464 0.024 52.488 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.040 0.024 53.064 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 53.616 0.024 53.640 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.192 0.024 54.216 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 54.768 0.024 54.792 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.344 0.024 55.368 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 55.920 0.024 55.944 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 56.496 0.024 56.520 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.072 0.024 57.096 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 57.648 0.024 57.672 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.224 0.024 58.248 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 58.800 0.024 58.824 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.376 0.024 59.400 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 59.952 0.024 59.976 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 60.528 0.024 60.552 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.104 0.024 61.128 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 61.680 0.024 61.704 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.256 0.024 62.280 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 62.832 0.024 62.856 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.408 0.024 63.432 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 63.984 0.024 64.008 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 64.560 0.024 64.584 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.136 0.024 65.160 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 65.712 0.024 65.736 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.288 0.024 66.312 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 66.864 0.024 66.888 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 67.440 0.024 67.464 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.016 0.024 68.040 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 68.592 0.024 68.616 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.168 0.024 69.192 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 69.744 0.024 69.768 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.320 0.024 70.344 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 70.896 0.024 70.920 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 71.472 0.024 71.496 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.048 0.024 72.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 72.624 0.024 72.648 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 73.200 0.024 73.224 ; + END + END rd_out[127] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 77.424 0.024 77.448 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.000 0.024 78.024 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 78.576 0.024 78.600 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.152 0.024 79.176 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 79.728 0.024 79.752 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.304 0.024 80.328 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 80.880 0.024 80.904 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 81.456 0.024 81.480 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.032 0.024 82.056 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 82.608 0.024 82.632 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.184 0.024 83.208 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 83.760 0.024 83.784 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.336 0.024 84.360 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 84.912 0.024 84.936 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 85.488 0.024 85.512 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.064 0.024 86.088 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 86.640 0.024 86.664 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.216 0.024 87.240 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 87.792 0.024 87.816 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.368 0.024 88.392 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 88.944 0.024 88.968 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 89.520 0.024 89.544 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.096 0.024 90.120 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 90.672 0.024 90.696 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.248 0.024 91.272 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 91.824 0.024 91.848 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.400 0.024 92.424 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 92.976 0.024 93.000 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 93.552 0.024 93.576 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.128 0.024 94.152 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 94.704 0.024 94.728 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.280 0.024 95.304 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 95.856 0.024 95.880 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 96.432 0.024 96.456 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.008 0.024 97.032 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 97.584 0.024 97.608 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.160 0.024 98.184 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 98.736 0.024 98.760 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 99.312 0.024 99.336 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 99.888 0.024 99.912 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 100.464 0.024 100.488 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 101.040 0.024 101.064 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 101.616 0.024 101.640 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 102.192 0.024 102.216 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 102.768 0.024 102.792 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 103.344 0.024 103.368 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 103.920 0.024 103.944 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 104.496 0.024 104.520 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.072 0.024 105.096 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 105.648 0.024 105.672 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.224 0.024 106.248 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 106.800 0.024 106.824 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 107.376 0.024 107.400 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 107.952 0.024 107.976 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 108.528 0.024 108.552 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 109.104 0.024 109.128 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 109.680 0.024 109.704 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 110.256 0.024 110.280 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 110.832 0.024 110.856 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 111.408 0.024 111.432 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 111.984 0.024 112.008 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 112.560 0.024 112.584 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 113.136 0.024 113.160 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 113.712 0.024 113.736 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 114.288 0.024 114.312 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 114.864 0.024 114.888 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 115.440 0.024 115.464 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 116.016 0.024 116.040 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 116.592 0.024 116.616 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.168 0.024 117.192 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 117.744 0.024 117.768 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 118.320 0.024 118.344 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 118.896 0.024 118.920 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 119.472 0.024 119.496 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 120.048 0.024 120.072 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 120.624 0.024 120.648 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 121.200 0.024 121.224 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 121.776 0.024 121.800 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 122.352 0.024 122.376 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 122.928 0.024 122.952 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 123.504 0.024 123.528 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 124.080 0.024 124.104 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 124.656 0.024 124.680 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 125.232 0.024 125.256 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 125.808 0.024 125.832 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 126.384 0.024 126.408 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 126.960 0.024 126.984 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 127.536 0.024 127.560 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 128.112 0.024 128.136 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 128.688 0.024 128.712 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 129.264 0.024 129.288 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 129.840 0.024 129.864 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 130.416 0.024 130.440 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 130.992 0.024 131.016 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 131.568 0.024 131.592 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 132.144 0.024 132.168 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 132.720 0.024 132.744 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 133.296 0.024 133.320 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 133.872 0.024 133.896 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 134.448 0.024 134.472 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 135.024 0.024 135.048 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 135.600 0.024 135.624 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 136.176 0.024 136.200 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 136.752 0.024 136.776 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 137.328 0.024 137.352 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 137.904 0.024 137.928 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 138.480 0.024 138.504 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 139.056 0.024 139.080 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 139.632 0.024 139.656 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 140.208 0.024 140.232 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 140.784 0.024 140.808 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 141.360 0.024 141.384 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 141.936 0.024 141.960 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 142.512 0.024 142.536 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 143.088 0.024 143.112 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 143.664 0.024 143.688 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 144.240 0.024 144.264 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 144.816 0.024 144.840 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 145.392 0.024 145.416 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 145.968 0.024 145.992 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 146.544 0.024 146.568 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 147.120 0.024 147.144 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 147.696 0.024 147.720 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 148.272 0.024 148.296 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 148.848 0.024 148.872 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 149.424 0.024 149.448 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 150.000 0.024 150.024 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 150.576 0.024 150.600 ; + END + END wd_in[127] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 154.800 0.024 154.824 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 155.376 0.024 155.400 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 155.952 0.024 155.976 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 156.528 0.024 156.552 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 157.104 0.024 157.128 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 157.680 0.024 157.704 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 158.256 0.024 158.280 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 158.832 0.024 158.856 ; + END + END addr_in[7] + PIN addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 159.408 0.024 159.432 ; + END + END addr_in[8] + PIN addr_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 159.984 0.024 160.008 ; + END + END addr_in[9] + PIN addr_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 160.560 0.024 160.584 ; + END + END addr_in[10] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 164.784 0.024 164.808 ; + END + END we_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 165.360 0.024 165.384 ; + END + END clk + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 165.936 0.024 165.960 ; + END + END ce_in + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 66.452 0.480 ; + RECT 0.048 1.152 66.452 1.248 ; + RECT 0.048 1.920 66.452 2.016 ; + RECT 0.048 2.688 66.452 2.784 ; + RECT 0.048 3.456 66.452 3.552 ; + RECT 0.048 4.224 66.452 4.320 ; + RECT 0.048 4.992 66.452 5.088 ; + RECT 0.048 5.760 66.452 5.856 ; + RECT 0.048 6.528 66.452 6.624 ; + RECT 0.048 7.296 66.452 7.392 ; + RECT 0.048 8.064 66.452 8.160 ; + RECT 0.048 8.832 66.452 8.928 ; + RECT 0.048 9.600 66.452 9.696 ; + RECT 0.048 10.368 66.452 10.464 ; + RECT 0.048 11.136 66.452 11.232 ; + RECT 0.048 11.904 66.452 12.000 ; + RECT 0.048 12.672 66.452 12.768 ; + RECT 0.048 13.440 66.452 13.536 ; + RECT 0.048 14.208 66.452 14.304 ; + RECT 0.048 14.976 66.452 15.072 ; + RECT 0.048 15.744 66.452 15.840 ; + RECT 0.048 16.512 66.452 16.608 ; + RECT 0.048 17.280 66.452 17.376 ; + RECT 0.048 18.048 66.452 18.144 ; + RECT 0.048 18.816 66.452 18.912 ; + RECT 0.048 19.584 66.452 19.680 ; + RECT 0.048 20.352 66.452 20.448 ; + RECT 0.048 21.120 66.452 21.216 ; + RECT 0.048 21.888 66.452 21.984 ; + RECT 0.048 22.656 66.452 22.752 ; + RECT 0.048 23.424 66.452 23.520 ; + RECT 0.048 24.192 66.452 24.288 ; + RECT 0.048 24.960 66.452 25.056 ; + RECT 0.048 25.728 66.452 25.824 ; + RECT 0.048 26.496 66.452 26.592 ; + RECT 0.048 27.264 66.452 27.360 ; + RECT 0.048 28.032 66.452 28.128 ; + RECT 0.048 28.800 66.452 28.896 ; + RECT 0.048 29.568 66.452 29.664 ; + RECT 0.048 30.336 66.452 30.432 ; + RECT 0.048 31.104 66.452 31.200 ; + RECT 0.048 31.872 66.452 31.968 ; + RECT 0.048 32.640 66.452 32.736 ; + RECT 0.048 33.408 66.452 33.504 ; + RECT 0.048 34.176 66.452 34.272 ; + RECT 0.048 34.944 66.452 35.040 ; + RECT 0.048 35.712 66.452 35.808 ; + RECT 0.048 36.480 66.452 36.576 ; + RECT 0.048 37.248 66.452 37.344 ; + RECT 0.048 38.016 66.452 38.112 ; + RECT 0.048 38.784 66.452 38.880 ; + RECT 0.048 39.552 66.452 39.648 ; + RECT 0.048 40.320 66.452 40.416 ; + RECT 0.048 41.088 66.452 41.184 ; + RECT 0.048 41.856 66.452 41.952 ; + RECT 0.048 42.624 66.452 42.720 ; + RECT 0.048 43.392 66.452 43.488 ; + RECT 0.048 44.160 66.452 44.256 ; + RECT 0.048 44.928 66.452 45.024 ; + RECT 0.048 45.696 66.452 45.792 ; + RECT 0.048 46.464 66.452 46.560 ; + RECT 0.048 47.232 66.452 47.328 ; + RECT 0.048 48.000 66.452 48.096 ; + RECT 0.048 48.768 66.452 48.864 ; + RECT 0.048 49.536 66.452 49.632 ; + RECT 0.048 50.304 66.452 50.400 ; + RECT 0.048 51.072 66.452 51.168 ; + RECT 0.048 51.840 66.452 51.936 ; + RECT 0.048 52.608 66.452 52.704 ; + RECT 0.048 53.376 66.452 53.472 ; + RECT 0.048 54.144 66.452 54.240 ; + RECT 0.048 54.912 66.452 55.008 ; + RECT 0.048 55.680 66.452 55.776 ; + RECT 0.048 56.448 66.452 56.544 ; + RECT 0.048 57.216 66.452 57.312 ; + RECT 0.048 57.984 66.452 58.080 ; + RECT 0.048 58.752 66.452 58.848 ; + RECT 0.048 59.520 66.452 59.616 ; + RECT 0.048 60.288 66.452 60.384 ; + RECT 0.048 61.056 66.452 61.152 ; + RECT 0.048 61.824 66.452 61.920 ; + RECT 0.048 62.592 66.452 62.688 ; + RECT 0.048 63.360 66.452 63.456 ; + RECT 0.048 64.128 66.452 64.224 ; + RECT 0.048 64.896 66.452 64.992 ; + RECT 0.048 65.664 66.452 65.760 ; + RECT 0.048 66.432 66.452 66.528 ; + RECT 0.048 67.200 66.452 67.296 ; + RECT 0.048 67.968 66.452 68.064 ; + RECT 0.048 68.736 66.452 68.832 ; + RECT 0.048 69.504 66.452 69.600 ; + RECT 0.048 70.272 66.452 70.368 ; + RECT 0.048 71.040 66.452 71.136 ; + RECT 0.048 71.808 66.452 71.904 ; + RECT 0.048 72.576 66.452 72.672 ; + RECT 0.048 73.344 66.452 73.440 ; + RECT 0.048 74.112 66.452 74.208 ; + RECT 0.048 74.880 66.452 74.976 ; + RECT 0.048 75.648 66.452 75.744 ; + RECT 0.048 76.416 66.452 76.512 ; + RECT 0.048 77.184 66.452 77.280 ; + RECT 0.048 77.952 66.452 78.048 ; + RECT 0.048 78.720 66.452 78.816 ; + RECT 0.048 79.488 66.452 79.584 ; + RECT 0.048 80.256 66.452 80.352 ; + RECT 0.048 81.024 66.452 81.120 ; + RECT 0.048 81.792 66.452 81.888 ; + RECT 0.048 82.560 66.452 82.656 ; + RECT 0.048 83.328 66.452 83.424 ; + RECT 0.048 84.096 66.452 84.192 ; + RECT 0.048 84.864 66.452 84.960 ; + RECT 0.048 85.632 66.452 85.728 ; + RECT 0.048 86.400 66.452 86.496 ; + RECT 0.048 87.168 66.452 87.264 ; + RECT 0.048 87.936 66.452 88.032 ; + RECT 0.048 88.704 66.452 88.800 ; + RECT 0.048 89.472 66.452 89.568 ; + RECT 0.048 90.240 66.452 90.336 ; + RECT 0.048 91.008 66.452 91.104 ; + RECT 0.048 91.776 66.452 91.872 ; + RECT 0.048 92.544 66.452 92.640 ; + RECT 0.048 93.312 66.452 93.408 ; + RECT 0.048 94.080 66.452 94.176 ; + RECT 0.048 94.848 66.452 94.944 ; + RECT 0.048 95.616 66.452 95.712 ; + RECT 0.048 96.384 66.452 96.480 ; + RECT 0.048 97.152 66.452 97.248 ; + RECT 0.048 97.920 66.452 98.016 ; + RECT 0.048 98.688 66.452 98.784 ; + RECT 0.048 99.456 66.452 99.552 ; + RECT 0.048 100.224 66.452 100.320 ; + RECT 0.048 100.992 66.452 101.088 ; + RECT 0.048 101.760 66.452 101.856 ; + RECT 0.048 102.528 66.452 102.624 ; + RECT 0.048 103.296 66.452 103.392 ; + RECT 0.048 104.064 66.452 104.160 ; + RECT 0.048 104.832 66.452 104.928 ; + RECT 0.048 105.600 66.452 105.696 ; + RECT 0.048 106.368 66.452 106.464 ; + RECT 0.048 107.136 66.452 107.232 ; + RECT 0.048 107.904 66.452 108.000 ; + RECT 0.048 108.672 66.452 108.768 ; + RECT 0.048 109.440 66.452 109.536 ; + RECT 0.048 110.208 66.452 110.304 ; + RECT 0.048 110.976 66.452 111.072 ; + RECT 0.048 111.744 66.452 111.840 ; + RECT 0.048 112.512 66.452 112.608 ; + RECT 0.048 113.280 66.452 113.376 ; + RECT 0.048 114.048 66.452 114.144 ; + RECT 0.048 114.816 66.452 114.912 ; + RECT 0.048 115.584 66.452 115.680 ; + RECT 0.048 116.352 66.452 116.448 ; + RECT 0.048 117.120 66.452 117.216 ; + RECT 0.048 117.888 66.452 117.984 ; + RECT 0.048 118.656 66.452 118.752 ; + RECT 0.048 119.424 66.452 119.520 ; + RECT 0.048 120.192 66.452 120.288 ; + RECT 0.048 120.960 66.452 121.056 ; + RECT 0.048 121.728 66.452 121.824 ; + RECT 0.048 122.496 66.452 122.592 ; + RECT 0.048 123.264 66.452 123.360 ; + RECT 0.048 124.032 66.452 124.128 ; + RECT 0.048 124.800 66.452 124.896 ; + RECT 0.048 125.568 66.452 125.664 ; + RECT 0.048 126.336 66.452 126.432 ; + RECT 0.048 127.104 66.452 127.200 ; + RECT 0.048 127.872 66.452 127.968 ; + RECT 0.048 128.640 66.452 128.736 ; + RECT 0.048 129.408 66.452 129.504 ; + RECT 0.048 130.176 66.452 130.272 ; + RECT 0.048 130.944 66.452 131.040 ; + RECT 0.048 131.712 66.452 131.808 ; + RECT 0.048 132.480 66.452 132.576 ; + RECT 0.048 133.248 66.452 133.344 ; + RECT 0.048 134.016 66.452 134.112 ; + RECT 0.048 134.784 66.452 134.880 ; + RECT 0.048 135.552 66.452 135.648 ; + RECT 0.048 136.320 66.452 136.416 ; + RECT 0.048 137.088 66.452 137.184 ; + RECT 0.048 137.856 66.452 137.952 ; + RECT 0.048 138.624 66.452 138.720 ; + RECT 0.048 139.392 66.452 139.488 ; + RECT 0.048 140.160 66.452 140.256 ; + RECT 0.048 140.928 66.452 141.024 ; + RECT 0.048 141.696 66.452 141.792 ; + RECT 0.048 142.464 66.452 142.560 ; + RECT 0.048 143.232 66.452 143.328 ; + RECT 0.048 144.000 66.452 144.096 ; + RECT 0.048 144.768 66.452 144.864 ; + RECT 0.048 145.536 66.452 145.632 ; + RECT 0.048 146.304 66.452 146.400 ; + RECT 0.048 147.072 66.452 147.168 ; + RECT 0.048 147.840 66.452 147.936 ; + RECT 0.048 148.608 66.452 148.704 ; + RECT 0.048 149.376 66.452 149.472 ; + RECT 0.048 150.144 66.452 150.240 ; + RECT 0.048 150.912 66.452 151.008 ; + RECT 0.048 151.680 66.452 151.776 ; + RECT 0.048 152.448 66.452 152.544 ; + RECT 0.048 153.216 66.452 153.312 ; + RECT 0.048 153.984 66.452 154.080 ; + RECT 0.048 154.752 66.452 154.848 ; + RECT 0.048 155.520 66.452 155.616 ; + RECT 0.048 156.288 66.452 156.384 ; + RECT 0.048 157.056 66.452 157.152 ; + RECT 0.048 157.824 66.452 157.920 ; + RECT 0.048 158.592 66.452 158.688 ; + RECT 0.048 159.360 66.452 159.456 ; + RECT 0.048 160.128 66.452 160.224 ; + RECT 0.048 160.896 66.452 160.992 ; + RECT 0.048 161.664 66.452 161.760 ; + RECT 0.048 162.432 66.452 162.528 ; + RECT 0.048 163.200 66.452 163.296 ; + RECT 0.048 163.968 66.452 164.064 ; + RECT 0.048 164.736 66.452 164.832 ; + RECT 0.048 165.504 66.452 165.600 ; + RECT 0.048 166.272 66.452 166.368 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 66.452 0.096 ; + RECT 0.048 0.768 66.452 0.864 ; + RECT 0.048 1.536 66.452 1.632 ; + RECT 0.048 2.304 66.452 2.400 ; + RECT 0.048 3.072 66.452 3.168 ; + RECT 0.048 3.840 66.452 3.936 ; + RECT 0.048 4.608 66.452 4.704 ; + RECT 0.048 5.376 66.452 5.472 ; + RECT 0.048 6.144 66.452 6.240 ; + RECT 0.048 6.912 66.452 7.008 ; + RECT 0.048 7.680 66.452 7.776 ; + RECT 0.048 8.448 66.452 8.544 ; + RECT 0.048 9.216 66.452 9.312 ; + RECT 0.048 9.984 66.452 10.080 ; + RECT 0.048 10.752 66.452 10.848 ; + RECT 0.048 11.520 66.452 11.616 ; + RECT 0.048 12.288 66.452 12.384 ; + RECT 0.048 13.056 66.452 13.152 ; + RECT 0.048 13.824 66.452 13.920 ; + RECT 0.048 14.592 66.452 14.688 ; + RECT 0.048 15.360 66.452 15.456 ; + RECT 0.048 16.128 66.452 16.224 ; + RECT 0.048 16.896 66.452 16.992 ; + RECT 0.048 17.664 66.452 17.760 ; + RECT 0.048 18.432 66.452 18.528 ; + RECT 0.048 19.200 66.452 19.296 ; + RECT 0.048 19.968 66.452 20.064 ; + RECT 0.048 20.736 66.452 20.832 ; + RECT 0.048 21.504 66.452 21.600 ; + RECT 0.048 22.272 66.452 22.368 ; + RECT 0.048 23.040 66.452 23.136 ; + RECT 0.048 23.808 66.452 23.904 ; + RECT 0.048 24.576 66.452 24.672 ; + RECT 0.048 25.344 66.452 25.440 ; + RECT 0.048 26.112 66.452 26.208 ; + RECT 0.048 26.880 66.452 26.976 ; + RECT 0.048 27.648 66.452 27.744 ; + RECT 0.048 28.416 66.452 28.512 ; + RECT 0.048 29.184 66.452 29.280 ; + RECT 0.048 29.952 66.452 30.048 ; + RECT 0.048 30.720 66.452 30.816 ; + RECT 0.048 31.488 66.452 31.584 ; + RECT 0.048 32.256 66.452 32.352 ; + RECT 0.048 33.024 66.452 33.120 ; + RECT 0.048 33.792 66.452 33.888 ; + RECT 0.048 34.560 66.452 34.656 ; + RECT 0.048 35.328 66.452 35.424 ; + RECT 0.048 36.096 66.452 36.192 ; + RECT 0.048 36.864 66.452 36.960 ; + RECT 0.048 37.632 66.452 37.728 ; + RECT 0.048 38.400 66.452 38.496 ; + RECT 0.048 39.168 66.452 39.264 ; + RECT 0.048 39.936 66.452 40.032 ; + RECT 0.048 40.704 66.452 40.800 ; + RECT 0.048 41.472 66.452 41.568 ; + RECT 0.048 42.240 66.452 42.336 ; + RECT 0.048 43.008 66.452 43.104 ; + RECT 0.048 43.776 66.452 43.872 ; + RECT 0.048 44.544 66.452 44.640 ; + RECT 0.048 45.312 66.452 45.408 ; + RECT 0.048 46.080 66.452 46.176 ; + RECT 0.048 46.848 66.452 46.944 ; + RECT 0.048 47.616 66.452 47.712 ; + RECT 0.048 48.384 66.452 48.480 ; + RECT 0.048 49.152 66.452 49.248 ; + RECT 0.048 49.920 66.452 50.016 ; + RECT 0.048 50.688 66.452 50.784 ; + RECT 0.048 51.456 66.452 51.552 ; + RECT 0.048 52.224 66.452 52.320 ; + RECT 0.048 52.992 66.452 53.088 ; + RECT 0.048 53.760 66.452 53.856 ; + RECT 0.048 54.528 66.452 54.624 ; + RECT 0.048 55.296 66.452 55.392 ; + RECT 0.048 56.064 66.452 56.160 ; + RECT 0.048 56.832 66.452 56.928 ; + RECT 0.048 57.600 66.452 57.696 ; + RECT 0.048 58.368 66.452 58.464 ; + RECT 0.048 59.136 66.452 59.232 ; + RECT 0.048 59.904 66.452 60.000 ; + RECT 0.048 60.672 66.452 60.768 ; + RECT 0.048 61.440 66.452 61.536 ; + RECT 0.048 62.208 66.452 62.304 ; + RECT 0.048 62.976 66.452 63.072 ; + RECT 0.048 63.744 66.452 63.840 ; + RECT 0.048 64.512 66.452 64.608 ; + RECT 0.048 65.280 66.452 65.376 ; + RECT 0.048 66.048 66.452 66.144 ; + RECT 0.048 66.816 66.452 66.912 ; + RECT 0.048 67.584 66.452 67.680 ; + RECT 0.048 68.352 66.452 68.448 ; + RECT 0.048 69.120 66.452 69.216 ; + RECT 0.048 69.888 66.452 69.984 ; + RECT 0.048 70.656 66.452 70.752 ; + RECT 0.048 71.424 66.452 71.520 ; + RECT 0.048 72.192 66.452 72.288 ; + RECT 0.048 72.960 66.452 73.056 ; + RECT 0.048 73.728 66.452 73.824 ; + RECT 0.048 74.496 66.452 74.592 ; + RECT 0.048 75.264 66.452 75.360 ; + RECT 0.048 76.032 66.452 76.128 ; + RECT 0.048 76.800 66.452 76.896 ; + RECT 0.048 77.568 66.452 77.664 ; + RECT 0.048 78.336 66.452 78.432 ; + RECT 0.048 79.104 66.452 79.200 ; + RECT 0.048 79.872 66.452 79.968 ; + RECT 0.048 80.640 66.452 80.736 ; + RECT 0.048 81.408 66.452 81.504 ; + RECT 0.048 82.176 66.452 82.272 ; + RECT 0.048 82.944 66.452 83.040 ; + RECT 0.048 83.712 66.452 83.808 ; + RECT 0.048 84.480 66.452 84.576 ; + RECT 0.048 85.248 66.452 85.344 ; + RECT 0.048 86.016 66.452 86.112 ; + RECT 0.048 86.784 66.452 86.880 ; + RECT 0.048 87.552 66.452 87.648 ; + RECT 0.048 88.320 66.452 88.416 ; + RECT 0.048 89.088 66.452 89.184 ; + RECT 0.048 89.856 66.452 89.952 ; + RECT 0.048 90.624 66.452 90.720 ; + RECT 0.048 91.392 66.452 91.488 ; + RECT 0.048 92.160 66.452 92.256 ; + RECT 0.048 92.928 66.452 93.024 ; + RECT 0.048 93.696 66.452 93.792 ; + RECT 0.048 94.464 66.452 94.560 ; + RECT 0.048 95.232 66.452 95.328 ; + RECT 0.048 96.000 66.452 96.096 ; + RECT 0.048 96.768 66.452 96.864 ; + RECT 0.048 97.536 66.452 97.632 ; + RECT 0.048 98.304 66.452 98.400 ; + RECT 0.048 99.072 66.452 99.168 ; + RECT 0.048 99.840 66.452 99.936 ; + RECT 0.048 100.608 66.452 100.704 ; + RECT 0.048 101.376 66.452 101.472 ; + RECT 0.048 102.144 66.452 102.240 ; + RECT 0.048 102.912 66.452 103.008 ; + RECT 0.048 103.680 66.452 103.776 ; + RECT 0.048 104.448 66.452 104.544 ; + RECT 0.048 105.216 66.452 105.312 ; + RECT 0.048 105.984 66.452 106.080 ; + RECT 0.048 106.752 66.452 106.848 ; + RECT 0.048 107.520 66.452 107.616 ; + RECT 0.048 108.288 66.452 108.384 ; + RECT 0.048 109.056 66.452 109.152 ; + RECT 0.048 109.824 66.452 109.920 ; + RECT 0.048 110.592 66.452 110.688 ; + RECT 0.048 111.360 66.452 111.456 ; + RECT 0.048 112.128 66.452 112.224 ; + RECT 0.048 112.896 66.452 112.992 ; + RECT 0.048 113.664 66.452 113.760 ; + RECT 0.048 114.432 66.452 114.528 ; + RECT 0.048 115.200 66.452 115.296 ; + RECT 0.048 115.968 66.452 116.064 ; + RECT 0.048 116.736 66.452 116.832 ; + RECT 0.048 117.504 66.452 117.600 ; + RECT 0.048 118.272 66.452 118.368 ; + RECT 0.048 119.040 66.452 119.136 ; + RECT 0.048 119.808 66.452 119.904 ; + RECT 0.048 120.576 66.452 120.672 ; + RECT 0.048 121.344 66.452 121.440 ; + RECT 0.048 122.112 66.452 122.208 ; + RECT 0.048 122.880 66.452 122.976 ; + RECT 0.048 123.648 66.452 123.744 ; + RECT 0.048 124.416 66.452 124.512 ; + RECT 0.048 125.184 66.452 125.280 ; + RECT 0.048 125.952 66.452 126.048 ; + RECT 0.048 126.720 66.452 126.816 ; + RECT 0.048 127.488 66.452 127.584 ; + RECT 0.048 128.256 66.452 128.352 ; + RECT 0.048 129.024 66.452 129.120 ; + RECT 0.048 129.792 66.452 129.888 ; + RECT 0.048 130.560 66.452 130.656 ; + RECT 0.048 131.328 66.452 131.424 ; + RECT 0.048 132.096 66.452 132.192 ; + RECT 0.048 132.864 66.452 132.960 ; + RECT 0.048 133.632 66.452 133.728 ; + RECT 0.048 134.400 66.452 134.496 ; + RECT 0.048 135.168 66.452 135.264 ; + RECT 0.048 135.936 66.452 136.032 ; + RECT 0.048 136.704 66.452 136.800 ; + RECT 0.048 137.472 66.452 137.568 ; + RECT 0.048 138.240 66.452 138.336 ; + RECT 0.048 139.008 66.452 139.104 ; + RECT 0.048 139.776 66.452 139.872 ; + RECT 0.048 140.544 66.452 140.640 ; + RECT 0.048 141.312 66.452 141.408 ; + RECT 0.048 142.080 66.452 142.176 ; + RECT 0.048 142.848 66.452 142.944 ; + RECT 0.048 143.616 66.452 143.712 ; + RECT 0.048 144.384 66.452 144.480 ; + RECT 0.048 145.152 66.452 145.248 ; + RECT 0.048 145.920 66.452 146.016 ; + RECT 0.048 146.688 66.452 146.784 ; + RECT 0.048 147.456 66.452 147.552 ; + RECT 0.048 148.224 66.452 148.320 ; + RECT 0.048 148.992 66.452 149.088 ; + RECT 0.048 149.760 66.452 149.856 ; + RECT 0.048 150.528 66.452 150.624 ; + RECT 0.048 151.296 66.452 151.392 ; + RECT 0.048 152.064 66.452 152.160 ; + RECT 0.048 152.832 66.452 152.928 ; + RECT 0.048 153.600 66.452 153.696 ; + RECT 0.048 154.368 66.452 154.464 ; + RECT 0.048 155.136 66.452 155.232 ; + RECT 0.048 155.904 66.452 156.000 ; + RECT 0.048 156.672 66.452 156.768 ; + RECT 0.048 157.440 66.452 157.536 ; + RECT 0.048 158.208 66.452 158.304 ; + RECT 0.048 158.976 66.452 159.072 ; + RECT 0.048 159.744 66.452 159.840 ; + RECT 0.048 160.512 66.452 160.608 ; + RECT 0.048 161.280 66.452 161.376 ; + RECT 0.048 162.048 66.452 162.144 ; + RECT 0.048 162.816 66.452 162.912 ; + RECT 0.048 163.584 66.452 163.680 ; + RECT 0.048 164.352 66.452 164.448 ; + RECT 0.048 165.120 66.452 165.216 ; + RECT 0.048 165.888 66.452 165.984 ; + END + END VSS + OBS + LAYER M1 ; + RECT 0 0 66.500 166.600 ; + LAYER M2 ; + RECT 0 0 66.500 166.600 ; + LAYER M3 ; + RECT 0 0 66.500 166.600 ; + LAYER M4 ; + RECT 0 0 66.500 166.600 ; + END +END fakeram_2048x128 + +END LIBRARY diff --git a/flow/platforms/asap7/lef/fakeram_512x128.lef b/flow/platforms/asap7/lef/fakeram_512x128.lef new file mode 100644 index 0000000000..b6c73a2b74 --- /dev/null +++ b/flow/platforms/asap7/lef/fakeram_512x128.lef @@ -0,0 +1,2565 @@ +# Generated by FakeRAM 2.0 +VERSION 5.7 ; +BUSBITCHARS "[]" ; +PROPERTYDEFINITIONS + MACRO width INTEGER ; + MACRO depth INTEGER ; + MACRO banks INTEGER ; +END PROPERTYDEFINITIONS +MACRO fakeram_512x128 + PROPERTY width 128 ; + PROPERTY depth 512 ; + PROPERTY banks 4 ; + FOREIGN fakeram_512x128 0 0 ; + SYMMETRY X Y R90 ; + SIZE 66.500 BY 42.000 ; + CLASS BLOCK ; + PIN rd_out[0] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.048 0.024 0.072 ; + END + END rd_out[0] + PIN rd_out[1] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.192 0.024 0.216 ; + END + END rd_out[1] + PIN rd_out[2] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.336 0.024 0.360 ; + END + END rd_out[2] + PIN rd_out[3] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.480 0.024 0.504 ; + END + END rd_out[3] + PIN rd_out[4] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.624 0.024 0.648 ; + END + END rd_out[4] + PIN rd_out[5] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.768 0.024 0.792 ; + END + END rd_out[5] + PIN rd_out[6] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 0.912 0.024 0.936 ; + END + END rd_out[6] + PIN rd_out[7] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.056 0.024 1.080 ; + END + END rd_out[7] + PIN rd_out[8] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.200 0.024 1.224 ; + END + END rd_out[8] + PIN rd_out[9] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.344 0.024 1.368 ; + END + END rd_out[9] + PIN rd_out[10] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.488 0.024 1.512 ; + END + END rd_out[10] + PIN rd_out[11] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.632 0.024 1.656 ; + END + END rd_out[11] + PIN rd_out[12] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.776 0.024 1.800 ; + END + END rd_out[12] + PIN rd_out[13] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 1.920 0.024 1.944 ; + END + END rd_out[13] + PIN rd_out[14] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.064 0.024 2.088 ; + END + END rd_out[14] + PIN rd_out[15] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.208 0.024 2.232 ; + END + END rd_out[15] + PIN rd_out[16] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.352 0.024 2.376 ; + END + END rd_out[16] + PIN rd_out[17] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.496 0.024 2.520 ; + END + END rd_out[17] + PIN rd_out[18] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.640 0.024 2.664 ; + END + END rd_out[18] + PIN rd_out[19] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.784 0.024 2.808 ; + END + END rd_out[19] + PIN rd_out[20] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 2.928 0.024 2.952 ; + END + END rd_out[20] + PIN rd_out[21] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.072 0.024 3.096 ; + END + END rd_out[21] + PIN rd_out[22] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.216 0.024 3.240 ; + END + END rd_out[22] + PIN rd_out[23] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.360 0.024 3.384 ; + END + END rd_out[23] + PIN rd_out[24] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.504 0.024 3.528 ; + END + END rd_out[24] + PIN rd_out[25] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.648 0.024 3.672 ; + END + END rd_out[25] + PIN rd_out[26] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.792 0.024 3.816 ; + END + END rd_out[26] + PIN rd_out[27] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 3.936 0.024 3.960 ; + END + END rd_out[27] + PIN rd_out[28] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.080 0.024 4.104 ; + END + END rd_out[28] + PIN rd_out[29] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.224 0.024 4.248 ; + END + END rd_out[29] + PIN rd_out[30] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.368 0.024 4.392 ; + END + END rd_out[30] + PIN rd_out[31] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.512 0.024 4.536 ; + END + END rd_out[31] + PIN rd_out[32] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.656 0.024 4.680 ; + END + END rd_out[32] + PIN rd_out[33] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.800 0.024 4.824 ; + END + END rd_out[33] + PIN rd_out[34] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 4.944 0.024 4.968 ; + END + END rd_out[34] + PIN rd_out[35] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.088 0.024 5.112 ; + END + END rd_out[35] + PIN rd_out[36] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.232 0.024 5.256 ; + END + END rd_out[36] + PIN rd_out[37] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.376 0.024 5.400 ; + END + END rd_out[37] + PIN rd_out[38] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.520 0.024 5.544 ; + END + END rd_out[38] + PIN rd_out[39] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.664 0.024 5.688 ; + END + END rd_out[39] + PIN rd_out[40] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.808 0.024 5.832 ; + END + END rd_out[40] + PIN rd_out[41] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 5.952 0.024 5.976 ; + END + END rd_out[41] + PIN rd_out[42] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.096 0.024 6.120 ; + END + END rd_out[42] + PIN rd_out[43] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.240 0.024 6.264 ; + END + END rd_out[43] + PIN rd_out[44] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.384 0.024 6.408 ; + END + END rd_out[44] + PIN rd_out[45] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.528 0.024 6.552 ; + END + END rd_out[45] + PIN rd_out[46] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.672 0.024 6.696 ; + END + END rd_out[46] + PIN rd_out[47] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.816 0.024 6.840 ; + END + END rd_out[47] + PIN rd_out[48] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 6.960 0.024 6.984 ; + END + END rd_out[48] + PIN rd_out[49] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.104 0.024 7.128 ; + END + END rd_out[49] + PIN rd_out[50] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.248 0.024 7.272 ; + END + END rd_out[50] + PIN rd_out[51] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.392 0.024 7.416 ; + END + END rd_out[51] + PIN rd_out[52] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.536 0.024 7.560 ; + END + END rd_out[52] + PIN rd_out[53] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.680 0.024 7.704 ; + END + END rd_out[53] + PIN rd_out[54] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.824 0.024 7.848 ; + END + END rd_out[54] + PIN rd_out[55] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 7.968 0.024 7.992 ; + END + END rd_out[55] + PIN rd_out[56] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.112 0.024 8.136 ; + END + END rd_out[56] + PIN rd_out[57] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.256 0.024 8.280 ; + END + END rd_out[57] + PIN rd_out[58] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.400 0.024 8.424 ; + END + END rd_out[58] + PIN rd_out[59] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.544 0.024 8.568 ; + END + END rd_out[59] + PIN rd_out[60] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.688 0.024 8.712 ; + END + END rd_out[60] + PIN rd_out[61] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.832 0.024 8.856 ; + END + END rd_out[61] + PIN rd_out[62] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 8.976 0.024 9.000 ; + END + END rd_out[62] + PIN rd_out[63] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.120 0.024 9.144 ; + END + END rd_out[63] + PIN rd_out[64] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.264 0.024 9.288 ; + END + END rd_out[64] + PIN rd_out[65] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.408 0.024 9.432 ; + END + END rd_out[65] + PIN rd_out[66] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.552 0.024 9.576 ; + END + END rd_out[66] + PIN rd_out[67] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.696 0.024 9.720 ; + END + END rd_out[67] + PIN rd_out[68] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.840 0.024 9.864 ; + END + END rd_out[68] + PIN rd_out[69] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 9.984 0.024 10.008 ; + END + END rd_out[69] + PIN rd_out[70] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.128 0.024 10.152 ; + END + END rd_out[70] + PIN rd_out[71] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.272 0.024 10.296 ; + END + END rd_out[71] + PIN rd_out[72] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.416 0.024 10.440 ; + END + END rd_out[72] + PIN rd_out[73] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.560 0.024 10.584 ; + END + END rd_out[73] + PIN rd_out[74] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.704 0.024 10.728 ; + END + END rd_out[74] + PIN rd_out[75] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.848 0.024 10.872 ; + END + END rd_out[75] + PIN rd_out[76] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 10.992 0.024 11.016 ; + END + END rd_out[76] + PIN rd_out[77] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.136 0.024 11.160 ; + END + END rd_out[77] + PIN rd_out[78] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.280 0.024 11.304 ; + END + END rd_out[78] + PIN rd_out[79] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.424 0.024 11.448 ; + END + END rd_out[79] + PIN rd_out[80] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.568 0.024 11.592 ; + END + END rd_out[80] + PIN rd_out[81] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.712 0.024 11.736 ; + END + END rd_out[81] + PIN rd_out[82] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 11.856 0.024 11.880 ; + END + END rd_out[82] + PIN rd_out[83] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.000 0.024 12.024 ; + END + END rd_out[83] + PIN rd_out[84] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.144 0.024 12.168 ; + END + END rd_out[84] + PIN rd_out[85] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.288 0.024 12.312 ; + END + END rd_out[85] + PIN rd_out[86] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.432 0.024 12.456 ; + END + END rd_out[86] + PIN rd_out[87] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.576 0.024 12.600 ; + END + END rd_out[87] + PIN rd_out[88] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.720 0.024 12.744 ; + END + END rd_out[88] + PIN rd_out[89] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 12.864 0.024 12.888 ; + END + END rd_out[89] + PIN rd_out[90] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.008 0.024 13.032 ; + END + END rd_out[90] + PIN rd_out[91] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.152 0.024 13.176 ; + END + END rd_out[91] + PIN rd_out[92] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.296 0.024 13.320 ; + END + END rd_out[92] + PIN rd_out[93] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.440 0.024 13.464 ; + END + END rd_out[93] + PIN rd_out[94] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.584 0.024 13.608 ; + END + END rd_out[94] + PIN rd_out[95] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.728 0.024 13.752 ; + END + END rd_out[95] + PIN rd_out[96] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 13.872 0.024 13.896 ; + END + END rd_out[96] + PIN rd_out[97] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.016 0.024 14.040 ; + END + END rd_out[97] + PIN rd_out[98] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.160 0.024 14.184 ; + END + END rd_out[98] + PIN rd_out[99] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.304 0.024 14.328 ; + END + END rd_out[99] + PIN rd_out[100] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.448 0.024 14.472 ; + END + END rd_out[100] + PIN rd_out[101] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.592 0.024 14.616 ; + END + END rd_out[101] + PIN rd_out[102] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.736 0.024 14.760 ; + END + END rd_out[102] + PIN rd_out[103] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 14.880 0.024 14.904 ; + END + END rd_out[103] + PIN rd_out[104] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.024 0.024 15.048 ; + END + END rd_out[104] + PIN rd_out[105] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.168 0.024 15.192 ; + END + END rd_out[105] + PIN rd_out[106] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.312 0.024 15.336 ; + END + END rd_out[106] + PIN rd_out[107] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.456 0.024 15.480 ; + END + END rd_out[107] + PIN rd_out[108] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.600 0.024 15.624 ; + END + END rd_out[108] + PIN rd_out[109] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.744 0.024 15.768 ; + END + END rd_out[109] + PIN rd_out[110] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 15.888 0.024 15.912 ; + END + END rd_out[110] + PIN rd_out[111] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.032 0.024 16.056 ; + END + END rd_out[111] + PIN rd_out[112] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.176 0.024 16.200 ; + END + END rd_out[112] + PIN rd_out[113] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.320 0.024 16.344 ; + END + END rd_out[113] + PIN rd_out[114] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.464 0.024 16.488 ; + END + END rd_out[114] + PIN rd_out[115] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.608 0.024 16.632 ; + END + END rd_out[115] + PIN rd_out[116] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.752 0.024 16.776 ; + END + END rd_out[116] + PIN rd_out[117] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 16.896 0.024 16.920 ; + END + END rd_out[117] + PIN rd_out[118] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.040 0.024 17.064 ; + END + END rd_out[118] + PIN rd_out[119] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.184 0.024 17.208 ; + END + END rd_out[119] + PIN rd_out[120] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.328 0.024 17.352 ; + END + END rd_out[120] + PIN rd_out[121] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.472 0.024 17.496 ; + END + END rd_out[121] + PIN rd_out[122] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.616 0.024 17.640 ; + END + END rd_out[122] + PIN rd_out[123] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.760 0.024 17.784 ; + END + END rd_out[123] + PIN rd_out[124] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 17.904 0.024 17.928 ; + END + END rd_out[124] + PIN rd_out[125] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.048 0.024 18.072 ; + END + END rd_out[125] + PIN rd_out[126] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.192 0.024 18.216 ; + END + END rd_out[126] + PIN rd_out[127] + DIRECTION OUTPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 18.336 0.024 18.360 ; + END + END rd_out[127] + PIN wd_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.584 0.024 19.608 ; + END + END wd_in[0] + PIN wd_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.728 0.024 19.752 ; + END + END wd_in[1] + PIN wd_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 19.872 0.024 19.896 ; + END + END wd_in[2] + PIN wd_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.016 0.024 20.040 ; + END + END wd_in[3] + PIN wd_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.160 0.024 20.184 ; + END + END wd_in[4] + PIN wd_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.304 0.024 20.328 ; + END + END wd_in[5] + PIN wd_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.448 0.024 20.472 ; + END + END wd_in[6] + PIN wd_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.592 0.024 20.616 ; + END + END wd_in[7] + PIN wd_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.736 0.024 20.760 ; + END + END wd_in[8] + PIN wd_in[9] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 20.880 0.024 20.904 ; + END + END wd_in[9] + PIN wd_in[10] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.024 0.024 21.048 ; + END + END wd_in[10] + PIN wd_in[11] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.168 0.024 21.192 ; + END + END wd_in[11] + PIN wd_in[12] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.312 0.024 21.336 ; + END + END wd_in[12] + PIN wd_in[13] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.456 0.024 21.480 ; + END + END wd_in[13] + PIN wd_in[14] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.600 0.024 21.624 ; + END + END wd_in[14] + PIN wd_in[15] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.744 0.024 21.768 ; + END + END wd_in[15] + PIN wd_in[16] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 21.888 0.024 21.912 ; + END + END wd_in[16] + PIN wd_in[17] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.032 0.024 22.056 ; + END + END wd_in[17] + PIN wd_in[18] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.176 0.024 22.200 ; + END + END wd_in[18] + PIN wd_in[19] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.320 0.024 22.344 ; + END + END wd_in[19] + PIN wd_in[20] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.464 0.024 22.488 ; + END + END wd_in[20] + PIN wd_in[21] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.608 0.024 22.632 ; + END + END wd_in[21] + PIN wd_in[22] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.752 0.024 22.776 ; + END + END wd_in[22] + PIN wd_in[23] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 22.896 0.024 22.920 ; + END + END wd_in[23] + PIN wd_in[24] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.040 0.024 23.064 ; + END + END wd_in[24] + PIN wd_in[25] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.184 0.024 23.208 ; + END + END wd_in[25] + PIN wd_in[26] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.328 0.024 23.352 ; + END + END wd_in[26] + PIN wd_in[27] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.472 0.024 23.496 ; + END + END wd_in[27] + PIN wd_in[28] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.616 0.024 23.640 ; + END + END wd_in[28] + PIN wd_in[29] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.760 0.024 23.784 ; + END + END wd_in[29] + PIN wd_in[30] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 23.904 0.024 23.928 ; + END + END wd_in[30] + PIN wd_in[31] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.048 0.024 24.072 ; + END + END wd_in[31] + PIN wd_in[32] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.192 0.024 24.216 ; + END + END wd_in[32] + PIN wd_in[33] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.336 0.024 24.360 ; + END + END wd_in[33] + PIN wd_in[34] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.480 0.024 24.504 ; + END + END wd_in[34] + PIN wd_in[35] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.624 0.024 24.648 ; + END + END wd_in[35] + PIN wd_in[36] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.768 0.024 24.792 ; + END + END wd_in[36] + PIN wd_in[37] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 24.912 0.024 24.936 ; + END + END wd_in[37] + PIN wd_in[38] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.056 0.024 25.080 ; + END + END wd_in[38] + PIN wd_in[39] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.200 0.024 25.224 ; + END + END wd_in[39] + PIN wd_in[40] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.344 0.024 25.368 ; + END + END wd_in[40] + PIN wd_in[41] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.488 0.024 25.512 ; + END + END wd_in[41] + PIN wd_in[42] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.632 0.024 25.656 ; + END + END wd_in[42] + PIN wd_in[43] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.776 0.024 25.800 ; + END + END wd_in[43] + PIN wd_in[44] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 25.920 0.024 25.944 ; + END + END wd_in[44] + PIN wd_in[45] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.064 0.024 26.088 ; + END + END wd_in[45] + PIN wd_in[46] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.208 0.024 26.232 ; + END + END wd_in[46] + PIN wd_in[47] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.352 0.024 26.376 ; + END + END wd_in[47] + PIN wd_in[48] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.496 0.024 26.520 ; + END + END wd_in[48] + PIN wd_in[49] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.640 0.024 26.664 ; + END + END wd_in[49] + PIN wd_in[50] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.784 0.024 26.808 ; + END + END wd_in[50] + PIN wd_in[51] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 26.928 0.024 26.952 ; + END + END wd_in[51] + PIN wd_in[52] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.072 0.024 27.096 ; + END + END wd_in[52] + PIN wd_in[53] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.216 0.024 27.240 ; + END + END wd_in[53] + PIN wd_in[54] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.360 0.024 27.384 ; + END + END wd_in[54] + PIN wd_in[55] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.504 0.024 27.528 ; + END + END wd_in[55] + PIN wd_in[56] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.648 0.024 27.672 ; + END + END wd_in[56] + PIN wd_in[57] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.792 0.024 27.816 ; + END + END wd_in[57] + PIN wd_in[58] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 27.936 0.024 27.960 ; + END + END wd_in[58] + PIN wd_in[59] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.080 0.024 28.104 ; + END + END wd_in[59] + PIN wd_in[60] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.224 0.024 28.248 ; + END + END wd_in[60] + PIN wd_in[61] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.368 0.024 28.392 ; + END + END wd_in[61] + PIN wd_in[62] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.512 0.024 28.536 ; + END + END wd_in[62] + PIN wd_in[63] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.656 0.024 28.680 ; + END + END wd_in[63] + PIN wd_in[64] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.800 0.024 28.824 ; + END + END wd_in[64] + PIN wd_in[65] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 28.944 0.024 28.968 ; + END + END wd_in[65] + PIN wd_in[66] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.088 0.024 29.112 ; + END + END wd_in[66] + PIN wd_in[67] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.232 0.024 29.256 ; + END + END wd_in[67] + PIN wd_in[68] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.376 0.024 29.400 ; + END + END wd_in[68] + PIN wd_in[69] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.520 0.024 29.544 ; + END + END wd_in[69] + PIN wd_in[70] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.664 0.024 29.688 ; + END + END wd_in[70] + PIN wd_in[71] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.808 0.024 29.832 ; + END + END wd_in[71] + PIN wd_in[72] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 29.952 0.024 29.976 ; + END + END wd_in[72] + PIN wd_in[73] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.096 0.024 30.120 ; + END + END wd_in[73] + PIN wd_in[74] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.240 0.024 30.264 ; + END + END wd_in[74] + PIN wd_in[75] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.384 0.024 30.408 ; + END + END wd_in[75] + PIN wd_in[76] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.528 0.024 30.552 ; + END + END wd_in[76] + PIN wd_in[77] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.672 0.024 30.696 ; + END + END wd_in[77] + PIN wd_in[78] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.816 0.024 30.840 ; + END + END wd_in[78] + PIN wd_in[79] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 30.960 0.024 30.984 ; + END + END wd_in[79] + PIN wd_in[80] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.104 0.024 31.128 ; + END + END wd_in[80] + PIN wd_in[81] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.248 0.024 31.272 ; + END + END wd_in[81] + PIN wd_in[82] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.392 0.024 31.416 ; + END + END wd_in[82] + PIN wd_in[83] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.536 0.024 31.560 ; + END + END wd_in[83] + PIN wd_in[84] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.680 0.024 31.704 ; + END + END wd_in[84] + PIN wd_in[85] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.824 0.024 31.848 ; + END + END wd_in[85] + PIN wd_in[86] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 31.968 0.024 31.992 ; + END + END wd_in[86] + PIN wd_in[87] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.112 0.024 32.136 ; + END + END wd_in[87] + PIN wd_in[88] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.256 0.024 32.280 ; + END + END wd_in[88] + PIN wd_in[89] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.400 0.024 32.424 ; + END + END wd_in[89] + PIN wd_in[90] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.544 0.024 32.568 ; + END + END wd_in[90] + PIN wd_in[91] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.688 0.024 32.712 ; + END + END wd_in[91] + PIN wd_in[92] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.832 0.024 32.856 ; + END + END wd_in[92] + PIN wd_in[93] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 32.976 0.024 33.000 ; + END + END wd_in[93] + PIN wd_in[94] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.120 0.024 33.144 ; + END + END wd_in[94] + PIN wd_in[95] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.264 0.024 33.288 ; + END + END wd_in[95] + PIN wd_in[96] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.408 0.024 33.432 ; + END + END wd_in[96] + PIN wd_in[97] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.552 0.024 33.576 ; + END + END wd_in[97] + PIN wd_in[98] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.696 0.024 33.720 ; + END + END wd_in[98] + PIN wd_in[99] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.840 0.024 33.864 ; + END + END wd_in[99] + PIN wd_in[100] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 33.984 0.024 34.008 ; + END + END wd_in[100] + PIN wd_in[101] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.128 0.024 34.152 ; + END + END wd_in[101] + PIN wd_in[102] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.272 0.024 34.296 ; + END + END wd_in[102] + PIN wd_in[103] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.416 0.024 34.440 ; + END + END wd_in[103] + PIN wd_in[104] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.560 0.024 34.584 ; + END + END wd_in[104] + PIN wd_in[105] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.704 0.024 34.728 ; + END + END wd_in[105] + PIN wd_in[106] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.848 0.024 34.872 ; + END + END wd_in[106] + PIN wd_in[107] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 34.992 0.024 35.016 ; + END + END wd_in[107] + PIN wd_in[108] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.136 0.024 35.160 ; + END + END wd_in[108] + PIN wd_in[109] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.280 0.024 35.304 ; + END + END wd_in[109] + PIN wd_in[110] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.424 0.024 35.448 ; + END + END wd_in[110] + PIN wd_in[111] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.568 0.024 35.592 ; + END + END wd_in[111] + PIN wd_in[112] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.712 0.024 35.736 ; + END + END wd_in[112] + PIN wd_in[113] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 35.856 0.024 35.880 ; + END + END wd_in[113] + PIN wd_in[114] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.000 0.024 36.024 ; + END + END wd_in[114] + PIN wd_in[115] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.144 0.024 36.168 ; + END + END wd_in[115] + PIN wd_in[116] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.288 0.024 36.312 ; + END + END wd_in[116] + PIN wd_in[117] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.432 0.024 36.456 ; + END + END wd_in[117] + PIN wd_in[118] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.576 0.024 36.600 ; + END + END wd_in[118] + PIN wd_in[119] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.720 0.024 36.744 ; + END + END wd_in[119] + PIN wd_in[120] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 36.864 0.024 36.888 ; + END + END wd_in[120] + PIN wd_in[121] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.008 0.024 37.032 ; + END + END wd_in[121] + PIN wd_in[122] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.152 0.024 37.176 ; + END + END wd_in[122] + PIN wd_in[123] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.296 0.024 37.320 ; + END + END wd_in[123] + PIN wd_in[124] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.440 0.024 37.464 ; + END + END wd_in[124] + PIN wd_in[125] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.584 0.024 37.608 ; + END + END wd_in[125] + PIN wd_in[126] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.728 0.024 37.752 ; + END + END wd_in[126] + PIN wd_in[127] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 37.872 0.024 37.896 ; + END + END wd_in[127] + PIN addr_in[0] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.120 0.024 39.144 ; + END + END addr_in[0] + PIN addr_in[1] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.264 0.024 39.288 ; + END + END addr_in[1] + PIN addr_in[2] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.408 0.024 39.432 ; + END + END addr_in[2] + PIN addr_in[3] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.552 0.024 39.576 ; + END + END addr_in[3] + PIN addr_in[4] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.696 0.024 39.720 ; + END + END addr_in[4] + PIN addr_in[5] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.840 0.024 39.864 ; + END + END addr_in[5] + PIN addr_in[6] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 39.984 0.024 40.008 ; + END + END addr_in[6] + PIN addr_in[7] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.128 0.024 40.152 ; + END + END addr_in[7] + PIN addr_in[8] + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 40.272 0.024 40.296 ; + END + END addr_in[8] + PIN we_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.520 0.024 41.544 ; + END + END we_in + PIN clk + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.664 0.024 41.688 ; + END + END clk + PIN ce_in + DIRECTION INPUT ; + USE SIGNAL ; + SHAPE ABUTMENT ; + PORT + LAYER M4 ; + RECT 0.000 41.808 0.024 41.832 ; + END + END ce_in + PIN VDD + DIRECTION INOUT ; + USE POWER ; + PORT + LAYER M4 ; + RECT 0.048 0.384 66.452 0.480 ; + RECT 0.048 1.152 66.452 1.248 ; + RECT 0.048 1.920 66.452 2.016 ; + RECT 0.048 2.688 66.452 2.784 ; + RECT 0.048 3.456 66.452 3.552 ; + RECT 0.048 4.224 66.452 4.320 ; + RECT 0.048 4.992 66.452 5.088 ; + RECT 0.048 5.760 66.452 5.856 ; + RECT 0.048 6.528 66.452 6.624 ; + RECT 0.048 7.296 66.452 7.392 ; + RECT 0.048 8.064 66.452 8.160 ; + RECT 0.048 8.832 66.452 8.928 ; + RECT 0.048 9.600 66.452 9.696 ; + RECT 0.048 10.368 66.452 10.464 ; + RECT 0.048 11.136 66.452 11.232 ; + RECT 0.048 11.904 66.452 12.000 ; + RECT 0.048 12.672 66.452 12.768 ; + RECT 0.048 13.440 66.452 13.536 ; + RECT 0.048 14.208 66.452 14.304 ; + RECT 0.048 14.976 66.452 15.072 ; + RECT 0.048 15.744 66.452 15.840 ; + RECT 0.048 16.512 66.452 16.608 ; + RECT 0.048 17.280 66.452 17.376 ; + RECT 0.048 18.048 66.452 18.144 ; + RECT 0.048 18.816 66.452 18.912 ; + RECT 0.048 19.584 66.452 19.680 ; + RECT 0.048 20.352 66.452 20.448 ; + RECT 0.048 21.120 66.452 21.216 ; + RECT 0.048 21.888 66.452 21.984 ; + RECT 0.048 22.656 66.452 22.752 ; + RECT 0.048 23.424 66.452 23.520 ; + RECT 0.048 24.192 66.452 24.288 ; + RECT 0.048 24.960 66.452 25.056 ; + RECT 0.048 25.728 66.452 25.824 ; + RECT 0.048 26.496 66.452 26.592 ; + RECT 0.048 27.264 66.452 27.360 ; + RECT 0.048 28.032 66.452 28.128 ; + RECT 0.048 28.800 66.452 28.896 ; + RECT 0.048 29.568 66.452 29.664 ; + RECT 0.048 30.336 66.452 30.432 ; + RECT 0.048 31.104 66.452 31.200 ; + RECT 0.048 31.872 66.452 31.968 ; + RECT 0.048 32.640 66.452 32.736 ; + RECT 0.048 33.408 66.452 33.504 ; + RECT 0.048 34.176 66.452 34.272 ; + RECT 0.048 34.944 66.452 35.040 ; + RECT 0.048 35.712 66.452 35.808 ; + RECT 0.048 36.480 66.452 36.576 ; + RECT 0.048 37.248 66.452 37.344 ; + RECT 0.048 38.016 66.452 38.112 ; + RECT 0.048 38.784 66.452 38.880 ; + RECT 0.048 39.552 66.452 39.648 ; + RECT 0.048 40.320 66.452 40.416 ; + RECT 0.048 41.088 66.452 41.184 ; + RECT 0.048 41.856 66.452 41.952 ; + END + END VDD + PIN VSS + DIRECTION INOUT ; + USE GROUND ; + PORT + LAYER M4 ; + RECT 0.048 0.000 66.452 0.096 ; + RECT 0.048 0.768 66.452 0.864 ; + RECT 0.048 1.536 66.452 1.632 ; + RECT 0.048 2.304 66.452 2.400 ; + RECT 0.048 3.072 66.452 3.168 ; + RECT 0.048 3.840 66.452 3.936 ; + RECT 0.048 4.608 66.452 4.704 ; + RECT 0.048 5.376 66.452 5.472 ; + RECT 0.048 6.144 66.452 6.240 ; + RECT 0.048 6.912 66.452 7.008 ; + RECT 0.048 7.680 66.452 7.776 ; + RECT 0.048 8.448 66.452 8.544 ; + RECT 0.048 9.216 66.452 9.312 ; + RECT 0.048 9.984 66.452 10.080 ; + RECT 0.048 10.752 66.452 10.848 ; + RECT 0.048 11.520 66.452 11.616 ; + RECT 0.048 12.288 66.452 12.384 ; + RECT 0.048 13.056 66.452 13.152 ; + RECT 0.048 13.824 66.452 13.920 ; + RECT 0.048 14.592 66.452 14.688 ; + RECT 0.048 15.360 66.452 15.456 ; + RECT 0.048 16.128 66.452 16.224 ; + RECT 0.048 16.896 66.452 16.992 ; + RECT 0.048 17.664 66.452 17.760 ; + RECT 0.048 18.432 66.452 18.528 ; + RECT 0.048 19.200 66.452 19.296 ; + RECT 0.048 19.968 66.452 20.064 ; + RECT 0.048 20.736 66.452 20.832 ; + RECT 0.048 21.504 66.452 21.600 ; + RECT 0.048 22.272 66.452 22.368 ; + RECT 0.048 23.040 66.452 23.136 ; + RECT 0.048 23.808 66.452 23.904 ; + RECT 0.048 24.576 66.452 24.672 ; + RECT 0.048 25.344 66.452 25.440 ; + RECT 0.048 26.112 66.452 26.208 ; + RECT 0.048 26.880 66.452 26.976 ; + RECT 0.048 27.648 66.452 27.744 ; + RECT 0.048 28.416 66.452 28.512 ; + RECT 0.048 29.184 66.452 29.280 ; + RECT 0.048 29.952 66.452 30.048 ; + RECT 0.048 30.720 66.452 30.816 ; + RECT 0.048 31.488 66.452 31.584 ; + RECT 0.048 32.256 66.452 32.352 ; + RECT 0.048 33.024 66.452 33.120 ; + RECT 0.048 33.792 66.452 33.888 ; + RECT 0.048 34.560 66.452 34.656 ; + RECT 0.048 35.328 66.452 35.424 ; + RECT 0.048 36.096 66.452 36.192 ; + RECT 0.048 36.864 66.452 36.960 ; + RECT 0.048 37.632 66.452 37.728 ; + RECT 0.048 38.400 66.452 38.496 ; + RECT 0.048 39.168 66.452 39.264 ; + RECT 0.048 39.936 66.452 40.032 ; + RECT 0.048 40.704 66.452 40.800 ; + RECT 0.048 41.472 66.452 41.568 ; + END + END VSS + OBS + LAYER M1 ; + RECT 0 0 66.500 42.000 ; + LAYER M2 ; + RECT 0 0 66.500 42.000 ; + LAYER M3 ; + RECT 0 0 66.500 42.000 ; + LAYER M4 ; + RECT 0 0 66.500 42.000 ; + END +END fakeram_512x128 + +END LIBRARY diff --git a/flow/platforms/asap7/lib/NLDM/fakeram_2048x128.lib b/flow/platforms/asap7/lib/NLDM/fakeram_2048x128.lib new file mode 100644 index 0000000000..7a6638e883 --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram_2048x128.lib @@ -0,0 +1,388 @@ +library(fakeram_2048x128) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2026-04-27 19:02:21Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_2048x128_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_2048x128_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_2048x128_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_2048x128_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_2048x128_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_2048x128_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 128; + bit_from : 127; + bit_to : 0 ; + downto : true ; + } + type (fakeram_2048x128_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 11; + bit_from : 10; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_2048x128) { + area : 11007.531; + interface_timing : true; + memory() { + type : ram; + address_width : 11; + word_width : 128; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_2048x128_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_2048x128_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram_2048x128_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_2048x128_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_2048x128_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_2048x128_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_2048x128_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram_2048x128_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram_2048x128_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_2048x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_2048x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/lib/NLDM/fakeram_512x128.lib b/flow/platforms/asap7/lib/NLDM/fakeram_512x128.lib new file mode 100644 index 0000000000..8c6479978b --- /dev/null +++ b/flow/platforms/asap7/lib/NLDM/fakeram_512x128.lib @@ -0,0 +1,388 @@ +library(fakeram_512x128) { + technology (cmos); + delay_model : table_lookup; + revision : 1.0; + date : "2025-11-03 18:13:00Z"; + comment : "SRAM"; + time_unit : "1ns"; + voltage_unit : "1V"; + current_unit : "1uA"; + leakage_power_unit : "1uW"; + nom_process : 1; + nom_temperature : 25.000; + nom_voltage : 0.7; + capacitive_load_unit (1,pf); + + pulling_resistance_unit : "1kohm"; + + operating_conditions(tt_1.0_25.0) { + process : 1; + temperature : 25.000; + voltage : 0.7; + tree_type : balanced_tree; + } + + /* default attributes */ + default_cell_leakage_power : 0; + default_fanout_load : 1; + default_inout_pin_cap : 0.0; + default_input_pin_cap : 0.0; + default_output_pin_cap : 0.0; + default_max_transition : 0.227; + + default_operating_conditions : tt_1.0_25.0; + default_leakage_power_density : 0.0; + + /* additional header data */ + slew_derate_from_library : 1.000; + slew_lower_threshold_pct_fall : 20.000; + slew_upper_threshold_pct_fall : 80.000; + slew_lower_threshold_pct_rise : 20.000; + slew_upper_threshold_pct_rise : 80.000; + input_threshold_pct_fall : 50.000; + input_threshold_pct_rise : 50.000; + output_threshold_pct_fall : 50.000; + output_threshold_pct_rise : 50.000; + + + lu_table_template(fakeram_512x128_mem_out_delay_template) { + variable_1 : input_net_transition; + variable_2 : total_output_net_capacitance; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + lu_table_template(fakeram_512x128_mem_out_slew_template) { + variable_1 : total_output_net_capacitance; + index_1 ("1000, 1001"); + } + lu_table_template(fakeram_512x128_constraint_template) { + variable_1 : related_pin_transition; + variable_2 : constrained_pin_transition; + index_1 ("1000, 1001"); + index_2 ("1000, 1001"); + } + power_lut_template(fakeram_512x128_energy_template_clkslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + power_lut_template(fakeram_512x128_energy_template_sigslew) { + variable_1 : input_transition_time; + index_1 ("1000, 1001"); + } + library_features(report_delay_calculation); + type (fakeram_512x128_DATA) { + base_type : array ; + data_type : bit ; + bit_width : 128; + bit_from : 127; + bit_to : 0 ; + downto : true ; + } + type (fakeram_512x128_ADDRESS) { + base_type : array ; + data_type : bit ; + bit_width : 9; + bit_from : 8; + bit_to : 0 ; + downto : true ; + } +cell(fakeram_512x128) { + area : 2751.883; + interface_timing : true; + memory() { + type : ram; + address_width : 9; + word_width : 128; + } + pin(clk) { + direction : input; + capacitance : 0.025; + clock : true; + min_period : 0.157 ; + internal_power(){ + rise_power(fakeram_512x128_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + fall_power(fakeram_512x128_energy_template_clkslew) { + index_1 ("0.009, 0.227"); + values ("1.345, 1.345") + } + } + } + + bus(rd_out) { + bus_type : fakeram_512x128_DATA; + direction : output; + max_capacitance : 0.500; + memory_read() { + address : addr_in; + } + timing() { + related_pin : "clk" ; + timing_type : rising_edge; + timing_sense : non_unate; + cell_rise(fakeram_512x128_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + cell_fall(fakeram_512x128_mem_out_delay_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.005, 0.500"); + values ( \ + "0.218, 0.218", \ + "0.218, 0.218" \ + ) + } + rise_transition(fakeram_512x128_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + fall_transition(fakeram_512x128_mem_out_slew_template) { + index_1 ("0.005, 0.500"); + values ("0.009, 0.227") + } + } + } + pin(we_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + pin(ce_in){ + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(addr_in) { + bus_type : fakeram_512x128_ADDRESS; + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + rise_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + bus(wd_in) { + bus_type : fakeram_512x128_DATA; + memory_write() { + address : addr_in; + clocked_on : "clk"; + } + direction : input; + capacitance : 0.005; + timing() { + related_pin : clk; + timing_type : setup_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + timing() { + related_pin : clk; + timing_type : hold_rising ; + rise_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + fall_constraint(fakeram_512x128_constraint_template) { + index_1 ("0.009, 0.227"); + index_2 ("0.009, 0.227"); + values ( \ + "0.050, 0.050", \ + "0.050, 0.050" \ + ) + } + } + internal_power(){ + when : "(! (we_in) )"; + rise_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + internal_power(){ + when : "(we_in)"; + rise_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + fall_power(fakeram_512x128_energy_template_sigslew) { + index_1 ("0.009, 0.227"); + values ("0.013, 0.013") + } + } + } + cell_leakage_power : 128.900; +} + +} diff --git a/flow/platforms/asap7/verilog/fakeram_2048x128.sv b/flow/platforms/asap7/verilog/fakeram_2048x128.sv new file mode 100644 index 0000000000..328eb0a8ec --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram_2048x128.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram_2048x128 ( + output reg [127:0] rd_out, + input [10:0] addr_in, + input we_in, + input [127:0] wd_in, + input clk, + input ce_in +); +endmodule diff --git a/flow/platforms/asap7/verilog/fakeram_512x128.sv b/flow/platforms/asap7/verilog/fakeram_512x128.sv new file mode 100644 index 0000000000..56cc3e745f --- /dev/null +++ b/flow/platforms/asap7/verilog/fakeram_512x128.sv @@ -0,0 +1,10 @@ +(* blackbox *) +module fakeram_512x128 ( + output reg [127:0] rd_out, + input [8:0] addr_in, + input we_in, + input [127:0] wd_in, + input clk, + input ce_in +); +endmodule