diff --git a/core/src/cpus/cortex_m.zig b/core/src/cpus/cortex_m.zig index 2b0a49a9f..c344c520e 100644 --- a/core/src/cpus/cortex_m.zig +++ b/core/src/cpus/cortex_m.zig @@ -51,73 +51,7 @@ pub const CPU_Options = struct { enable_fpu: bool = builtin.abi.float() == .hard, }; -/// External Interrupts -/// These are the interrupts generated by the NVIC. -pub const ExternalInterrupt = blk: { - // Note: The value of each field is the interrupt number (VTOR offset), - // not the offset into the whole vector table. - - const vector_info = @typeInfo(Interrupt).@"enum"; - var result_len: usize = 0; - - for (vector_info.field_values) |field_value| { - if (field_value >= 0) result_len += 1; - } - - if (result_len == 0) break :blk enum {}; - - var field_names: [result_len][]const u8 = undefined; - var field_values: [result_len]u8 = undefined; - var i: usize = 0; - for (microzig.chip.interrupts) |intr| { - if (intr.index >= 0) { - field_names[i] = intr.name; - field_values[i] = intr.index; - i += 1; - } - } - - break :blk @Enum(u8, .exhaustive, &field_names, &field_values); -}; - -/// Machine exceptions. -pub const Exception = blk: { - // Note: The value of each field is the index into the whole - // vector table, not the negative offset from VTOR. - - const vector_info = @typeInfo(Interrupt).@"enum"; - var result_len: usize = 0; - - for (vector_info.field_values) |field_value| { - if (field_value < 0) - result_len += 1; - } - - var field_names: [result_len][]const u8 = undefined; - var field_values: [result_len]u4 = undefined; - var i: usize = 0; - for (microzig.chip.interrupts) |intr| { - if (intr.index < 0) { - field_names[i] = intr.name; - field_values[i] = 16 + intr.index; // Cortex-M exceptions are mapped to vector table slots 0 - 15 - i += 1; - } - } - - break :blk @Enum(u4, .exhaustive, &field_names, &field_values); -}; - pub const interrupt = struct { - /// The priority of an interrupt. - /// Cortex-M uses a reversed priority scheme so the lowest priority is 15 and the highest is 0. - /// - /// Note: Some platforms may only use the most significant bits of the priority register. - pub const Priority = enum(u8) { - lowest = 15, - highest = 0, - _, - }; - pub fn globally_enabled() bool { var mrs: u32 = undefined; asm volatile ("mrs %[mrs], 16" @@ -140,237 +74,11 @@ pub const interrupt = struct { } } - pub const exception = struct { - const ppb = switch (cortex_m) { - .cortex_m7 => microzig.chip.peripherals.SCB, - else => microzig.cpu.peripherals.ppb, - }; - - pub fn is_enabled(comptime excpt: Exception) bool { - switch (cortex_m) { - .cortex_m3, .cortex_m4, .cortex_m7 => { - const raw = ppb.SHCSR.raw; - switch (excpt) { - .UsageFault => return (raw & 0x0004_0000) != 0, - .BusFault => return (raw & 0x0002_0000) != 0, - .MemManageFault => return (raw & 0x0001_0000) != 0, - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - const raw = ppb.SHCSR.raw; - switch (excpt) { - .SecureFault => return (raw & 0x0008_0000) != 0, - .UsageFault => return (raw & 0x0004_0000) != 0, - .BusFault => return (raw & 0x0002_0000) != 0, - .MemManageFault => return (raw & 0x0001_0000) != 0, - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - pub fn enable(comptime excpt: Exception) void { - switch (cortex_m) { - .cortex_m3, .cortex_m4, .cortex_m7 => { - switch (excpt) { - .UsageFault => ppb.SHCSR.raw |= 0x0004_0000, - .BusFault => ppb.SHCSR.raw |= 0x0002_0000, - .MemManageFault => ppb.SHCSR.raw |= 0x0001_0000, - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - switch (excpt) { - .SecureFault => ppb.SHCSR.raw |= 0x0008_0000, - .UsageFault => ppb.SHCSR.raw |= 0x0004_0000, - .BusFault => ppb.SHCSR.raw |= 0x0002_0000, - .MemManageFault => ppb.SHCSR.raw |= 0x0001_0000, - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - pub fn disable(comptime excpt: Exception) void { - switch (cortex_m) { - .cortex_m3, .cortex_m4, .cortex_m7 => { - switch (excpt) { - .UsageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0004_0000), - .BusFault => ppb.SHCSR.raw &= ~@as(u32, 0x0002_0000), - .MemManageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0001_0000), - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - switch (excpt) { - .SecureFault => ppb.SHCSR.raw &= ~@as(u32, 0x0008_0000), - .UsageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0004_0000), - .BusFault => ppb.SHCSR.raw &= ~@as(u32, 0x0002_0000), - .MemManageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0001_0000), - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - pub fn is_pending(comptime excpt: Exception) bool { - switch (cortex_m) { - .cortex_m0plus, - => { - if (excpt == .SVCALL) return (ppb.SHCSR.raw & 0x0000_8000) != 0; - @compileError("not supported on this platform"); - }, - .cortex_m3, .cortex_m4, .cortex_m7 => { - const raw = ppb.SHCSR.raw; - switch (excpt) { - .SVCall => return (raw & 0x0000_8000) != 0, - .BusFault => return (raw & 0x0000_4000) != 0, - .MemManageFault => return (raw & 0x0000_2000) != 0, - .UsageFault => return (raw & 0x0000_1000) != 0, - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - const raw = ppb.SHCSR.raw; - switch (excpt) { - .HardFault => return (raw & 0x0020_0000) != 0, - .SecureFault => return (raw & 0x0010_0000) != 0, - .SVCall => return (raw & 0x0000_8000) != 0, - .BusFault => return (raw & 0x0000_4000) != 0, - .MemManageFault => return (raw & 0x0000_2000) != 0, - .UsageFault => return (raw & 0x0000_1000) != 0, - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - pub fn set_pending(comptime excpt: Exception) void { - switch (cortex_m) { - .cortex_m0plus, - => { - if (excpt == .SVCALL) ppb.SHCSR.raw |= 0x0000_8000; - @compileError("not supported on this platform"); - }, - .cortex_m3, .cortex_m4, .cortex_m7 => { - switch (excpt) { - .SVCall => ppb.SHCSR.raw |= 0x0000_8000, - .BusFault => ppb.SHCSR.raw |= 0x0000_4000, - .MemManageFault => ppb.SHCSR.raw |= 0x0000_2000, - .UsageFault => ppb.SHCSR.raw |= 0x0000_1000, - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - switch (excpt) { - .HardFault => ppb.SHCSR.raw |= 0x0020_0000, - .SecureFault => ppb.SHCSR.raw |= 0x0010_0000, - .SVCall => ppb.SHCSR.raw |= 0x0000_8000, - .BusFault => ppb.SHCSR.raw |= 0x0000_4000, - .MemManageFault => ppb.SHCSR.raw |= 0x0000_2000, - .UsageFault => ppb.SHCSR.raw |= 0x0000_1000, - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - pub fn clear_pending(comptime excpt: Exception) void { - switch (cortex_m) { - .cortex_m0plus, - => { - if (excpt == .SVCALL) ppb.SHCSR.raw &= ~@as(u32, 0x0000_8000); - @compileError("not supported on this platform"); - }, - .cortex_m3, .cortex_m4, .cortex_m7 => { - switch (excpt) { - .SVCall => ppb.SHCSR.raw &= ~@as(u32, 0x0000_8000), - .BusFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_4000), - .MemManageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_2000), - .UsageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_1000), - else => @compileError("not supported on this platform"), - } - }, - .cortex_m33, - .cortex_m55, - => { - switch (excpt) { - .HardFault => ppb.SHCSR.raw &= ~@as(u32, 0x0020_0000), - .SecureFault => ppb.SHCSR.raw &= ~@as(u32, 0x0010_0000), - .SVCall => ppb.SHCSR.raw &= ~@as(u32, 0x0000_8000), - .BusFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_4000), - .MemManageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_2000), - .UsageFault => ppb.SHCSR.raw &= ~@as(u32, 0x0000_1000), - else => @compileError("not supported on this platform"), - } - }, - else => @compileError("not supported on this platform"), - } - } - - /// Note: Although the Priority values are 0 - 15, some platforms may - /// only use the most significant bits. - pub fn set_priority(comptime excpt: Exception, priority: Priority) void { - const num: u2 = @intCast(@backingInt(excpt) / 4); - const shift: u5 = @as(u5, @intCast(@backingInt(excpt))) % 4 * 8; - - // The code below is safe since the switch is compile-time resolved. - // The any SHPRn register which is unavailable on a platform will - // not be accessed as no matching `Exception` will be exist. - - switch (num) { - 0 => { - @compileError("Cannot set the priority for the exception"); - }, - 1 => { - ppb.SHPR1.raw &= ~(@as(u32, 0xFF) << shift); - ppb.SHPR1.raw |= @as(u32, @backingInt(priority)) << shift; - }, - 2 => { - ppb.SHPR2.raw &= ~(@as(u32, 0xFF) << shift); - ppb.SHPR2.raw |= @as(u32, @backingInt(priority)) << shift; - }, - 3 => { - ppb.SHPR3.raw &= ~(@as(u32, 0xFF) << shift); - ppb.SHPR3.raw |= @as(u32, @backingInt(priority)) << shift; - }, - } - } - - pub fn get_priority(comptime excpt: Exception) Priority { - const num: u2 = @intCast(@backingInt(excpt) / 4); - const shift: u5 = @as(u5, @intCast(@backingInt(excpt))) % 4 * 8; - - const raw: u8 = (switch (num) { - 0 => @compileError("Cannot get the priority for the exception"), - 1 => ppb.SHPR1.raw, - 2 => ppb.SHPR2.raw, - 3 => ppb.SHPR3.raw, - } >> shift) & 0xFF; - - return @fromBackingInt(raw); - } - }; - const nvic = peripherals.nvic; - pub fn is_enabled(comptime int: ExternalInterrupt) bool { + pub fn is_enabled(comptime int: Interrupt) bool { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, @@ -391,13 +99,15 @@ pub const interrupt = struct { } } - pub fn enable(comptime int: ExternalInterrupt) void { + pub fn enable(comptime int: Interrupt) void { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, .cortex_m0plus, => { - nvic.ISER |= 1 << num; + nvic.ISER = 1 << num; }, .cortex_m3, .cortex_m33, @@ -407,18 +117,20 @@ pub const interrupt = struct { => { const bank = num / 32; const index = num % 32; - nvic.ISER[bank] |= 1 << index; + nvic.ISER[bank] = 1 << index; }, } } - pub fn disable(comptime int: ExternalInterrupt) void { + pub fn disable(comptime int: Interrupt) void { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, .cortex_m0plus, => { - nvic.ICER |= 1 << num; + nvic.ICER = 1 << num; }, .cortex_m3, .cortex_m33, @@ -428,12 +140,14 @@ pub const interrupt = struct { => { const bank = num / 32; const index = num % 32; - nvic.ICER[bank] |= 1 << index; + nvic.ICER[bank] = 1 << index; }, } } - pub fn is_pending(comptime int: ExternalInterrupt) bool { + pub fn is_pending(comptime int: Interrupt) bool { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, @@ -454,13 +168,15 @@ pub const interrupt = struct { } } - pub fn set_pending(comptime int: ExternalInterrupt) void { + pub fn set_pending(comptime int: Interrupt) void { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, .cortex_m0plus, => { - nvic.ISPR |= 1 << num; + nvic.ISPR = 1 << num; }, .cortex_m3, .cortex_m33, @@ -470,18 +186,20 @@ pub const interrupt = struct { => { const bank = num / 32; const index = num % 32; - nvic.ISPR[bank] |= 1 << index; + nvic.ISPR[bank] = 1 << index; }, } } - pub fn clear_pending(comptime int: ExternalInterrupt) void { + pub fn clear_pending(comptime int: Interrupt) void { + assert_not_exception(int); + const num: comptime_int = @backingInt(int); switch (cortex_m) { .cortex_m0, .cortex_m0plus, => { - nvic.ICPR |= 1 << num; + nvic.ICPR = 1 << num; }, .cortex_m3, .cortex_m33, @@ -491,17 +209,31 @@ pub const interrupt = struct { => { const bank = num / 32; const index = num % 32; - nvic.ICPR[bank] |= 1 << index; + nvic.ICPR[bank] = 1 << index; }, } } - pub fn set_priority(comptime int: ExternalInterrupt, priority: Priority) void { - nvic.IPR[@backingInt(int)] = @backingInt(priority); + const priority_bits = microzig.chip.properties.interrupt_priority_bits orelse 2; + const priority_shift = 8 - priority_bits; + const PriorityBackingInt = @Int(.unsigned, priority_bits); + + /// The priority of an interrupt. Lower means higher priority (zero is the + /// highest priority). + pub const Priority = enum(PriorityBackingInt) { + highest = 0, + lowest = std.math.maxInt(PriorityBackingInt), + _, + }; + + pub fn set_priority(comptime int: Interrupt, priority: Priority) void { + assert_not_exception(int); + nvic.IPR[@backingInt(int)] = @as(u8, @backingInt(priority)) << priority_shift; } - pub fn get_priority(comptime int: ExternalInterrupt) Priority { - return @fromBackingInt(peripherals.nvic.IPR[@backingInt(int)]); + pub fn get_priority(comptime int: Interrupt) Priority { + assert_not_exception(int); + return @fromBackingInt(@truncate(peripherals.nvic.IPR[@backingInt(int)] >> priority_shift)); } }; @@ -1009,7 +741,8 @@ const scs_base = 0xE000E000; const itm_base = 0xE0000000; const tpi_base = 0xE0040000; -const coredebug_base = 0xE000EDF0; +const dwt_base = 0xE0001000; +const dcb_base = 0xE000EDF0; const systick_base = scs_base + 0x0010; const nvic_base = scs_base + 0x0100; const scb_base = scs_base + core.scb_base_offset; @@ -1099,10 +832,15 @@ pub const peripherals = struct { \\ ++ mpu_error_helper_message); - pub const dbg: (if (@hasDecl(core, "DebugRegisters")) - *volatile core.DebugRegisters + pub const dcb: (if (@hasDecl(core, "DebugControlBlock")) + *volatile core.DebugControlBlock + else + *volatile anyopaque) = @ptrFromInt(dcb_base); + + pub const dwt: (if (@hasDecl(core, "DataWatchpointAndTrace")) + *volatile core.DataWatchpointAndTrace else - *volatile anyopaque) = @ptrFromInt(coredebug_base); + *volatile anyopaque) = @ptrFromInt(dwt_base); pub const itm: (if (@hasDecl(core, "ITM")) *volatile core.ITM diff --git a/core/src/cpus/cortex_m/m33.zig b/core/src/cpus/cortex_m/m33.zig index 3e93d5f96..453524fa6 100644 --- a/core/src/cpus/cortex_m/m33.zig +++ b/core/src/cpus/cortex_m/m33.zig @@ -453,3 +453,232 @@ pub const MemoryProtectionUnit = extern struct { LIMIT: u27, }); }; + +pub const DebugControlBlock = extern struct { + /// Debug Halting Control and Status Register + /// + /// Careful when using .modify() on this register, you should always write + /// the DBGKEY to the upper half of the register, otherwise the write will + /// be ignored. + DHCSR: mmio.Mmio(packed struct(u32) { + /// Debug enable. + C_DEBUGEN: u1, + /// Core halt. When set to 1, halts the core. + C_HALT: u1, + /// Core step. When set to 1, steps the core. + C_STEP: u1, + /// Mask interrupts when halting or stepping. + C_MASKINTS: u1, + reserved0: u1 = 0, + /// Snap stall control. + C_SNAPSTALL: u1, + /// Halt on PMU overflow control. + C_PMOV: u1, + reserved1: u9 = 0, + + /// Upper 16 bits: write DBGKEY or read status flags + upper: packed union(u16) { + /// Debug Key. Must be written as 0xA05F to enable writes to this register. + DBGKEY: u16, + /// Status flags (Read-Only). + status: packed struct(u16) { + /// Register ready status. + S_REGRDY: u1, + /// Core halt status. + S_HALT: u1, + /// Core sleep status. + S_SLEEP: u1, + /// Core lockup status. + S_LOCKUP: u1, + /// Secure Debug Enabled status. + S_SDE: u1, + /// Non-secure Unprivileged Halting Debug Enabled status. + S_NSUIDE: u1, + /// Secure Unprivileged Halting Debug Enabled status. + S_SUIDE: u1, + /// Floating-point registers Debuggable status. + S_FPD: u1, + /// Retire sticky status. + S_RETIRE_ST: u1, + /// Reset sticky status. + S_RESET_ST: u1, + /// Restart sticky status. + S_RESTART_ST: u1, + reserved2: u5 = 0, + }, + }, + }), + /// Debug Core Register Selector Register + DCRSR: mmio.Mmio(packed struct(u32) { + /// Register selector. + REGSEL: u8, + reserved0: u8 = 0, + /// Write / not Read access to the selected core register. + /// 0 = Read + /// 1 = Write + REGWnR: u1, + reserved1: u15 = 0, + }), + /// Debug Core Register Data Register + DCRDR: u32, + /// Debug Exception and Monitor Control Register + DEMCR: mmio.Mmio(packed struct(u32) { + /// Vector catch on core reset. + VC_CORERESET: u1, + reserved0: u3 = 0, + /// Vector catch on Memory Management Fault. + VC_MMERR: u1, + /// Vector catch on Coprocessor Access Fault. + VC_NOCPERR: u1, + /// Vector catch on Check Fault. + VC_CHKERR: u1, + /// Vector catch on State Fault. + VC_STATERR: u1, + /// Vector catch on Bus Fault. + VC_BUSERR: u1, + /// Vector catch on Interrupt/Exception Fault. + VC_INTERR: u1, + /// Vector catch on Hard Fault. + VC_HARDERR: u1, + /// Vector catch on Secure Fault. + VC_SFERR: u1, + reserved1: u4 = 0, + /// Debug Monitor Enable. + MON_EN: u1, + /// Debug Monitor pending state. + MON_PEND: u1, + /// Debug Monitor step enable. + MON_STEP: u1, + /// Debug Monitor request. + MON_REQ: u1, + /// Secure Debug Monitor Enable. + SDME: u1, + /// Unprivileged Debug Monitor Enable. + UMON_EN: u1, + reserved2: u1 = 0, + /// Monitor pend request key. + MONPRKEY: u1, + /// Trace enable. Enables DWT and ITM features. + TRCENA: u1, + reserved3: u7 = 0, + }), + /// Debug Set Clear Exception and Monitor Control Register + DSCMECR: mmio.Mmio(packed struct(u32) { + reserved0: u1 = 0, + /// Set monitor pend. + SET_MON_PEND: u1, + reserved1: u1 = 0, + /// Set monitor request. + SET_MON_REQ: u1, + reserved2: u13 = 0, + /// Clear monitor pend. + CLR_MON_PEND: u1, + reserved3: u1 = 0, + /// Clear monitor request. + CLR_MON_REQ: u1, + reserved4: u12 = 0, + }), + /// Debug Authentication Control Register + DAUTHCTRL: u32, + /// Debug Security Control and Status Register + DSCSR: mmio.Mmio(packed struct(u32) { + /// Secure banked register select enable. + SBRSELEN: u1, + /// Secure banked register select. + SBRSEL: u1, + reserved0: u14 = 0, + /// Current domain Secure. + CDS: u1, + /// CDS write-enable key. + CDSKEY: u1, + reserved1: u14 = 0, + }), +}; + +pub const DataWatchpointAndTrace = extern struct { + /// Control Register + CTRL: mmio.Mmio(packed struct(u32) { + /// Enables the Cycle Count Register (CYCCNT). + CYCCNTENA: u1, + /// Reload value for the Post-preset counter. + POSTPRESET: u4, + /// Reload value for the Post-init counter. + POSTINIT: u4, + /// Selects the tap on the CYCCNT for POSTCNT. + CYCTAP: u1, + /// Synchronization tap select. + SYNCTAP: u2, + /// Enables PC sampling. + PCSAMPLENA: u1, + reserved0: u3 = 0, + /// Enables Exception trace. + EXCTRCENA: u1, + /// Enables CPI event trace. + CPIEVTENA: u1, + /// Enables Exception event trace. + EXCEVTENA: u1, + /// Enables Sleep event trace. + SLEEPEVTENA: u1, + /// Enables LSU event trace. + LSUEVTENA: u1, + /// Enables Folded instruction event trace. + FOLDEVTENA: u1, + /// Enables Cycle count event trace. + CYCEVTENA: u1, + /// Cycle counter disable secure. + CYCDISS: u1 = 0, + /// Profiling counter not supported. + NOPRFCNT: u1, + /// Cycle counter not supported. + NOCYCCNT: u1, + /// External triggers not supported. + NOEXTTRIG: u1, + /// Trace packet generation not supported. + NOTRCPKT: u1, + /// Number of comparators implemented. + NUMCOMP: u4, + }), + /// Cycle Count Register + CYCCNT: u32, + /// CPI Count Register + CPICNT: u32, + /// Exception Overhead Count Register + EXCCNT: u32, + /// Sleep Count Register + SLEEPCNT: u32, + /// LSU Count Register + LSUCNT: u32, + /// Folded Instruction Count Register + FOLDCNT: u32, + /// Program Counter Sample Register + PCSR: u32, + + /// DWT Comparators + COMPARATORS: [15]Comparator, + + pub const Comparator = extern struct { + /// Comparator Value Register + COMP: u32, + reserved: u32 = 0, + /// Comparator Function Register + FUNCTION: mmio.Mmio(packed struct(u32) { + /// Comparator function (e.g., PC value, data address, data value). + FUNCTION: u4, + reserved0: u1 = 0, + /// Emit range tracing. + EMITRANGE: u1, + reserved1: u2 = 0, + /// Data value size. + DATAVSIZE: u2, + /// Linked comparator number. + LNK1ENA: u1, + /// Linked comparator number. + DATAVADDR0: u4, + reserved2: u9 = 0, + /// Comparator matched status. + MATCHED: u1, + reserved3: u7 = 0, + }), + VMASK: u32, + }; +}; diff --git a/core/src/cpus/cortex_m/m7.zig b/core/src/cpus/cortex_m/m7.zig index 9127054ed..561855c92 100644 --- a/core/src/cpus/cortex_m/m7.zig +++ b/core/src/cpus/cortex_m/m7.zig @@ -237,7 +237,7 @@ pub const MemoryProtectionUnit = extern struct { }); }; -pub const DebugRegisters = extern struct { +pub const DebugControlBlock = extern struct { /// Debyg Halting Control and Status Register DHCSR: mmio.Mmio(packed struct { reserved0: u6 = 0, diff --git a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig index c10266dc1..ceaa09009 100644 --- a/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig +++ b/port/raspberrypi/rp2xxx/src/cpus/hazard3.zig @@ -27,7 +27,7 @@ pub const CoreInterrupt = enum(u5) { // supports a maximum of 128 interrupts (actually supports 512 but for some reason priorities // only support 128) -pub const ExternalInterrupt = microzig.utilities.GenerateInterruptEnum(u7); +pub const Interrupt = microzig.utilities.GenerateInterruptEnum(u7); // NOTE: there is no way to use a custom incoming_stack_alignment with this way of doing things const riscv_calling_convention: std.builtin.CallingConvention = .{ .riscv32_interrupt = .{ .mode = .machine } }; @@ -42,7 +42,7 @@ pub const Handler = microzig.interrupt.Handler; pub const InterruptOptions = microzig.utilities.GenerateInterruptOptions(&.{ .{ .InterruptEnum = enum { Exception }, .HandlerFn = InterruptHandler }, .{ .InterruptEnum = CoreInterrupt, .HandlerFn = InterruptHandler }, - .{ .InterruptEnum = ExternalInterrupt, .HandlerFn = Handler }, + .{ .InterruptEnum = Interrupt, .HandlerFn = Handler }, }); pub const interrupt = struct { @@ -53,14 +53,14 @@ pub const interrupt = struct { // use a custom `CoreInterrupt` enum specifically for hazard3 pub const core = riscv32_common.utilities.interrupt.CoreImpl(CoreInterrupt); - pub fn is_enabled(int: ExternalInterrupt) bool { + pub fn is_enabled(int: Interrupt) bool { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); return csr.meiea.read_set(.{ .index = index }).window & mask != 0; } - pub fn enable(int: ExternalInterrupt) void { + pub fn enable(int: Interrupt) void { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); @@ -70,7 +70,7 @@ pub const interrupt = struct { }); } - pub fn disable(int: ExternalInterrupt) void { + pub fn disable(int: Interrupt) void { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); @@ -80,21 +80,21 @@ pub const interrupt = struct { }); } - pub fn is_pending(int: ExternalInterrupt) bool { + pub fn is_pending(int: Interrupt) bool { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); return csr.meipa.read_set(.{ .index = index }).window & mask != 0; } - pub fn set_pending(int: ExternalInterrupt) void { + pub fn set_pending(int: Interrupt) void { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); csr.meifa.set(.{ .index = index, .window = mask }); } - pub fn clear_pending(int: ExternalInterrupt) void { + pub fn clear_pending(int: Interrupt) void { const num: u7 = @backingInt(int); const index: u3 = @intCast(num >> 4); const mask: u16 = @as(u16, 1) << @as(u4, @intCast(num & 0xf)); @@ -107,7 +107,7 @@ pub const interrupt = struct { _, }; - pub fn set_priority(int: ExternalInterrupt, priority: Priority) void { + pub fn set_priority(int: Interrupt, priority: Priority) void { const num: u7 = @backingInt(int); const index: u5 = @intCast(num >> 2); const shift: u4 = @intCast(4 * (num & 0x4)); @@ -117,7 +117,7 @@ pub const interrupt = struct { csr.meipra.set(.{ .index = index, .window = set_mask }); } - pub fn get_priority(int: ExternalInterrupt) Priority { + pub fn get_priority(int: Interrupt) Priority { const num: u7 = @backingInt(int); const index: u5 = @intCast(num >> 2); const shift: u4 = @intCast(4 * (num & 0x4)); @@ -231,7 +231,7 @@ pub const startup_logic = struct { const vector_count = @sizeOf(microzig.chip.VectorTable) / @sizeOf(usize); var temp: [vector_count]Handler = @splat(microzig.interrupt.unhandled); - const info = @typeInfo(ExternalInterrupt).@"enum"; + const info = @typeInfo(Interrupt).@"enum"; for (info.field_names, info.field_values) |field_name, field_value| { if (@field(microzig.options.interrupts, field_name)) |handler| { temp[field_value] = handler; diff --git a/port/stmicro/stm32/src/hals/STM32F103/time.zig b/port/stmicro/stm32/src/hals/STM32F103/time.zig index 4de5f270c..b8c84926b 100644 --- a/port/stmicro/stm32/src/hals/STM32F103/time.zig +++ b/port/stmicro/stm32/src/hals/STM32F103/time.zig @@ -78,7 +78,7 @@ pub fn init_timer(comptime tim: timer.Instances) void { gptim.clear_interrupts(); microzig.interrupt.enable_interrupts(); - microzig.interrupt.enable(@field(microzig.cpu.ExternalInterrupt, @tagName(tim))); + microzig.interrupt.enable(@field(microzig.cpu.Interrupt, @tagName(tim))); gptim.start(); tim_ctx = gptim; diff --git a/port/stmicro/stm32/src/hals/common/bdma_v1.zig b/port/stmicro/stm32/src/hals/common/bdma_v1.zig index 9a379a678..01b00c073 100644 --- a/port/stmicro/stm32/src/hals/common/bdma_v1.zig +++ b/port/stmicro/stm32/src/hals/common/bdma_v1.zig @@ -77,7 +77,7 @@ pub fn DMA(comptime dma_ctrl: Instances, comptime ch: ChannelNumber) type { const vector_table: *microzig.cpu.VectorTable = @ptrFromInt(0x0); std.debug.assert(@field(vector_table, interrupt_name).* == @intFromPtr(&DMA_Handler)); } - microzig.interrupt.enable(@as(microzig.cpu.ExternalInterrupt, @fromBackingInt(interrupt_index))); + microzig.interrupt.enable(@as(microzig.cpu.Interrupt, @fromBackingInt(interrupt_index))); } pub fn get_channel() *Channel { diff --git a/port/stmicro/stm32/src/hals/common/bdma_v2.zig b/port/stmicro/stm32/src/hals/common/bdma_v2.zig index 456591a6c..0dcd31277 100644 --- a/port/stmicro/stm32/src/hals/common/bdma_v2.zig +++ b/port/stmicro/stm32/src/hals/common/bdma_v2.zig @@ -78,7 +78,7 @@ pub fn DMA(comptime dma_ctrl: Instances, comptime ch: ChannelNumber) type { const vector_table: *microzig.cpu.VectorTable = @ptrFromInt(0x0); std.debug.assert(@field(vector_table, interrupt_name).* == @intFromPtr(&DMA_Handler)); } - microzig.interrupt.enable(@as(microzig.cpu.ExternalInterrupt, @fromBackingInt(interrupt_index))); + microzig.interrupt.enable(@as(microzig.cpu.Interrupt, @fromBackingInt(interrupt_index))); } pub fn get_channel() *Channel {