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fpistmfpistm
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system(wba): update STM32WBAxx CMSIS Drivers to v1.10.0
Included in STM32CubeWBA FW v1.10.0 Signed-off-by: Frederic Pillon <frederic.pillon@st.com>
1 parent 0a31f19 commit 64c9fa5

19 files changed

Lines changed: 1623 additions & 488 deletions

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba20xx.h‎

Lines changed: 127 additions & 21 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba23xx.h‎

Lines changed: 127 additions & 21 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba25xx.h‎

Lines changed: 127 additions & 21 deletions
Large diffs are not rendered by default.

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba50xx.h‎

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -6637,41 +6637,41 @@ typedef struct
66376637
/******************** Bits definition for RNG_CR register *******************/
66386638
#define RNG_CR_RNGEN_Pos (2UL)
66396639
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
6640-
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
6640+
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */
66416641
#define RNG_CR_IE_Pos (3UL)
66426642
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
6643-
#define RNG_CR_IE RNG_CR_IE_Msk
6643+
#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */
66446644
#define RNG_CR_CED_Pos (5UL)
66456645
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
6646-
#define RNG_CR_CED RNG_CR_CED_Msk
6646+
#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */
66476647
#define RNG_CR_ARDIS_Pos (7UL)
6648-
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
6649-
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
6648+
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */
6649+
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */
66506650
#define RNG_CR_RNG_CONFIG3_Pos (8UL)
6651-
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
6652-
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
6651+
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
6652+
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */
66536653
#define RNG_CR_NISTC_Pos (12UL)
6654-
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
6655-
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
6654+
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
6655+
#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */
66566656
#define RNG_CR_RNG_CONFIG2_Pos (13UL)
6657-
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
6658-
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
6657+
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
6658+
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */
66596659
#define RNG_CR_CLKDIV_Pos (16UL)
6660-
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
6661-
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
6660+
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
6661+
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */
66626662
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
66636663
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
66646664
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
66656665
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
66666666
#define RNG_CR_RNG_CONFIG1_Pos (20UL)
6667-
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
6668-
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
6667+
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
6668+
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */
66696669
#define RNG_CR_CONDRST_Pos (30UL)
6670-
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
6671-
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
6670+
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
6671+
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */
66726672
#define RNG_CR_CONFIGLOCK_Pos (31UL)
6673-
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
6674-
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
6673+
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
6674+
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */
66756675

66766676
/******************** Bits definition for RNG_SR register *******************/
66776677
#define RNG_SR_DRDY_Pos (0UL)
@@ -6720,11 +6720,12 @@ typedef struct
67206720
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
67216721
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
67226722

6723+
6724+
67236725
/******************** RNG Nist Compliance Values *******************/
67246726
#define RNG_CR_NIST_VALUE (0x00F02D00U)
67256727
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
67266728
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
6727-
67286729
/******************************************************************************/
67296730
/* */
67306731
/* Real-Time Clock (RTC) */

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba52xx.h‎

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -10539,41 +10539,41 @@ typedef struct
1053910539
/******************** Bits definition for RNG_CR register *******************/
1054010540
#define RNG_CR_RNGEN_Pos (2UL)
1054110541
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10542-
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10542+
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */
1054310543
#define RNG_CR_IE_Pos (3UL)
1054410544
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
10545-
#define RNG_CR_IE RNG_CR_IE_Msk
10545+
#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */
1054610546
#define RNG_CR_CED_Pos (5UL)
1054710547
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
10548-
#define RNG_CR_CED RNG_CR_CED_Msk
10548+
#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */
1054910549
#define RNG_CR_ARDIS_Pos (7UL)
10550-
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
10551-
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
10550+
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */
10551+
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */
1055210552
#define RNG_CR_RNG_CONFIG3_Pos (8UL)
10553-
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
10554-
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
10553+
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
10554+
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */
1055510555
#define RNG_CR_NISTC_Pos (12UL)
10556-
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
10557-
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
10556+
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
10557+
#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */
1055810558
#define RNG_CR_RNG_CONFIG2_Pos (13UL)
10559-
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
10560-
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
10559+
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
10560+
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */
1056110561
#define RNG_CR_CLKDIV_Pos (16UL)
10562-
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
10563-
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
10562+
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
10563+
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */
1056410564
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
1056510565
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
1056610566
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
1056710567
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1056810568
#define RNG_CR_RNG_CONFIG1_Pos (20UL)
10569-
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
10570-
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
10569+
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
10570+
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */
1057110571
#define RNG_CR_CONDRST_Pos (30UL)
10572-
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
10573-
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
10572+
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
10573+
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */
1057410574
#define RNG_CR_CONFIGLOCK_Pos (31UL)
10575-
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
10576-
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
10575+
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
10576+
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */
1057710577

1057810578
/******************** Bits definition for RNG_SR register *******************/
1057910579
#define RNG_SR_DRDY_Pos (0UL)
@@ -10622,11 +10622,12 @@ typedef struct
1062210622
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1062310623
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
1062410624

10625+
10626+
1062510627
/******************** RNG Nist Compliance Values *******************/
1062610628
#define RNG_CR_NIST_VALUE (0x00F02D00U)
1062710629
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
1062810630
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
10629-
1063010631
/******************************************************************************/
1063110632
/* */
1063210633
/* Real-Time Clock (RTC) */

‎system/Drivers/CMSIS/Device/ST/STM32WBAxx/Include/stm32wba54xx.h‎

Lines changed: 21 additions & 20 deletions
Original file line numberDiff line numberDiff line change
@@ -10902,41 +10902,41 @@ typedef struct
1090210902
/******************** Bits definition for RNG_CR register *******************/
1090310903
#define RNG_CR_RNGEN_Pos (2UL)
1090410904
#define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
10905-
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
10905+
#define RNG_CR_RNGEN RNG_CR_RNGEN_Msk /*!< True random number generator enable */
1090610906
#define RNG_CR_IE_Pos (3UL)
1090710907
#define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
10908-
#define RNG_CR_IE RNG_CR_IE_Msk
10908+
#define RNG_CR_IE RNG_CR_IE_Msk /*!< Interrupt enable */
1090910909
#define RNG_CR_CED_Pos (5UL)
1091010910
#define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
10911-
#define RNG_CR_CED RNG_CR_CED_Msk
10911+
#define RNG_CR_CED RNG_CR_CED_Msk /*!< Clock error detection */
1091210912
#define RNG_CR_ARDIS_Pos (7UL)
10913-
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos)
10914-
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk
10913+
#define RNG_CR_ARDIS_Msk (0x1UL << RNG_CR_ARDIS_Pos) /*!< 0x00000080 */
10914+
#define RNG_CR_ARDIS RNG_CR_ARDIS_Msk /*!< Auto reset disable */
1091510915
#define RNG_CR_RNG_CONFIG3_Pos (8UL)
10916-
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos)
10917-
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
10916+
#define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
10917+
#define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk /*!< RNG configuration 3 */
1091810918
#define RNG_CR_NISTC_Pos (12UL)
10919-
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos)
10920-
#define RNG_CR_NISTC RNG_CR_NISTC_Msk
10919+
#define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
10920+
#define RNG_CR_NISTC RNG_CR_NISTC_Msk /*!< NIST custom */
1092110921
#define RNG_CR_RNG_CONFIG2_Pos (13UL)
10922-
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos)
10923-
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
10922+
#define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
10923+
#define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk /*!< RNG configuration 2 */
1092410924
#define RNG_CR_CLKDIV_Pos (16UL)
10925-
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos)
10926-
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
10925+
#define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
10926+
#define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk /*!< Clock divider factor */
1092710927
#define RNG_CR_CLKDIV_0 (0x1UL << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
1092810928
#define RNG_CR_CLKDIV_1 (0x2UL << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
1092910929
#define RNG_CR_CLKDIV_2 (0x4UL << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
1093010930
#define RNG_CR_CLKDIV_3 (0x8UL << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
1093110931
#define RNG_CR_RNG_CONFIG1_Pos (20UL)
10932-
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos)
10933-
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
10932+
#define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
10933+
#define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk /*!< RNG configuration 1 */
1093410934
#define RNG_CR_CONDRST_Pos (30UL)
10935-
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos)
10936-
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
10935+
#define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
10936+
#define RNG_CR_CONDRST RNG_CR_CONDRST_Msk /*!< Conditioning soft reset */
1093710937
#define RNG_CR_CONFIGLOCK_Pos (31UL)
10938-
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos)
10939-
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
10938+
#define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
10939+
#define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk /*!< RNG configuration lock */
1094010940

1094110941
/******************** Bits definition for RNG_SR register *******************/
1094210942
#define RNG_SR_DRDY_Pos (0UL)
@@ -10985,11 +10985,12 @@ typedef struct
1098510985
#define RNG_HTCR_HTCFG_Msk (0xFFFFFFFFUL << RNG_HTCR_HTCFG_Pos) /*!< 0xFFFFFFFF */
1098610986
#define RNG_HTCR_HTCFG RNG_HTCR_HTCFG_Msk
1098710987

10988+
10989+
1098810990
/******************** RNG Nist Compliance Values *******************/
1098910991
#define RNG_CR_NIST_VALUE (0x00F02D00U)
1099010992
#define RNG_NSCR_NIST_VALUE (0x0003FFFFU)
1099110993
#define RNG_HTCR_NIST_VALUE (0xAAC7U)
10992-
1099310994
/******************************************************************************/
1099410995
/* */
1099510996
/* Real-Time Clock (RTC) */

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