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| 1 | +/* |
| 2 | + ******************************************************************************* |
| 3 | + * Copyright (c) 2026, STMicroelectronics |
| 4 | + * All rights reserved. |
| 5 | + * |
| 6 | + * This software component is licensed by ST under BSD 3-Clause license, |
| 7 | + * the "License"; You may not use this file except in compliance with the |
| 8 | + * License. You may obtain a copy of the License at: |
| 9 | + * opensource.org/licenses/BSD-3-Clause |
| 10 | + * |
| 11 | + ******************************************************************************* |
| 12 | + */ |
| 13 | +#if defined(ARDUINO_DISCO_F723IE) |
| 14 | + |
| 15 | +#include "pins_arduino.h" |
| 16 | + |
| 17 | +// Pin number |
| 18 | +const PinName digitalPin[] = { |
| 19 | + PA_3, // D0 - USART2_RX |
| 20 | + PA_2, // D1 - USART2_TX |
| 21 | + PC_5, // D2 |
| 22 | + PE_5, // D3 - TIM9_CH1 |
| 23 | + PH_3, // D4 |
| 24 | + PB_0, // D5 - TIM3_CH3 |
| 25 | + PE_6, // D6 - TIM9_CH2 |
| 26 | + PE_3, // D7 |
| 27 | + PE_4, // D8 |
| 28 | + PH_6, // D9 - TIM12_CH1 |
| 29 | + PA_1, // D10 - TIM2_CH2 / SPI1_NSS |
| 30 | + PB_5, // D11 - TIM3_CH2 / SPI1_MOSI |
| 31 | + PB_4, // D12 - SPI1_MISO |
| 32 | + PA_5, // D13 - SPI1_SCK |
| 33 | + PH_5, // D14 - I2C2_SDA |
| 34 | + PH_4, // D15 - I2C2_SCL |
| 35 | + PA_6, // A0 |
| 36 | + PA_4, // A1 |
| 37 | + PC_4, // A2 |
| 38 | + PF_10, // A3 - ADC3_IN8 |
| 39 | + PC_0, // A4 |
| 40 | + PC_1, // A5 |
| 41 | + PA_0, // User button |
| 42 | + PA_7, // LED_RED |
| 43 | + PB_1, // LED_GREEN |
| 44 | + PC_6, // ST-LINK VCP TX |
| 45 | + PC_7, // ST-LINK VCP RX |
| 46 | + PA_8, |
| 47 | + PA_9, |
| 48 | + PA_10, |
| 49 | + PA_11, |
| 50 | + PA_12, |
| 51 | + PA_13, |
| 52 | + PA_14, |
| 53 | + PA_15, |
| 54 | + PB_2, |
| 55 | + PB_3, |
| 56 | + PB_6, |
| 57 | + PB_7, |
| 58 | + PB_8, |
| 59 | + PB_9, |
| 60 | + PB_10, |
| 61 | + PB_11, |
| 62 | + PB_12, |
| 63 | + PB_13, |
| 64 | + PB_14, |
| 65 | + PB_15, |
| 66 | + PC_2, |
| 67 | + PC_3, |
| 68 | + PC_8, |
| 69 | + PC_9, |
| 70 | + PC_10, |
| 71 | + PC_11, |
| 72 | + PC_12, |
| 73 | + PC_13, |
| 74 | + PC_14, |
| 75 | + PC_15, |
| 76 | + PD_0, |
| 77 | + PD_1, |
| 78 | + PD_2, |
| 79 | + PD_3, |
| 80 | + PD_4, |
| 81 | + PD_5, |
| 82 | + PD_6, |
| 83 | + PD_7, |
| 84 | + PD_8, |
| 85 | + PD_9, |
| 86 | + PD_10, |
| 87 | + PD_11, |
| 88 | + PD_12, |
| 89 | + PD_13, |
| 90 | + PD_14, |
| 91 | + PD_15, |
| 92 | + PE_0, |
| 93 | + PE_1, |
| 94 | + PE_2, |
| 95 | + PE_7, |
| 96 | + PE_8, |
| 97 | + PE_9, |
| 98 | + PE_10, |
| 99 | + PE_11, |
| 100 | + PE_12, |
| 101 | + PE_13, |
| 102 | + PE_14, |
| 103 | + PE_15, |
| 104 | + PF_0, |
| 105 | + PF_1, |
| 106 | + PF_2, |
| 107 | + PF_3, |
| 108 | + PF_4, |
| 109 | + PF_5, |
| 110 | + PF_6, |
| 111 | + PF_7, |
| 112 | + PF_8, |
| 113 | + PF_9, |
| 114 | + PF_11, |
| 115 | + PF_12, |
| 116 | + PF_13, |
| 117 | + PF_14, |
| 118 | + PF_15, |
| 119 | + PG_0, |
| 120 | + PG_1, |
| 121 | + PG_2, |
| 122 | + PG_3, |
| 123 | + PG_4, |
| 124 | + PG_5, |
| 125 | + PG_8, |
| 126 | + PG_9, |
| 127 | + PG_10, |
| 128 | + PG_11, |
| 129 | + PG_12, |
| 130 | + PG_13, |
| 131 | + PG_14, |
| 132 | + PG_15, |
| 133 | + PH_0, |
| 134 | + PH_1, |
| 135 | + PH_2, |
| 136 | + PH_7, |
| 137 | + PH_8, |
| 138 | + PH_9, |
| 139 | + PH_10, |
| 140 | + PH_11, |
| 141 | + PH_12, |
| 142 | + PH_13, |
| 143 | + PH_14, |
| 144 | + PH_15, |
| 145 | + PI_0, |
| 146 | + PI_1, |
| 147 | + PI_2, |
| 148 | + PI_3, |
| 149 | + PI_4, |
| 150 | + PI_5, |
| 151 | + PI_6, |
| 152 | + PI_7, |
| 153 | + PI_8, |
| 154 | + PI_9, |
| 155 | + PI_10, |
| 156 | + PI_11 |
| 157 | +}; |
| 158 | + |
| 159 | +// Analog (Ax) pin number array |
| 160 | +const pin_size_t analogInputPin[] = { |
| 161 | + 16, // A0 |
| 162 | + 17, // A1 |
| 163 | + 18, // A2 |
| 164 | + 19, // A3 |
| 165 | + 20, // A4 |
| 166 | + 21 // A5 |
| 167 | +}; |
| 168 | + |
| 169 | +// ---------------------------------------------------------------------------- |
| 170 | + |
| 171 | +#ifdef __cplusplus |
| 172 | +extern "C" { |
| 173 | +#endif |
| 174 | + |
| 175 | +/** |
| 176 | + * @brief Board-specific early init, called from main() before setup(), |
| 177 | + * but after the core has already enabled the Cortex-M7 I/D-Cache |
| 178 | + * (see premain() in cores/arduino/main.cpp). |
| 179 | + * |
| 180 | + * The ARMv7-M *default* memory map treats 0x60000000-0x7FFFFFFF |
| 181 | + * (all FMC NOR/SRAM bank windows - PSRAM on NE1 at 0x60000000, the |
| 182 | + * on-board LCD on NE2 at 0x64000000) as cacheable "Normal/External |
| 183 | + * RAM" unless an MPU region says otherwise. With the D-Cache |
| 184 | + * enabled and no MPU region configured, writes to a memory-mapped |
| 185 | + * peripheral register interface there (e.g. the LCD's |
| 186 | + * command/index and data registers) can get absorbed into the |
| 187 | + * cache instead of reaching the external bus: no crash, no hang, |
| 188 | + * the external device just never receives a coherent byte stream. |
| 189 | + * ST's own reference firmware for this board does the same thing |
| 190 | + * for the same reason (see MPU_ConfigPSRAM() in the STM32CubeF7 |
| 191 | + * BSP example Applications/Display/LCD_PicturesFromUSB/Src/main.c). |
| 192 | + * @param None |
| 193 | + * @retval None |
| 194 | + */ |
| 195 | +WEAK void initVariant(void) |
| 196 | +{ |
| 197 | + HAL_MPU_Disable(); |
| 198 | + |
| 199 | + MPU_Region_InitTypeDef mpu = {0}; |
| 200 | + mpu.Enable = MPU_REGION_ENABLE; |
| 201 | + mpu.BaseAddress = 0x64000000; // FMC Bank2 (NE2, on-board LCD) |
| 202 | + mpu.Size = MPU_REGION_SIZE_64MB; // whole NE2 decode window |
| 203 | + mpu.AccessPermission = MPU_REGION_FULL_ACCESS; |
| 204 | + mpu.IsBufferable = MPU_ACCESS_NOT_BUFFERABLE; |
| 205 | + mpu.IsCacheable = MPU_ACCESS_NOT_CACHEABLE; |
| 206 | + mpu.IsShareable = MPU_ACCESS_SHAREABLE; |
| 207 | + mpu.Number = MPU_REGION_NUMBER0; |
| 208 | + mpu.TypeExtField = MPU_TEX_LEVEL0; |
| 209 | + mpu.SubRegionDisable = 0x00; |
| 210 | + mpu.DisableExec = MPU_INSTRUCTION_ACCESS_DISABLE; |
| 211 | + HAL_MPU_ConfigRegion(&mpu); |
| 212 | + |
| 213 | + HAL_MPU_Enable(MPU_PRIVILEGED_DEFAULT); |
| 214 | +} |
| 215 | + |
| 216 | +/** |
| 217 | + * @brief System Clock Configuration |
| 218 | + * The system Clock is configured as follows: |
| 219 | + * System Clock source = PLL (HSE) |
| 220 | + * SYSCLK(Hz) = 216000000 |
| 221 | + * HCLK(Hz) = 216000000 |
| 222 | + * AHB Prescaler = 1 |
| 223 | + * APB1 Prescaler = 4 |
| 224 | + * APB2 Prescaler = 2 |
| 225 | + * HSE Frequency(Hz) = 25000000 |
| 226 | + * PLL_M = 25 |
| 227 | + * PLL_N = 432 |
| 228 | + * PLL_P = 2 |
| 229 | + * PLL_Q = 9 |
| 230 | + * VDD(V) = 3.3 |
| 231 | + * Main regulator output voltage = Scale1 mode |
| 232 | + * Flash Latency(WS) = 7 |
| 233 | + * @param None |
| 234 | + * @retval None |
| 235 | + */ |
| 236 | +WEAK void SystemClock_Config(void) |
| 237 | +{ |
| 238 | + RCC_OscInitTypeDef RCC_OscInitStruct = {}; |
| 239 | + RCC_ClkInitTypeDef RCC_ClkInitStruct = {}; |
| 240 | + RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {}; |
| 241 | + |
| 242 | + /* Configure the main internal regulator output voltage */ |
| 243 | + __HAL_RCC_PWR_CLK_ENABLE(); |
| 244 | + __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
| 245 | + |
| 246 | + /* Initializes the RCC Oscillators according to the specified parameters */ |
| 247 | + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; |
| 248 | + RCC_OscInitStruct.HSEState = RCC_HSE_ON; |
| 249 | + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
| 250 | + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
| 251 | + RCC_OscInitStruct.PLL.PLLM = 25; |
| 252 | + RCC_OscInitStruct.PLL.PLLN = 432; |
| 253 | + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; |
| 254 | + RCC_OscInitStruct.PLL.PLLQ = 9; |
| 255 | + if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) { |
| 256 | + Error_Handler(); |
| 257 | + } |
| 258 | + |
| 259 | + /* Activate the Over-Drive mode */ |
| 260 | + if (HAL_PWREx_EnableOverDrive() != HAL_OK) { |
| 261 | + Error_Handler(); |
| 262 | + } |
| 263 | + |
| 264 | + /* Initializes the CPU, AHB and APB buses clocks */ |
| 265 | + RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK |
| 266 | + | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2; |
| 267 | + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; |
| 268 | + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; |
| 269 | + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; |
| 270 | + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; |
| 271 | + |
| 272 | + if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7) != HAL_OK) { |
| 273 | + Error_Handler(); |
| 274 | + } |
| 275 | + |
| 276 | + /* Initializes the peripherals clock (48 MHz for USB OTG FS/HS) */ |
| 277 | + PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_CLK48; |
| 278 | + PeriphClkInitStruct.Clk48ClockSelection = RCC_CLK48SOURCE_PLL; |
| 279 | + if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) { |
| 280 | + Error_Handler(); |
| 281 | + } |
| 282 | +} |
| 283 | + |
| 284 | +#ifdef __cplusplus |
| 285 | +} |
| 286 | +#endif |
| 287 | + |
| 288 | +#endif /* ARDUINO_DISCO_F723IE */ |
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