diff --git a/README.md b/README.md
index 368474007a..683d717a8e 100644
--- a/README.md
+++ b/README.md
@@ -153,6 +153,7 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32G431RB | [Nucleo G431RB](https://www.st.com/en/evaluation-tools/nucleo-g431rb.html) | *1.7.0* | |
| :green_heart: | STM32G474RE | [Nucleo G474RE](https://www.st.com/en/evaluation-tools/nucleo-g474re.html) | *1.7.0* | |
| :green_heart: | STM32H503RB | [Nucleo H503RB](https://www.st.com/en/evaluation-tools/nucleo-h503rb.html) | *2.7.0* | |
+| :yellow_heart: | STM32H533RE | [Nucleo H533RE](https://www.st.com/en/evaluation-tools/nucleo-h533re.html) | **3.0.1** | |
| :green_heart: | STM32L010RB | [Nucleo L010RB](https://www.st.com/en/evaluation-tools/nucleo-l010rb.html) | *2.1.0* | |
| :green_heart: | STM32L053R8 | [Nucleo L053R8](http://www.st.com/en/evaluation-tools/nucleo-l053r8.html) | *0.1.0* | |
| :green_heart: | STM32L073RZ | [Nucleo L073RZ](http://www.st.com/en/evaluation-tools/nucleo-l073rz.html) | *1.4.0* | |
@@ -595,6 +596,8 @@ User can add a STM32 based board following this [wiki](https://github.com/stm32d
| :green_heart: | STM32H503CB | Generic Board | *2.9.0* | |
| :green_heart: | STM32H503KB | Generic Board | *2.8.1* | |
| :green_heart: | STM32H503RB | Generic Board | *2.7.0* | |
+| :yellow_heart: | STM32H523RC
STM32H523RE | Generic Board | **3.0.1** | |
+| :yellow_heart: | STM32H533RE | Generic Board | **3.0.1** | |
| :green_heart: | STM32H562RGT | WeAct H562RGT | *2.9.0* | |
| :green_heart: | STM32H562RGT
STM32H562RIT | Generic Board | *2.9.0* | |
| :green_heart: | STM32H562RGV
STM32H562RIV | Generic Board | *3.0.0* | |
diff --git a/boards.txt b/boards.txt
index 07c3cac043..9849aa95cb 100644
--- a/boards.txt
+++ b/boards.txt
@@ -803,6 +803,21 @@ Nucleo_64.menu.pnum.NUCLEO_H503RB.build.variant=STM32H5xx/H503RBT
Nucleo_64.menu.pnum.NUCLEO_H503RB.openocd.target=stm32h5x
Nucleo_64.menu.pnum.NUCLEO_H503RB.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
+# NUCLEO H533RE
+Nucleo_64.menu.pnum.NUCLEO_H533RE=Nucleo H533RE
+Nucleo_64.menu.pnum.NUCLEO_H533RE.node=NOD_H533RE
+Nucleo_64.menu.pnum.NUCLEO_H533RE.upload.maximum_size=524288
+Nucleo_64.menu.pnum.NUCLEO_H533RE.upload.maximum_data_size=278528
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.mcu=cortex-m33
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.fpu=-mfpu=fpv5-sp-d16
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.float-abi=-mfloat-abi=hard
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.board=NUCLEO_H533RE
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.series=STM32H5xx
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.product_line=STM32H533xx
+Nucleo_64.menu.pnum.NUCLEO_H533RE.build.variant=STM32H5xx/H523R(C-E)T_H533RET
+Nucleo_64.menu.pnum.NUCLEO_H533RE.openocd.target=stm32h5x
+Nucleo_64.menu.pnum.NUCLEO_H533RE.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H533.svd
+
# NUCLEO_L010RB board
Nucleo_64.menu.pnum.NUCLEO_L010RB=Nucleo L010RB
Nucleo_64.menu.pnum.NUCLEO_L010RB.node=NODE_L010RB
@@ -9507,6 +9522,33 @@ GenH5.menu.pnum.GENERIC_H503RBTX.build.product_line=STM32H503xx
GenH5.menu.pnum.GENERIC_H503RBTX.build.variant=STM32H5xx/H503RBT
GenH5.menu.pnum.GENERIC_H503RBTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H503.svd
+# Generic H523RCTx
+GenH5.menu.pnum.GENERIC_H523RCTX=Generic H523RCTx
+GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_size=262144
+GenH5.menu.pnum.GENERIC_H523RCTX.upload.maximum_data_size=278528
+GenH5.menu.pnum.GENERIC_H523RCTX.build.board=GENERIC_H523RCTX
+GenH5.menu.pnum.GENERIC_H523RCTX.build.product_line=STM32H523xx
+GenH5.menu.pnum.GENERIC_H523RCTX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
+GenH5.menu.pnum.GENERIC_H523RCTX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H523.svd
+
+# Generic H523RETx
+GenH5.menu.pnum.GENERIC_H523RETX=Generic H523RETx
+GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_size=524288
+GenH5.menu.pnum.GENERIC_H523RETX.upload.maximum_data_size=278528
+GenH5.menu.pnum.GENERIC_H523RETX.build.board=GENERIC_H523RETX
+GenH5.menu.pnum.GENERIC_H523RETX.build.product_line=STM32H523xx
+GenH5.menu.pnum.GENERIC_H523RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
+GenH5.menu.pnum.GENERIC_H523RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H523.svd
+
+# Generic H533RETx
+GenH5.menu.pnum.GENERIC_H533RETX=Generic H533RETx
+GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_size=524288
+GenH5.menu.pnum.GENERIC_H533RETX.upload.maximum_data_size=278528
+GenH5.menu.pnum.GENERIC_H533RETX.build.board=GENERIC_H533RETX
+GenH5.menu.pnum.GENERIC_H533RETX.build.product_line=STM32H533xx
+GenH5.menu.pnum.GENERIC_H533RETX.build.variant=STM32H5xx/H523R(C-E)T_H533RET
+GenH5.menu.pnum.GENERIC_H533RETX.debug.svd_file={runtime.tools.STM32_SVD.path}/svd/STM32H5xx/STM32H533.svd
+
# Generic H562RGTx
GenH5.menu.pnum.GENERIC_H562RGTX=Generic H562RGTx
GenH5.menu.pnum.GENERIC_H562RGTX.upload.maximum_size=1048576
@@ -17752,4 +17794,4 @@ Phoque.menu.rtlib.nanofs.build.flags.ldspecs=--specs=nano.specs -u _scanf_float
Phoque.menu.rtlib.nanofps=Newlib Nano + Float Printf/Scanf
Phoque.menu.rtlib.nanofps.build.flags.ldspecs=--specs=nano.specs -u _printf_float -u _scanf_float
Phoque.menu.rtlib.full=Newlib Standard
-Phoque.menu.rtlib.full.build.flags.ldspecs=
\ No newline at end of file
+Phoque.menu.rtlib.full.build.flags.ldspecs=
diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c b/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c
index 03d7d6e862..ac7d15cf67 100644
--- a/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c
+++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/generic_clock.c
@@ -21,8 +21,93 @@
*/
WEAK void SystemClock_Config(void)
{
- /* SystemClock_Config can be generated by STM32CubeMX */
-#warning "SystemClock_Config() is empty. Default clock at reset is used."
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+
+ /** Configure the main internal regulator output voltage
+ */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
+ | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_CSI;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.LSIState = RCC_LSI_ON;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.CSIState = RCC_CSI_ON;
+ RCC_OscInitStruct.CSICalibrationValue = RCC_CSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_CSI;
+ RCC_OscInitStruct.PLL.PLLM = 1;
+ RCC_OscInitStruct.PLL.PLLN = 125;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the CPU, AHB and APB buses clocks
+ */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /** Initializes the peripherals clock
+ */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_LPUART1
+ | RCC_PERIPHCLK_SDMMC1 | RCC_PERIPHCLK_SPI1
+ | RCC_PERIPHCLK_SPI2 | RCC_PERIPHCLK_SPI3
+ | RCC_PERIPHCLK_SPI4 | RCC_PERIPHCLK_USB;
+
+ PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK;
+ PeriphClkInitStruct.DacLowPowerClockSelection = RCC_DACLPCLKSOURCE_LSI;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_CSI;
+ PeriphClkInitStruct.PLL2.PLL2M = 1;
+ PeriphClkInitStruct.PLL2.PLL2N = 96;
+ PeriphClkInitStruct.PLL2.PLL2P = 2;
+ PeriphClkInitStruct.PLL2.PLL2Q = 4;
+ PeriphClkInitStruct.PLL2.PLL2R = 2;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
+ PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ;
+ PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL2Q;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+
+
+ /** Configure the programming delay
+ */
+ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
}
#endif /* ARDUINO_GENERIC_* */
diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/ldscript.ld b/variants/STM32H5xx/H523R(C-E)T_H533RET/ldscript.ld
new file mode 100644
index 0000000000..c256d82cf1
--- /dev/null
+++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/ldscript.ld
@@ -0,0 +1,189 @@
+/*
+******************************************************************************
+**
+** @file : LinkerScript.ld
+**
+** @author : Auto-generated by STM32CubeIDE
+**
+** @brief : Linker script for STM32H533RETx Device from STM32H5 series
+** 512KBytes FLASH
+** 272KBytes RAM
+**
+** Set heap size, stack size and stack location according
+** to application requirements.
+**
+** Set memory bank area and size if external memory is used
+**
+** Target : STMicroelectronics STM32
+**
+** Distribution: The file is distributed as is, without any warranty
+** of any kind.
+**
+******************************************************************************
+** @attention
+**
+** Copyright (c) 2026 STMicroelectronics.
+** All rights reserved.
+**
+** This software is licensed under terms that can be found in the LICENSE file
+** in the root directory of this software component.
+** If no LICENSE file comes with this software, it is provided AS-IS.
+**
+******************************************************************************
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+/* Highest address of the user mode stack */
+_estack = ORIGIN(RAM) + LENGTH(RAM); /* end of "RAM" Ram type memory */
+_sstack = _estack - _Min_Stack_Size;
+
+_Min_Heap_Size = 0x200; /* required amount of heap */
+_Min_Stack_Size = 0x400; /* required amount of stack */
+
+/* Memories definition */
+MEMORY
+{
+ RAM (xrw) : ORIGIN = 0x20000000, LENGTH = LD_MAX_DATA_SIZE
+ FLASH (rx) : ORIGIN = 0x08000000 + LD_FLASH_OFFSET, LENGTH = LD_MAX_SIZE - LD_FLASH_OFFSET
+}
+
+/* Sections */
+SECTIONS
+{
+
+ /* The startup code into "FLASH" Rom type memory */
+ .isr_vector :
+ {
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } >FLASH
+
+ /* The program code and other data into "FLASH" Rom type memory */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+
+ KEEP (*(.init))
+ KEEP (*(.fini))
+
+ . = ALIGN(4);
+ _etext = .; /* define a global symbols at end of code */
+ } >FLASH
+
+ /* Constant data into "FLASH" Rom type memory */
+ .rodata :
+ {
+ . = ALIGN(4);
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM.extab (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ . = ALIGN(4);
+ } >FLASH
+
+ .ARM (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ . = ALIGN(4);
+ } >FLASH
+
+ .preinit_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .init_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ .fini_array (READONLY) : /* The "READONLY" keyword is only supported in GCC11 and later, remove it if using GCC10 or earlier. */
+ {
+ . = ALIGN(4);
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ . = ALIGN(4);
+ } >FLASH
+
+ /* Used by the startup to initialize data */
+ _sidata = LOADADDR(.data);
+
+ /* Initialized data sections into "RAM" Ram type memory */
+ .data :
+ {
+ . = ALIGN(4);
+ _sdata = .; /* create a global symbol at data start */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ *(.RamFunc) /* .RamFunc sections */
+ *(.RamFunc*) /* .RamFunc* sections */
+
+ . = ALIGN(4);
+ _edata = .; /* define a global symbol at data end */
+
+ } >RAM AT> FLASH
+
+ /* Uninitialized data section into "RAM" Ram type memory */
+ . = ALIGN(4);
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ _sbss = .; /* define a global symbol at bss start */
+ __bss_start__ = _sbss;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+
+ . = ALIGN(4);
+ _ebss = .; /* define a global symbol at bss end */
+ __bss_end__ = _ebss;
+ } >RAM
+
+ /* User_heap_stack section, used to check that there is enough "RAM" Ram type memory left */
+ ._user_heap_stack :
+ {
+ . = ALIGN(8);
+ PROVIDE ( end = . );
+ PROVIDE ( _end = . );
+ . = . + _Min_Heap_Size;
+ . = . + _Min_Stack_Size;
+ . = ALIGN(8);
+ } >RAM
+
+ /* Remove information from the compiler libraries */
+ /DISCARD/ :
+ {
+ libc.a ( * )
+ libm.a ( * )
+ libgcc.a ( * )
+ }
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+}
diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.cpp b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.cpp
new file mode 100644
index 0000000000..835a3d9ebf
--- /dev/null
+++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.cpp
@@ -0,0 +1,207 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020-2026, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#if defined(ARDUINO_NUCLEO_H533RE)
+#include "pins_arduino.h"
+
+// Digital PinName array
+const PinName digitalPin[] = {
+ PB_15, //D0
+ PB_14, //D1
+ PC_8, //D2
+ PB_3, //D3
+ PB_5, //D4
+ PB_4, //D5
+ PB_10, //D6
+ PA_8, //D7
+ PC_7, //D8
+ PC_6, //D9
+ PC_9, //D10
+ PA_7, //D11/A10
+ PA_6, //D12A11
+ PA_5, //D13/A12
+ PB_7, //D14
+ PB_6, //D15
+ PC_10, //D16
+ PC_12, //D17
+ PA_13, //D18
+ PA_14, //D19
+ PA_15, //D20
+ PC_13, //D21
+ PC_14, //D22
+ PC_15, //D23
+ PH_0, //D24
+ PH_1, //D25
+ PC_2, //D26/A6
+ PC_3, //D27/A7
+ PC_11, //D28
+ PD_2, //D29
+ PA_0, //D30/A0
+ PA_1, //D31/A1
+ PB_1, //D32/A2
+ PB_0, //D33/A3
+ PC_1, //D34/A4
+ PC_0, //D35/A5
+ PA_9, //D36
+ PA_10, //D37
+ PC_5, //D38/A8
+ PA_12, //D39
+ PA_11, //D40
+ PB_12, //D41
+ PB_2, //D42
+ PB_15, //D43
+ PB_14, //D44
+ PB_13, //D45
+ PC_4, //D46/A9
+ PB_8, //D47
+ PA_2, //D48/A13
+ PA_3, //D49/A14
+ PA_4 //D50/A15
+};
+
+// Analog (Ax) pin number array
+const pin_size_t analogInputPin[] = {
+ 30, // A0, PA0
+ 31, // A1, PA1
+ 32, // A2, PB1
+ 33, // A3, PB0
+ 34, // A4, PC1
+ 35, // A5, PC0
+ 26, // A6, PC2
+ 27, // A7, PC3
+ 38, // A8, PC5
+ 46, // A9, PC4
+ 11, // A10, PA7
+ 12, // A11, PA6
+ 13, // A12, PA5
+ 48, // A13, PA2
+ 49, // A14, PA3
+ 50 // A15, PA4
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief System Clock Configuration
+ * @param None
+ * @retval None
+ */
+WEAK void SystemClock_Config(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct = {};
+ RCC_ClkInitTypeDef RCC_ClkInitStruct = {};
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {};
+ RCC_CRSInitTypeDef RCC_CRSInitStruct = {};
+
+ /* Configure the main internal regulator output voltage */
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE0);
+
+ while (!__HAL_PWR_GET_FLAG(PWR_FLAG_VOSRDY)) {}
+
+ /** Configure LSE Drive Capability
+ * Warning : Only applied when the LSE is disabled.
+ */
+ HAL_PWR_EnableBkUpAccess();
+ __HAL_RCC_LSEDRIVE_CONFIG(RCC_LSEDRIVE_LOW);
+
+ /** Initializes the RCC Oscillators according to the specified parameters
+ * in the RCC_OscInitTypeDef structure.
+ */
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI48 | RCC_OSCILLATORTYPE_HSI
+ | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE;
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON;
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSIDiv = RCC_HSI_DIV2;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.HSI48State = RCC_HSI48_ON;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLL1_SOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 6;
+ RCC_OscInitStruct.PLL.PLLN = 125;
+ RCC_OscInitStruct.PLL.PLLP = 2;
+ RCC_OscInitStruct.PLL.PLLQ = 4;
+ RCC_OscInitStruct.PLL.PLLR = 2;
+ RCC_OscInitStruct.PLL.PLLRGE = RCC_PLL1_VCIRANGE_2;
+ RCC_OscInitStruct.PLL.PLLVCOSEL = RCC_PLL1_VCORANGE_WIDE;
+ RCC_OscInitStruct.PLL.PLLFRACN = 0;
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+ /* Initializes the CPU, AHB and APB buses clocks */
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_SYSCLK
+ | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2
+ | RCC_CLOCKTYPE_PCLK3;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;
+ RCC_ClkInitStruct.APB3CLKDivider = RCC_HCLK_DIV1;
+
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_5) != HAL_OK) {
+ Error_Handler();
+ }
+ /* Initializes the peripherals clock */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_ADCDAC | RCC_PERIPHCLK_DAC
+ | RCC_PERIPHCLK_LPUART1 | RCC_PERIPHCLK_SDMMC1
+ | RCC_PERIPHCLK_SPI1 | RCC_PERIPHCLK_SPI2
+ | RCC_PERIPHCLK_SPI3 | RCC_PERIPHCLK_SPI4
+ | RCC_PERIPHCLK_USB;;
+ PeriphClkInitStruct.DacLowPowerClockSelection = RCC_DACLPCLKSOURCE_LSE;
+ PeriphClkInitStruct.AdcDacClockSelection = RCC_ADCDACCLKSOURCE_HCLK;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_HSI;
+ PeriphClkInitStruct.Sdmmc1ClockSelection = RCC_SDMMC1CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi1ClockSelection = RCC_SPI1CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi2ClockSelection = RCC_SPI2CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.Spi3ClockSelection = RCC_SPI3CLKSOURCE_PLL1Q;
+ PeriphClkInitStruct.PLL2.PLL2Source = RCC_PLL2_SOURCE_HSE;
+ PeriphClkInitStruct.PLL2.PLL2M = 6;
+ PeriphClkInitStruct.PLL2.PLL2N = 125;
+ PeriphClkInitStruct.PLL2.PLL2P = 2;
+ PeriphClkInitStruct.PLL2.PLL2Q = 4;
+ PeriphClkInitStruct.PLL2.PLL2R = 2;
+ PeriphClkInitStruct.PLL2.PLL2RGE = RCC_PLL2_VCIRANGE_2;
+ PeriphClkInitStruct.PLL2.PLL2VCOSEL = RCC_PLL2_VCORANGE_WIDE;
+ PeriphClkInitStruct.PLL2.PLL2FRACN = 0.0;
+ PeriphClkInitStruct.PLL2.PLL2ClockOut = RCC_PLL2_DIVQ;
+ PeriphClkInitStruct.Spi4ClockSelection = RCC_SPI4CLKSOURCE_PLL2Q;
+ PeriphClkInitStruct.UsbClockSelection = RCC_USBCLKSOURCE_HSI48;
+
+ if (HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct) != HAL_OK) {
+ Error_Handler();
+ }
+
+
+ /* Enable the CRS APB clock */
+ __HAL_RCC_CRS_CLK_ENABLE();
+
+ /* Configures CRS */
+ RCC_CRSInitStruct.Prescaler = RCC_CRS_SYNC_DIV1;
+ RCC_CRSInitStruct.Source = RCC_CRS_SYNC_SOURCE_LSE;
+ RCC_CRSInitStruct.Polarity = RCC_CRS_SYNC_POLARITY_RISING;
+ RCC_CRSInitStruct.ReloadValue = __HAL_RCC_CRS_RELOADVALUE_CALCULATE(48000000, 32768);
+ RCC_CRSInitStruct.ErrorLimitValue = 34;
+ RCC_CRSInitStruct.HSI48CalibrationValue = 32;
+
+ HAL_RCCEx_CRSConfig(&RCC_CRSInitStruct);
+
+ /* Configure the programming delay */
+ __HAL_FLASH_SET_PROGRAM_DELAY(FLASH_PROGRAMMING_DELAY_2);
+}
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* ARDUINO_NUCLEO_H533RE */
diff --git a/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.h b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.h
new file mode 100644
index 0000000000..3b28362dcc
--- /dev/null
+++ b/variants/STM32H5xx/H523R(C-E)T_H533RET/variant_NUCLEO_H533RE.h
@@ -0,0 +1,208 @@
+/*
+ *******************************************************************************
+ * Copyright (c) 2020-2026, STMicroelectronics
+ * All rights reserved.
+ *
+ * This software component is licensed by ST under BSD 3-Clause license,
+ * the "License"; You may not use this file except in compliance with the
+ * License. You may obtain a copy of the License at:
+ * opensource.org/licenses/BSD-3-Clause
+ *
+ *******************************************************************************
+ */
+#pragma once
+
+/*----------------------------------------------------------------------------
+ * STM32 pins number
+ *----------------------------------------------------------------------------*/
+#define PB15 0
+#define PB14 1
+#define PC8 2
+#define PB3 3
+#define PB5 4
+#define PB4 5
+#define PB10 6
+#define PA8 7
+#define PC7 8
+#define PC6 9
+#define PC9 10
+#define PA7 PIN_A10
+#define PA6 PIN_A11
+#define PA5 PIN_A12
+#define PB7 14
+#define PB6 15
+// CN7 odd pins
+#define PC10 16
+#define PC12 17
+// PA13 and PA14 are shared with SWD signals connected to STLINK-V3EC.
+// It is not recommended to use them as I/O pins.
+// By default, they are used as SWD signals (SB40 and SB41 ON).
+#define PA13 18
+#define PA14 19
+#define PA15 20
+#define PC13 21
+#define PC14 22
+#define PC15 23
+#define PH0 24
+#define PH1 25
+#define PC2 PIN_A6
+#define PC3 PIN_A7
+// CN7 even pins
+#define PC11 28
+#define PD2 29
+#define PA0 PIN_A0
+#define PA1 PIN_A1
+#define PB1 PIN_A2
+#define PB0 PIN_A3
+#define PC1 PIN_A4
+#define PC0 PIN_A5
+// CN10 odd pins are D0-D15
+// CN10 even pins
+#define PA9 36
+#define PA10 37
+#define PC5 PIN_A8
+#define PA12 39
+#define PA11 40
+#define PB12 41
+#define PB2 42
+// 43 is PB15 (0)
+// 44 is PB14 (1)
+#define PB13 45
+#define PC4 PIN_A9
+#define PB8 47
+//Other
+#define PA2 PIN_A13
+#define PA3 PIN_A14
+#define PA4 PIN_A15
+
+
+
+// Alternate pins number
+#define PA0_ALT1 (PA0 | ALT1)
+#define PA1_ALT1 (PA1 | ALT1)
+#define PA1_ALT2 (PA1 | ALT2)
+#define PA2_ALT1 (PA2 | ALT1)
+#define PA2_ALT2 (PA2 | ALT2)
+#define PA3_ALT1 (PA3 | ALT1)
+#define PA3_ALT2 (PA3 | ALT2)
+#define PA4_ALT1 (PA4 | ALT1)
+#define PA5_ALT1 (PA5 | ALT1)
+#define PA6_ALT1 (PA6 | ALT1)
+#define PA7_ALT1 (PA7 | ALT1)
+#define PA7_ALT2 (PA7 | ALT2)
+#define PA9_ALT1 (PA9 | ALT1)
+#define PA10_ALT1 (PA10 | ALT1)
+#define PA11_ALT1 (PA11 | ALT1)
+#define PA12_ALT1 (PA12 | ALT1)
+#define PA15_ALT1 (PA15 | ALT1)
+#define PB0_ALT1 (PB0 | ALT1)
+#define PB0_ALT2 (PB0 | ALT2)
+#define PB1_ALT1 (PB1 | ALT1)
+#define PB1_ALT2 (PB1 | ALT2)
+#define PB3_ALT1 (PB3 | ALT1)
+#define PB4_ALT1 (PB4 | ALT1)
+#define PB5_ALT1 (PB5 | ALT1)
+#define PB6_ALT1 (PB6 | ALT1)
+#define PB6_ALT2 (PB6 | ALT2)
+#define PB7_ALT1 (PB7 | ALT1)
+#define PB10_ALT1 (PB10 | ALT1)
+#define PB13_ALT1 (PB13 | ALT1)
+#define PB14_ALT1 (PB14 | ALT1)
+#define PB14_ALT2 (PB14 | ALT2)
+#define PB15_ALT1 (PB15 | ALT1)
+#define PB15_ALT2 (PB15 | ALT2)
+#define PC0_ALT1 (PC0 | ALT1)
+#define PC1_ALT1 (PC1 | ALT1)
+#define PC2_ALT1 (PC2 | ALT1)
+#define PC3_ALT1 (PC3 | ALT1)
+#define PC4_ALT1 (PC4 | ALT1)
+#define PC5_ALT1 (PC5 | ALT1)
+#define PC6_ALT1 (PC6 | ALT1)
+#define PC7_ALT1 (PC7 | ALT1)
+#define PC8_ALT1 (PC8 | ALT1)
+#define PC9_ALT1 (PC9 | ALT1)
+#define PC10_ALT1 (PC10 | ALT1)
+#define PC11_ALT1 (PC11 | ALT1)
+
+#define NUM_DIGITAL_PINS 51
+#define NUM_ANALOG_INPUTS 16
+
+// On-board LED pin number
+#ifndef LED_BUILTIN
+ #define LED_BUILTIN PA5
+#endif
+
+// On-board user button
+#ifndef USER_BTN
+ #define USER_BTN PC13
+#endif
+
+// Timer Definitions
+// Use TIM6/TIM7 when possible as servo and tone don't need GPIO output pin
+#ifndef TIMER_TONE
+ #define TIMER_TONE TIM6
+#endif
+#ifndef TIMER_SERVO
+ #define TIMER_SERVO TIM7
+#endif
+
+// UART Definitions
+#ifndef SERIAL_UART_INSTANCE
+ #define SERIAL_UART_INSTANCE 2
+#endif
+
+// Default pin used for generic 'Serial' instance
+// Mandatory for Firmata
+#ifndef PIN_SERIAL_RX
+ #define PIN_SERIAL_RX PA3
+#endif
+#ifndef PIN_SERIAL_TX
+ #define PIN_SERIAL_TX PA2_ALT1
+#endif
+
+#define HSE_VALUE 24000000UL /*!< Value of the External oscillator in Hz */
+
+// SDMMC signals not available
+#define SDMMC_CDIR_NA
+
+// Extra HAL modules
+#if !defined(HAL_DAC_MODULE_DISABLED)
+ #define HAL_DAC_MODULE_ENABLED
+#endif
+#if !defined(HAL_I3C_MODULE_DISABLED)
+ #define HAL_I3C_MODULE_ENABLED
+#endif
+#if !defined(HAL_OSPI_MODULE_DISABLED)
+ #define HAL_OSPI_MODULE_ENABLED
+#endif
+#if !defined(HAL_SD_MODULE_DISABLED)
+ #define HAL_SD_MODULE_ENABLED
+#endif
+
+/*----------------------------------------------------------------------------
+ * Arduino objects - C++ only
+ *----------------------------------------------------------------------------*/
+
+#ifdef __cplusplus
+ // These serial port names are intended to allow libraries and architecture-neutral
+ // sketches to automatically default to the correct port name for a particular type
+ // of use. For example, a GPS module would normally connect to SERIAL_PORT_HARDWARE_OPEN,
+ // the first hardware serial port whose RX/TX pins are not dedicated to another use.
+ //
+ // SERIAL_PORT_MONITOR Port which normally prints to the Arduino Serial Monitor
+ //
+ // SERIAL_PORT_USBVIRTUAL Port which is USB virtual serial
+ //
+ // SERIAL_PORT_LINUXBRIDGE Port which connects to a Linux system via Bridge library
+ //
+ // SERIAL_PORT_HARDWARE Hardware serial port, physical RX & TX pins.
+ //
+ // SERIAL_PORT_HARDWARE_OPEN Hardware serial ports which are open for use. Their RX & TX
+ // pins are NOT connected to anything by default.
+ #ifndef SERIAL_PORT_MONITOR
+ #define SERIAL_PORT_MONITOR Serial
+ #endif
+ #ifndef SERIAL_PORT_HARDWARE
+ #define SERIAL_PORT_HARDWARE Serial
+ #endif
+#endif