feat: demo keyspace embeddings=ModeVectorSet

[Code0987]

Design

Follow-up PR 2 from docs/design/2026-09-04-mode-vector-set.md. PR 1 is merged (#44).

What landed

• Stock -demo-keyspace registers embeddings (ModeVectorSet, cosine, dim unlocked until first vadd)
• sc -keyspace embeddings vadd / vsim works on a default supercache-node
• examples/vecset walkthrough: cosine order, replace, dim/zero, L2 vs IP, last rem, delete + recreate
• Docs: README, OPERATIONS, cluster3, design index (ModeVectorSet shipped)

Tests

go test ./...

All packages green locally (including examples/vecset).

Bench risk

None. Node demo registration + example/docs only. No Get/Put/store path change.

[github-actions]

SuperCache bench vs main

Both sides ran once on this same GitHub runner (main, then this PR). Not a merge gate.

Baseline: d009506 (2026-09-06T11:58:35Z) → this run: d009506 (2026-09-06T11:57:49Z)

scbench smoke

cell	ops/s (main → PR)	Δ ops/s	p50	p99
get/hit n=1 c=1 uniform	8845 → 8893	+0.5%	112µs → 112µs	198µs → 203µs
get/hit n=1 c=10 uniform	33307 → 33409	+0.3%	272µs → 271µs	824µs → 831µs
get/hit n=3 c=10 uniform	38623 → 38142	-1.2%	227µs → 229µs	926µs → 933µs
miss/miss-cacheonly n=1 c=1 uniform	8647 → 8703	+0.6%	114µs → 113µs	212µs → 212µs
miss/miss-cacheonly n=1 c=10 uniform	34687 → 34936	+0.7%	262µs → 259µs	843µs → 843µs
set/put n=1 c=1 uniform	8545 → 8629	+1.0%	115µs → 114µs	218µs → 209µs
set/put n=1 c=10 uniform	31726 → 31989	+0.8%	284µs → 285µs	877µs → 857µs

Δ ops/s: green-ish is higher throughput. Latency: lower is better.

go test -bench (ns/op)

benchmark	ns/op (main → PR)	Δ	allocs/op
BenchmarkEngineDelete	769 → 811	+5.5%	6 → 6
BenchmarkEngineGetHit	1230 → 1260	+2.4%	15 → 15
BenchmarkEngineGetHitParallel	1229 → 1296	+5.5%	15 → 15
BenchmarkEngineGetMissCacheOnly	842 → 871	+3.4%	14 → 14
BenchmarkEngineGetMissCacheOnlyParallel	636 → 662	+4.0%	14 → 14
BenchmarkEngineGetMissLoadThrough	1602 → 1610	+0.5%	24 → 24
BenchmarkEngineGetMissLoadThroughParallel	1881 → 1835	-2.4%	23 → 23
BenchmarkEnginePut	1539 → 1669	+8.4%	18 → 18
BenchmarkEnginePutParallel	1429 → 1453	+1.7%	18 → 18
BenchmarkStoreBitSet	112 → 113	+0.4%	1 → 1
BenchmarkStoreCGetHit	73 → 73	+0.3%	0 → 0
BenchmarkStoreCIncr	101 → 101	+0.6%	1 → 1
BenchmarkStoreCMSIncr	121 → 120	-0.2%	0 → 0
BenchmarkStoreCMSIncrN	121 → 123	+1.7%	0 → 0
BenchmarkStoreGeoAdd	9559 → 9559	+0.0%	2 → 2
BenchmarkStoreGeoPosHit	88 → 89	+0.1%	0 → 0
BenchmarkStoreGeoPosMiss	87 → 86	-1.1%	0 → 0
BenchmarkStoreGetHit	292 → 296	+1.1%	2 → 2
BenchmarkStoreGetHitParallel	358 → 360	+0.5%	2 → 2
BenchmarkStoreHGetHit	92 → 92	+0.3%	1 → 1
BenchmarkStoreHGetMiss	85 → 85	-0.3%	0 → 0
BenchmarkStoreHLLAdd	100 → 100	+0.2%	0 → 0
BenchmarkStoreHSet	10614 → 10570	-0.4%	3 → 3
BenchmarkStoreJsonSet	26792 → 26654	-0.5%	207 → 207
BenchmarkStorePut	301 → 303	+0.7%	2 → 2
BenchmarkStorePutParallel	366 → 350	-4.3%	2 → 2
BenchmarkStoreSetAdd	9191 → 9341	+1.6%	2 → 2
BenchmarkStoreSetContainsHit	87 → 88	+0.5%	0 → 0
BenchmarkStoreSetContainsMiss	93 → 86	-7.9%	0 → 0
BenchmarkStoreTopKAdd	997 → 994	-0.3%	20 → 20
BenchmarkStoreVAdd	106980 → 109610	+2.5%	513 → 511
BenchmarkStoreVSim	89498 → 90712	+1.4%	530 → 530
BenchmarkStoreZAdd	9525 → 9539	+0.1%	2 → 2
BenchmarkStoreZScoreHit	86 → 88	+2.9%	0 → 0
BenchmarkStoreZScoreMiss	86 → 87	+1.1%	0 → 0

_{Posted by CI bench job. Not a merge gate.}