feat: Lab ModeStream chapter

[Code0987]

Summary

Lab-only Stream chapter so the explorer can append, range, trim, and delete a named log. No Engine / proto / RF change.

Design: docs/design/2026-09-08-lab-mode-stream.md

What landed vs the design

• In-process Lab keyspace stream (ModeStream, RF=2, StreamMaxLen=0)
• /v1/op: xadd, xrange, xrevrange, xlen, xdel, xtrim (plus existing Delete)
• Chapter Stream (name logs); widget shows minted id and last range as id + payload
• Scene: two XAdd, then XRange - +
• start/end on /v1/op accept string bounds (-, +, (id) without breaking integer start/end for List / Bitmap / ZSet
• Not in this PR (design non-goals): examples/stream binary, stock-node demo keyspace, consumer groups

Product docs

examples/lab/README.md chapter table; docs/design/README.md shipped row. No API/OpenAPI/PLAN change (no new public verb).

Test plan

• go test ./examples/lab (local, green)
• go test ./... (local, green)
• CI test + bench; read <!-- supercache-bench-comment -->

Bench risk

• Hot path? no. Lab HTTP + demo keyspace only.
• Gate: shared smoke ±10%; Get-hit / StoreGetHit allocs flat.

[github-actions]

SuperCache bench vs main

Both sides ran once on this same GitHub runner (main, then this PR). Not a merge gate.

Baseline: 0adb847 (2026-09-08T09:06:54Z) → this run: 0adb847 (2026-09-08T09:06:07Z)

scbench smoke

cell	ops/s (main → PR)	Δ ops/s	p50	p99
get/hit n=1 c=1 uniform	7128 → 7140	+0.2%	143µs → 142µs	224µs → 228µs
get/hit n=1 c=10 uniform	28058 → 27745	-1.1%	327µs → 334µs	934µs → 930µs
get/hit n=3 c=10 uniform	34197 → 34433	+0.7%	260µs → 257µs	947µs → 955µs
miss/miss-cacheonly n=1 c=1 uniform	6896 → 6863	-0.5%	148µs → 148µs	241µs → 247µs
miss/miss-cacheonly n=1 c=10 uniform	28279 → 28963	+2.4%	323µs → 315µs	978µs → 940µs
set/put n=1 c=1 uniform	6809 → 6773	-0.5%	145µs → 146µs	238µs → 246µs
set/put n=1 c=10 uniform	27023 → 26794	-0.8%	339µs → 345µs	978µs → 975µs

Δ ops/s: green-ish is higher throughput. Latency: lower is better.

go test -bench (ns/op)

benchmark	ns/op (main → PR)	Δ	allocs/op
BenchmarkEngineDelete	806 → 833	+3.3%	6 → 6
BenchmarkEngineGetHit	1258 → 1207	-4.1%	15 → 15
BenchmarkEngineGetHitParallel	1160 → 1058	-8.8%	15 → 15
BenchmarkEngineGetMissCacheOnly	909 → 908	-0.0%	14 → 14
BenchmarkEngineGetMissCacheOnlyParallel	693 → 677	-2.3%	14 → 14
BenchmarkEngineGetMissLoadThrough	1714 → 1679	-2.0%	24 → 24
BenchmarkEngineGetMissLoadThroughParallel	1933 → 1902	-1.6%	23 → 23
BenchmarkEnginePut	1607 → 1545	-3.9%	18 → 18
BenchmarkEnginePutParallel	1375 → 1363	-0.9%	18 → 18
BenchmarkStoreBitSet	109 → 127	+17.1%	1 → 1
BenchmarkStoreCGetHit	68 → 68	+0.1%	0 → 0
BenchmarkStoreCIncr	96 → 95	-1.3%	1 → 1
BenchmarkStoreCMSIncr	109 → 116	+6.2%	0 → 0
BenchmarkStoreCMSIncrN	110 → 110	+0.0%	0 → 0
BenchmarkStoreGeoAdd	11762 → 11815	+0.5%	2 → 2
BenchmarkStoreGeoPosHit	80 → 80	+0.3%	0 → 0
BenchmarkStoreGeoPosMiss	86 → 81	-5.7%	0 → 0
BenchmarkStoreGetHit	301 → 300	-0.2%	2 → 2
BenchmarkStoreGetHitParallel	367 → 358	-2.3%	2 → 2
BenchmarkStoreHGetHit	87 → 87	+0.0%	1 → 1
BenchmarkStoreHGetMiss	80 → 80	-0.8%	0 → 0
BenchmarkStoreHLLAdd	95 → 95	-0.0%	0 → 0
BenchmarkStoreHSet	12760 → 13118	+2.8%	3 → 3
BenchmarkStoreJsonSet	26969 → 26317	-2.4%	207 → 207
BenchmarkStorePut	310 → 308	-0.6%	2 → 2
BenchmarkStorePutParallel	380 → 365	-3.9%	2 → 2
BenchmarkStoreSetAdd	11524 → 11535	+0.1%	2 → 2
BenchmarkStoreSetContainsHit	79 → 80	+1.2%	0 → 0
BenchmarkStoreSetContainsMiss	80 → 79	-1.2%	0 → 0
BenchmarkStoreTopKAdd	1065 → 1048	-1.6%	20 → 20
BenchmarkStoreVAdd	118479 → 112523	-5.0%	513 → 513
BenchmarkStoreVSim	91363 → 91751	+0.4%	530 → 530
BenchmarkStoreZAdd	11681 → 11504	-1.5%	2 → 2
BenchmarkStoreZScoreHit	81 → 81	-0.3%	0 → 0
BenchmarkStoreZScoreMiss	81 → 82	+1.4%	0 → 0

_{Posted by CI bench job. Not a merge gate.}