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12 followers · 11 following
  • University of Waterloo
  • Greater Toronto Area

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Achievement: YOLOAchievement: Pull Shark

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Entropify/README.md

Hello there! (General Kenobi, you are a bold one)👋

  • 🔭 I’m currently working on random RTL and embedded projects I find interesting but also help me learn new skills
  • 🌱 I’m currently learning Python, C, Verilog, Java and SystemVerilog & UVM in the future
  • 👯 I’m looking to collaborate on any interesting ideas for hardware and embedded projects
  • 🤔 I’m looking for help with RTL design & verification, VLSI frontend & backend, FPGA implementation, embedded design, PCB design
  • 😄 Pronouns: he/him
  • ⚡ Fun fact: The fastest I've ever skied is 87 km/h, that's faster than city metros!

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  1. Entropic_R32-SC_RISC-V Entropic_R32-SC_RISC-V Public

    Single-cycle RISC-V CPU utilizing the RV32I ISA. Designed, verified and ASIC-flowed

    SystemVerilog 3

  2. spi-pwm-controller-uwasic spi-pwm-controller-uwasic Public

    Forked from UW-ASIC/onboarding-start

    UWASIC PWM peripheral controller chip using SPI protocol with TT's interface and SkyWater 130nm PDK, GDS 3D visualizer in deployed page below ↓

    Python 3

  3. Peteryhs/Weather-Station Peteryhs/Weather-Station Public

    C++ 3

  4. OmniMacro OmniMacro Public

    All the geeky macro / productivity / keyboard / mouse tools you need packaged in one. (win64 only)

    Python 7

  5. my-hdlbits-solutions my-hdlbits-solutions Public

    An archive for my solutions to HDLBits (a RTL learning platform by UofT) problem sets, organized by topic

    Verilog 2

  6. Entropic_R32-P5_RISC-V Entropic_R32-P5_RISC-V Public

    we upgradingggggg!! (this is lowk kinda hard most neuron activation ive ever had)

    SystemVerilog 1