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issue/1565 fix(nvidia): complete runtime support for Qwen MTP - #1566

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big-hip wants to merge 1 commit into
InfiniTensor:InfiniLM-v0.2.9cfrom
big-hip:issue/1565

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@big-hip big-hip commented Sep 19, 2026

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Problem and changes

Closes #1565. Target: InfiniLM-v0.2.9c.

Running Qwen's built-in greedy MTP on NVIDIA exposes missing E4M3/BOOL ATen conversions, CUDA device changes during TP communicator teardown, and reference-only Prefill dispatch for head size 256.

This six-file patch:

  • Maps DataType::F8 and DataType::BOOL to existing ATen scalar types. No new conversion kernel.
  • Saves/restores the caller's CUDA device around ncclCommDestroy, so its existing runtime stream remains valid when an engine is destroyed and another is created.
  • Instantiates the existing paged Prefill warp kernel at head size 256 and enables that default on NVIDIA only. Existing default dispatch for other vendors and MLA is preserved; this is not a separate attention implementation.
  • Adds two focused cast checks and extends existing Prefill coverage with multi-page/long-context cases. Test allocation now scales with the actual shape rather than reserving 8192 pages for every case.

Validation

Fresh build from base 1ab85ef1 with this patch: release, NVIDIA SM86, ATen, CCL, graph, OpenMP and cuDNN. 2 × RTX A6000 48 GiB, driver 580.105.08; native CUDA Toolkit 12.4, Python 3.11.15, PyTorch 2.9.0+cu128. The isolated install was verified with ldd, then tested independently of the development checkout.

  • python test/infinicore/ops/paged_attention_prefill.py --nvidia: 88/88 passed, FP16/BF16 and int32/int64 metadata, including head size 256 and existing MLA cases.
  • python -m pytest -q test/infinicore/ops/fp8_cast.py: 2 passed, all finite E4M3 byte patterns and BOOL-to-float/int casts against PyTorch exactly.
  • Public C API smoke: two TP2 communicator groups, caller device 0 and 1 each preserved after every destroy.
  • Project formatting and whitespace checks passed.
  • InfiniLM integration on the matching combined runtime: 59 TP2 checks passed, 57 TP1 passed + 1 TP2-only skip; real 27B FP8 packed generation and cancel/re-admit outputs matched ordinary Decode references. This integration additionally uses graph-lifetime PR fix(graph): preserve recurrent graph inputs and allocation lifetimes #1560; the standalone operator tests above do not require it.

Saved logs, commands, exact revisions and measurement provenance

Saved local test output rendered for review; not a CI screenshot

Performance and scope

The associated LM MTP path previously measured 33.91 → 49.57, 33.48 → 53.29, and 30.03 → 48.61 generated tok/s against ordinary Decode graphs on TP2 A6000 (63/127/1023-token prompts, FP8 block/Marlin, BF16 activations, K=2 eager, 40×64-token pages, two repeats). These are whole-stack archived results, not speedups attributed solely to this Core patch. Full definitions/raw measurements are in the evidence link; no standalone kernel speed claim is made here.

No new CUDA Graph runtime, Mamba scan, or vendor-specific backend implementation is included. Other accelerators could not be tested because no allocated usable environment was available; their default Prefill dispatch is unchanged. Please review the shared header mapping for vendor build compatibility.

Review / CI

Per DEV.md, this contribution has a linked issue, issue/1565 branch and commit/title prefix, and is submitted from a fork. Requesting @PanZezhong1725 (paged Prefill) and @spike-zhu (maintainer) review. Fork push starts the existing CPU/Linux/Windows checks; external PR jobs may require maintainer approval.

Merge only after the required checks and reviewer approval. InfiniLM integration: InfiniTensor/InfiniLM#584.

Formal reviewer assignment was rejected by GitHub (RequestReviewsByLogin: insufficient upstream permissions). A maintainer needs to assign the two reviewers above. Fork Ruff passed; the Linux/Windows build and CPU tests are running: https://github.com/big-hip/InfiniCore/actions/runs/35444866036.

Upstream PR workflows currently report action_required and have not executed jobs; maintainer approval is required. Fork checks are reported separately above.

Map E4M3 and BOOL through the existing ATen adaptor and preserve the
caller's CUDA device across NCCL communicator destruction.

Reuse the existing paged Prefill warp kernel for NVIDIA head size 256,
without changing other vendors' default dispatch. Extend existing
multi-page/long-context coverage and add finite FP8/mask cast checks.

Validation: fresh SM86 build, 88 paged Prefill cases, 2 cast tests,
and TP2 communicator teardown from both caller devices.

Closes InfiniTensor#1565
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