[Pytorch] MOE Sequential Block - #3350
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Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
…h error handling tests Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
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Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
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Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
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Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
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Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
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…/TransformerEngine into enable_extra_out_consumption
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…TransformerEngine into dispatch_combine_op
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Signed-off-by: vthumbe <vthumbe@nvidia.com>
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…merEngine into dispatch_combine_op
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…merEngine into dispatch_combine_op
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| const int64_t *const first_dims_ptr = reinterpret_cast<const int64_t *>(input->first_dims.dptr); | ||
| const int64_t *const last_dims_ptr = reinterpret_cast<const int64_t *>(input->last_dims.dptr); | ||
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| // Prefer the rowwise representation when both GEMM orientations are available. |
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This newly supported path selects the rowwise data and scales when both grouped MXFP8 orientations are present, but the dequantization tests cover only each orientation separately and still state that both is invalid. Without a both case that verifies the intended rowwise selection, this behavior can regress without detection.
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Signed-off-by: vthumbe <vthumbe@nvidia.com>
Signed-off-by: Varun Thumbe <vthumbe@nvidia.com>
…TransformerEngine into dispatch_combine_op
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Signed-off-by: vthumbe <vthumbe@nvidia.com>
Signed-off-by: vthumbe <vthumbe@nvidia.com>
Signed-off-by: vthumbe <vthumbe@nvidia.com>
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