[dm][clk] fixup the work flow of CLK - #11673
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📌 Code Review Assignment🏷️ Tag: componentsReviewers: @Maihuanyi Changed Files (Click to expand)
📊 Current Review Status (Last Updated: 2026-08-01 16:39 CST)
📝 Review Instructions
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Add RT_CLK_F_SET_RATE_NO_REPARENT so clock providers can preserv the currently selected parent during rate changes. Round and re-read the effective clock rate after parent handling, skip redundant gate toggles and hardware programming when the target is already active, and fix error handling for parent-clock allocation failures. Signed-off-by: GuEe-GUI <2991707448@qq.com>
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拉取/合并请求描述：(PR description)
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Add RT_CLK_F_SET_RATE_NO_REPARENT so clock providers can preserv the currently selected parent during rate changes. Round and re-read the effective clock rate after parent handling, skip redundant gate toggles and hardware programming when the target is already active, and fix error handling for parent-clock allocation failures.
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我在这个拉取/合并请求中已经考虑了 As part of this pull request, I've considered the following:
#if 0代码，不包含已经被注释了的代码 All redundant code is removed and cleaned up