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28 changes: 28 additions & 0 deletions flow/designs/asap7/coralnpu/config.mk
Original file line number Diff line number Diff line change
@@ -0,0 +1,28 @@
export PLATFORM = asap7

export DESIGN_NICKNAME = coralnpu
export DESIGN_NAME = CoreMiniAxi

export VERILOG_FILES = $(DESIGN_HOME)/src/$(DESIGN_NICKNAME)/$(DESIGN_NAME).sv \
$(PLATFORM_DIR)/verilog/fakeram_512x128.sv \
$(PLATFORM_DIR)/verilog/fakeram_2048x128.sv

export VERILOG_DEFINES += -D USE_ASAP7

export ADDITIONAL_LEFS = $(PLATFORM_DIR)/lef/fakeram_512x128.lef \
$(PLATFORM_DIR)/lef/fakeram_2048x128.lef

export ADDITIONAL_LIBS += $(PLATFORM_DIR)/lib/NLDM/fakeram_512x128.lib \
$(PLATFORM_DIR)/lib/NLDM/fakeram_2048x128.lib

export SDC_FILE = $(DESIGN_HOME)/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

export SYNTH_HDL_FRONTEND ?= slang

export CORE_UTILIZATION = 65

export SYNTH_HIERARCHICAL = 1
export SYNTH_MINIMUM_KEEP_SIZE = 40000

export MACRO_PLACE_HALO = 2 2

9 changes: 9 additions & 0 deletions flow/designs/asap7/coralnpu/constraint.sdc
Original file line number Diff line number Diff line change
@@ -0,0 +1,9 @@
current_design CoreMiniAxi

set clk_name io_aclk
set clk_port_name io_aclk
set clk_period 10.00

set clk_port [get_ports $clk_port_name]

create_clock -period $clk_period -name $clk_name $clk_port
112 changes: 112 additions & 0 deletions flow/designs/asap7/coralnpu/rules-base.json
Original file line number Diff line number Diff line change
@@ -0,0 +1,112 @@
{
"synth__canonical_netlist__hash": {
"value": "5b7726241a901a54348af6b0ce1c968587bb8a7e",
"compare": "==",
"level": "warning"
},
"synth__netlist__hash": {
"value": "6df65a45ac029ad537f0d8e4702bad13af94c54e",
"compare": "==",
"level": "warning"
},
"synth__design__instance__area__stdcell": {
"value": 17800.0,
"compare": "<="
},
"constraints__clocks__count": {
"value": 1,
"compare": "=="
},
"placeopt__design__instance__area": {
"value": 37543,
"compare": "<="
},
"placeopt__design__instance__count__stdcell": {
"value": 198708,
"compare": "<="
},
"detailedplace__design__violations": {
"value": 0,
"compare": "=="
},
"cts__design__instance__count__setup_buffer": {
"value": 17279,
"compare": "<="
},
"cts__design__instance__count__hold_buffer": {
"value": 17279,
"compare": "<="
},
"cts__timing__setup__ws": {
"value": -1980.0,
"compare": ">="
},
"cts__timing__setup__tns": {
"value": -10200000.0,
"compare": ">="
},
"cts__timing__hold__ws": {
"value": -0.5,
"compare": ">="
},
"cts__timing__hold__tns": {
"value": -2.0,
"compare": ">="
},
"globalroute__antenna_diodes_count": {
"value": 174,
"compare": "<="
},
"globalroute__timing__setup__ws": {
"value": -2030.0,
"compare": ">="
},
"globalroute__timing__setup__tns": {
"value": -10500000.0,
"compare": ">="
},
"globalroute__timing__hold__ws": {
"value": -0.5,
"compare": ">="
},
"globalroute__timing__hold__tns": {
"value": -2.0,
"compare": ">="
},
"detailedroute__route__wirelength": {
"value": 1540518,
"compare": "<="
},
"detailedroute__route__drc_errors": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna__violating__nets": {
"value": 0,
"compare": "<="
},
"detailedroute__antenna_diodes_count": {
"value": 174,
"compare": "<="
},
"finish__timing__setup__ws": {
"value": -2070.0,
"compare": ">="
},
"finish__timing__setup__tns": {
"value": -10800000.0,
"compare": ">="
},
"finish__timing__hold__ws": {
"value": -0.5,
"compare": ">="
},
"finish__timing__hold__tns": {
"value": -2.0,
"compare": ">="
},
"finish__design__instance__area": {
"value": 37931,
"compare": "<="
}
}
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