fix dependency for vhdl instances inside (Sysytem) verilog modules - #979
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roynil wants to merge 8 commits into
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fix dependency for vhdl instances inside (Sysytem) verilog modules#979roynil wants to merge 8 commits into
roynil wants to merge 8 commits into
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_find_verilog_module_dependencies scans for vhdl primary units
Parse interfaces as modules
Prevents getting: # ** Error: error reading "stdin": interrupted system call # Error in macro /home/jenkins/.local/lib/python3.6/site-packages/vunit/sim_if/tcl_read_eval_loop.tcl line 12 # error reading "stdin": interrupted system call when running regression from Jenkins
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I have found that vunit don't build full dependency between verilog and vhdl #929.
I have updated project.py to also check if a instance is a VHDL-instance. I have also updated verilog/parser.py to parse interfaces as modules (which they basically are).
tox -e py38-unit,py38-acceptance-modelsim
passes (questa 2023.4) with the exception of tb_uart_lib.tb_uart_rx.test_receives_one_byte (due to #889)