[C++] Add RISC-V Vector (RVV) support and dynamic dispatch

[zhanchangbao-sanechips]

Rationale for this change

Add initial RISC-V Vector (RVV) support to Arrow C++. This mirrors the existing SVE dynamic-dispatch support on AArch64, paves the way for upcoming RVV‑related optimizations, providing:

• Runtime CPU capability detection for RVV and vector length (VLEN = 128/256/512 bits) on riscv64 Linux.
• A DispatchLevel::RVV entry so RVV-optimized kernels can be compiled with -march=rv64gcv and selected at runtime.
• CMake plumbing: ARROW_SIMD_LEVEL=RVV for compile-time RVV and ARROW_RUNTIME_SIMD_LEVEL=RVV|MAX for runtime dispatch, with graceful fallback (NONE) when the toolchain lacks RVV support.

What changes are included

• cpp/src/arrow/util/cpu_info.h/.cc: add RVV/RVV128/RVV256/RVV512 hardware flags; detect V extension via getauxval(AT_HWCAP) and VLEN via the vlenb CSR on Linux/riscv64.
• cpp/src/arrow/util/dispatch_internal.h: add DispatchLevel::RVV and ARROW_DISPATCH_TARGET_RVV macro, wired into
  DynamicDispatch::IsSupported.
• cpp/cmake_modules/DefineOptions.cmake: add RVV to ARROW_SIMD_LEVEL and ARROW_RUNTIME_SIMD_LEVEL option lists.
• cpp/cmake_modules/SetupCxxFlags.cmake: riscv64 handling — check -march=rv64gcv, set ARROW_HAVE_RVV (compile-time) / ARROW_HAVE_RUNTIME_RVV (runtime), default ARROW_SIMD_LEVEL=NONE.
• cpp/src/arrow/util/simd.h: include <riscv_vector.h> when RVV is enabled.
• cpp/src/arrow/util/io_util_test.cc: extend CpuInfo.Basic to assert RVV detection and a matching VLEN flag.

Are these changes tested?

Yes. Built and unit-tested on Sophgo SG2044 board with GCC 14.3.1.
Built with --DARROW_SIMD_LEVEL=RVV -DARROW_RUNTIME_SIMD_LEVEL=RVV, config passed.
All unittest passed.

Are there any user-facing changes?

No user-facing API changes; adds build-time options ARROW_SIMD_LEVEL=RVV and ARROW_RUNTIME_SIMD_LEVEL=RVV|MAX for riscv64.
GitHub Issue: #51334

[github-actions]

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[pitrou]

Hi @zhanchangbao-sanechips , as you probably have in seen the SVE-handling code above your changes, we are using xsimd for instruction set detection. Can we ask you to do that for RVV too?

(you may need to contribute the required additions to xsimd if not already available)

[zhanchangbao-sanechips]

Hi @zhanchangbao-sanechips , as you probably have in seen the SVE-handling code above your changes, we are using xsimd for instruction set detection. Can we ask you to do that for RVV too?

(you may need to contribute the required additions to xsimd if not already available)

I referred to my previous PR: apache/orc#2639. I will follow the same approach as the SVE handling and use xsimd for RVV instruction set detection.