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[dv,sram] Update SRAM vPlan with Metric Types - #697

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[dv,sram] Update SRAM vPlan with Metric Types#697
tchilikov-semify wants to merge 1 commit into
lowRISC:mainfrom
tchilikov-semify:axi_vplan

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Closes issue #696

Reference: qohtih
Description: The SRAM block should have four ports: clock / reset / AXI4 request in / AXI4 response out
Node_Type: metric
Metric_Type: assert

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You need to add everywhere one or multi "Item" otherwise the conversion will fail (I'll fix DVPlan as so far it silently fail). But we expect at least placeholders eventhough you don't know the final name

'''
Description: Confirm DUT parameterisation matches spec: AxiDataWidth = 64 (8-byte word), CapSize = 128-bit (16-byte capability), 1 CHERI tag bit per 128-bit aligned region, SramMemSize = 128 KiB
Node_Type: metric
Metric_Type: assert

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Do you plan to write an assertion in an "initial begin"? Maybe a formal test is more appropriated for these kind of things?

@@ -253,6 +275,7 @@
'''

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Here you mention a testcase and an assertion, so your Metric_Type should be assert, testcase

'''
Description: Both ruser flits of a valid capability read should be 1
Node_Type: metric
Metric_Type: testcase

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You mention a testcase but in comment you already mentioned an assertion, both are valid or only one of them?

{
Description: Functional coverage collection for the AXI SRAM
Node_Type: section_title
cg_tag_write:

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This should probably moved under the section "Tag_write"?

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