feat: add ModeVectorSet (VAdd / VSim / VRem)

[Code0987]

Design

docs/design/2026-09-04-mode-vector-set.md

Approved in chat (ok got it, lets continue). One product PR.

What landed

• New ModeVectorSet: VAdd / VRem / VSim / VCard / VDim / VEmb
• Keyspace VectorDim (0 = first add locks) and VectorMetric (cosine default, L2, IP)
• Snapshot fan-out on last uint32 flag (1<<31) plus 'S'/'A'/'R' payload prefix
• Feature folders: pkg/vecset + pkg/vecset/eng, thin pkg/engine/vecset.go
• Proto, client, cacheserver, sc (vadd/vsim/…), product docs, examples/vecset

Not in this PR: stock-node demo keyspace, HNSW, per-query metric.

Tests

go test ./...

Local micros (200ms, count=1): BenchmarkEngineGetHit 15 allocs/op, BenchmarkStoreGetHit 2 allocs/op (flat).

Bench risk

Hot path? No. Get/Put do not decode vector sets. New micros BenchmarkStoreVAdd / BenchmarkStoreVSim are report-only. Shared smoke/micro ±10%; Get-hit / StoreGetHit allocs must not rise.

[github-actions]

SuperCache bench vs main

Both sides ran once on this same GitHub runner (main, then this PR). Not a merge gate.

Baseline: 7f12011 (2026-09-06T11:37:35Z) → this run: 7f12011 (2026-09-06T11:36:51Z)

scbench smoke

cell	ops/s (main → PR)	Δ ops/s	p50	p99
get/hit n=1 c=1 uniform	11738 → 11620	-1.0%	84µs → 85µs	150µs → 155µs
get/hit n=1 c=10 uniform	44111 → 43697	-0.9%	208µs → 209µs	614µs → 623µs
get/hit n=3 c=10 uniform	48664 → 49770	+2.3%	178µs → 176µs	779µs → 703µs
miss/miss-cacheonly n=1 c=1 uniform	11287 → 11105	-1.6%	87µs → 87µs	171µs → 228µs
miss/miss-cacheonly n=1 c=10 uniform	44559 → 44397	-0.4%	204µs → 204µs	648µs → 655µs
set/put n=1 c=1 uniform	11264 → 11184	-0.7%	87µs → 87µs	168µs → 193µs
set/put n=1 c=10 uniform	41401 → 42072	+1.6%	220µs → 217µs	664µs → 650µs

Δ ops/s: green-ish is higher throughput. Latency: lower is better.

go test -bench (ns/op)

benchmark	ns/op (main → PR)	Δ	allocs/op
BenchmarkEngineDelete	600 → 591	-1.6%	6 → 6
BenchmarkEngineGetHit	978 → 992	+1.4%	15 → 15
BenchmarkEngineGetHitParallel	974 → 980	+0.5%	15 → 15
BenchmarkEngineGetMissCacheOnly	666 → 660	-0.9%	14 → 14
BenchmarkEngineGetMissCacheOnlyParallel	505 → 503	-0.5%	14 → 14
BenchmarkEngineGetMissLoadThrough	1235 → 1271	+2.9%	24 → 24
BenchmarkEngineGetMissLoadThroughParallel	1397 → 1380	-1.2%	23 → 23
BenchmarkEnginePut	1257 → 1225	-2.5%	18 → 18
BenchmarkEnginePutParallel	1105 → 1138	+3.0%	18 → 18
BenchmarkStoreBitSet	87 → 87	+0.1%	1 → 1
BenchmarkStoreCGetHit	56 → 56	+0.3%	0 → 0
BenchmarkStoreCIncr	78 → 79	+1.1%	1 → 1
BenchmarkStoreCMSIncr	94 → 94	+0.1%	0 → 0
BenchmarkStoreCMSIncrN	93 → 94	+0.2%	0 → 0
BenchmarkStoreGeoAdd	7185 → 7433	+3.5%	2 → 2
BenchmarkStoreGeoPosHit	69 → 68	-0.4%	0 → 0
BenchmarkStoreGeoPosMiss	68 → 75	+11.0%	0 → 0
BenchmarkStoreGetHit	224 → 226	+0.8%	2 → 2
BenchmarkStoreGetHitParallel	264 → 282	+6.6%	2 → 2
BenchmarkStoreHGetHit	71 → 71	+0.1%	1 → 1
BenchmarkStoreHGetMiss	66 → 74	+12.5%	0 → 0
BenchmarkStoreHLLAdd	77 → 78	+1.0%	0 → 0
BenchmarkStoreHSet	8236 → 8257	+0.3%	3 → 3
BenchmarkStoreJsonSet	20227 → 21005	+3.8%	207 → 207
BenchmarkStorePut	231 → 236	+2.4%	2 → 2
BenchmarkStorePutParallel	269 → 264	-1.6%	2 → 2
BenchmarkStoreSetAdd	7148 → 7385	+3.3%	2 → 2
BenchmarkStoreSetContainsHit	68 → 70	+3.0%	0 → 0
BenchmarkStoreSetContainsMiss	66 → 73	+10.6%	0 → 0
BenchmarkStoreTopKAdd	762 → 784	+2.8%	20 → 20
BenchmarkStoreVAdd	— → 85378	n/a	514
BenchmarkStoreVSim	— → 70200	n/a	530
BenchmarkStoreZAdd	7422 → 7672	+3.4%	2 → 2
BenchmarkStoreZScoreHit	69 → 72	+5.4%	0 → 0
BenchmarkStoreZScoreMiss	67 → 68	+1.2%	0 → 0

_{Posted by CI bench job. Not a merge gate.}