docs(g6_03/g6_06): Mode 4 gain heritage, analog-input calibration commands 0xA5–0xA7, 0xA_ block allocation rule, capability bit 6 ai_cal

[mbreiser]

Spec sync for the analog-input work in LED-Display_G6_Firmware_Arena (#46 F1, #47 F2) and Arena Studio v0.74/v0.75 (webDisplayTools #190/#191). Plan and rationale: webDisplayTools docs/development/analog-input-plan.md (PR #189). @loeschef — the opcode and capability-bit choices are the parts to review.

g6_03-controller.md

• Mode 4 gain, corrected. The formula fps = V × 100 × gain / 10 was already here, but the worked example ("−20 = −2.0 fps/V") contradicted it. Traced to the G3 Xmega controller (XmegaController/main.c: xRate = gain × HzFromAdc / 10, HzFromAdc = 100 per volt, xRate is fps): the gain byte is 10× the gain and unity (10) = 100 fps per volt; the everyday G3 gains 0.2–0.5 (2–5) are 20–50 fps/V; −20 is −200 fps/V. Firmware F1 now implements exactly this (the shipped code had omitted the ×100). Mode 4 text also gains the 12-bit / 16× averaging, the G3-style EWMA, the per-board calibration and the deadband. Same fix in the trial-params gain row.
• 0xA_ block allocation rule (new paragraph in "G4 opcode compatibility"): 0xA0–0xA3 analog out, 0xA4–0xA9 analog in, 0xAA–0xAF digital I/O; set/get pairs on adjacent even/odd opcodes (A0/A1, A6/A7, AA/AB, AC/AD; A2/A3 the set-only pair); 0xA8/0xA9 reserved for the sampled analog block stream; 0xAE/0xAF free. G4 never used 0xA0–0xAF (checked against maDisplayTools' PanelsController.m command bytes and the reserved list here).
• New commands, table rows + per-command sections: 0xA5 get-analog-in-raw, 0xA6 set-analog-cal (two-point recipe: BNC open = +10 V reference via the 10k pull-up, BNC ground cap = 0 V; 256 averaged reads per point; validity rule; EEPROM authoritative + write-only SD JSON mirror; deadband; the procedure), 0xA7 get-analog-cal (18-byte record). 0xA4 gains its flags byte (calibrated ch1/ch2, 12-bit) and the calibrated-mV semantics.
• Capability bitmap: bit 6 = ai_cal (same gating rule as io_ext). Bit 7 is the last bit of the byte — documented as reserved with a proposed extension rule for review: bit 7 = cap_ext ⇒ a second capability byte follows the MAC at payload byte 8 (the same tolerant-extension pattern the MAC uses; version stays 1). The § 5 summary bullet is updated to match (it still said bits 6–7 reserved and showed the pre-MAC response).

g6_06-arena-firmware-interface.md

• Mode 4 wiring bullet corrected the same way, plus a new bullet recording the analog-input front-end fault and fix (stage-2 divider resistors swapped on both channels; A0: R180 = 20k / R178 = 10k, A1: R181 = 20k / R179 = 10k; Will, 2026-08-27; LAB-209) with the ground-cap bench check.

Not touched: the panel protocol, the pattern format, anything below 0xA0 or above 0xAF except the 0xC2 capability table.

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